CN101197299A - Film stress detecting method - Google Patents
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- CN101197299A CN101197299A CNA2006101193651A CN200610119365A CN101197299A CN 101197299 A CN101197299 A CN 101197299A CN A2006101193651 A CNA2006101193651 A CN A2006101193651A CN 200610119365 A CN200610119365 A CN 200610119365A CN 101197299 A CN101197299 A CN 101197299A
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Abstract
A film layer stress detection method comprises the following steps that: a patterned film layer is formed on a semiconductor substrate which comprises an alignment mark; the patterned film layer comprises a counterpoint mark or a measuring mark; with the alignment mark, the counterpoint mark and/or the measuring mark, the counterpoint operating deviation information of the corresponding areas of different counterpoint mark and/or measuring mark in the film layer is achieved; a counterpoint operating deviation standard of the film layer is determined; according to the counterpoint operating deviation standard of the film layer, the counterpoint operating deviation information of the corresponding areas of different counterpoint mark and/or measuring mark in the film layer is distinguished. With the method, the film layer stress can achieve online detection without adding separate detection procedures; the overproof stress information of different areas of the film layer can be provided; the waste chip loss and the production cost are reduced; the testing result has no relation with other parameters of the film layer.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a kind of film stress detecting method.
Background technology
For satisfying the needs of device miniaturization development, ic manufacturing technology adopts multi-layer film structure usually.Usually, the film with sandwich construction because of in its layer or the lattice mismatch of interlayer produce internal membrane stress.In addition, for example elasticity, thermal expansion etc. also can cause the generation of internal membrane stress to the characteristic of different materials.Excessive membrane stress usually causes the serious degradation of film material property, when serious, even cause component failure, as, for dynamic random access memory (DRAM) chip, because the lattice that excessive membrane stress causes dislocation may cause the variation of signal of telecommunication retention time.Therefore, in actual production process, need carry out the membrane stress test, and should be with its control within the specific limits.
At present use the widest membrane stress method of testing to be bending-plate measuring methodology, after promptly measuring the radius of curvature of film deposit front and back wafer by optical interdferometer or surface profiler, utilize the Stoney formula to calculate the stress value of film, again this stress value and preset standard are compared, judge whether the membrane stress value satisfies product requirement.The method is simply suitable, and the other materials parameter of stress value and film is irrelevant, but utilizes this method can only judge whether the mean stress value of film exceeds preset standard, and can't judge the particular location that the film internal stress exceeds standard; And along with the error that reduces of thickness increases, resolution also sharply reduces, and is not suitable for and measures the film of thickness less than 100 nanometers (nm).
Application number provides a kind of highly sensitive film stress test method in the Chinese patent application of " 200510126258.7 ", and this method is by carrying out substrate thinning on a plurality of locals on the substrate; Then deposition film material on substrate; Then, etched substrate makes the substrate behind the attenuate form hanging structure, and measures the radius of curvature of the hanging structure of deposition film; Subsequently, remove film, measure the radius of curvature of hanging structure; At last, the radius of curvature according to the hanging structure before and after the thin film deposition calculates membrane stress.Obviously, use this method and carry out membrane stress when test, though can carry out stress to optional position in the film detects, and can guarantee that this test has high sensitivity, when carrying out the membrane stress test, this method needs in substrate, to form hanging structure but use, complex manufacturing technology, and be destructive detection method, can't realize online detection.
The patent No. is for providing a kind of method of measuring internal membrane stress with high lateral resolution in the Chinese patent of " 99102479.6 ", this method is by obtaining ellipse of revolution and measure internal membrane stress with high lateral resolution by measuring the relative photo mathematic(al) parameter when rotating sample, promptly by sample being rotated the α angle, and in selected sample area, measure one group of elliptic parameter as αHan Shuo, then set up the calibration curve that concerns between one group of first elliptic parameter amplitude of expression and one group of first stress value, rotate to need measure the sample of stress then, at one group of second elliptic parameter of the selection area measuring samples of sample to determine the second oval amplitude.From calibration curve, determine that as index the internal stress of selected sample area is to determine corresponding stress value according to calibration curve with the second oval amplitude then.This stress value is determined according to the selected district of dielectric tensors, stress optical coefficient tensor and sample place's thickness.Obviously, can carry out the stress detection to optional position in the film though use this inventive method, and can guarantee that this test has high sensitivity, but the sensitivity of the stress value that records depends on the selected district of sample place's thickness, and the accurate measurement of the selected district of sample place's thickness is difficult for realizing aborning.
Thus, how to provide a kind of membrane stress detection method that had not only had high sensitivity but also can provide different subregion stress in the film to exceed standard information to become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The invention provides a kind of film stress detecting method, can have high sensitivity and can provide different alignment marks in the rete and/or the stress of the measurement markers corresponding region information that exceeds standard.
A kind of film stress detecting method provided by the invention comprises:
Form the rete of patterning on Semiconductor substrate, described Semiconductor substrate comprises alignment mark, comprises alignment mark and/or measurement markers in the rete of described patterning;
Utilize described alignment mark, alignment mark and/or measurement markers obtain different alignment marks in the rete and/or measurement markers corresponding region to bit manipulation off normal information;
Determine that rete is to bit manipulation off normal standard;
According to described rete to bit manipulation off normal standard differentiate different alignment marks in the described rete and/or measurement markers corresponding region to bit manipulation off normal information; Described when the bit manipulation off normal is exceeded this standard, judge that described different alignment mark and/or measurement markers corresponding region stress in thin film do not satisfy product requirement; Described when the bit manipulation off normal is satisfied this standard, judge that then described different alignment mark and/or measurement markers corresponding region stress in thin film satisfy product requirement.
Described rete comprises homogeneous material layer or mixed material layer; Described to bit manipulation comprise between rete between bit manipulation and rete and substrate to bit manipulation; Between described rete to bit manipulation comprise that the alignment mark that utilizes in the different retes carries out to bit manipulation; Between described rete and substrate to bit manipulation comprise that the alignment mark that utilizes in the rete and the alignment mark in the Semiconductor substrate carry out to bit manipulation; Deviation or alignment mark in the rete and the deviation between the alignment mark in the Semiconductor substrate between the described alignment mark that bit manipulation off normal information is comprised in the different retes that obtain when utilizing exposure device to carry out to bit manipulation; Deviation between the described measurement markers that bit manipulation off normal information is comprised in the different retes that obtain when utilization is carried out bit manipulation to level detecting apparatus; Described bit manipulation off normal information is included in that exposure registers report or contraposition detects and to register report; Described to bit manipulation off normal information comprise in the two dimensional surface between the measurement markers between the alignment mark in the different retes, in the different rete or between alignment mark in the rete and the alignment mark in the Semiconductor substrate laterally, length travel deviation and angular deviation represent; Described stress in thin film criterion comprise described laterally or the length travel deviation all be less than or equal to 10 nanometers; Described stress in thin film criterion comprises that described angular deviation is less than or equal to 30 degree.
Compared with prior art, the present invention has the following advantages:
1. utilize bit manipulation off normal information is carried out stress in thin film detecting of different alignment marks in the rete and/or measurement markers corresponding region, the stress of different alignment marks in the rete and/or the measurement markers corresponding region information that exceeds standard can be provided, and described different alignment marks of decidable and/or measurement markers corresponding region stress in thin film satisfy or do not satisfy product requirement then;
2. with described bit manipulation off normal information is applied to the stress in thin film testing process, has expanded the described processing procedure scope that bit manipulation off normal information is optimized technology of utilizing;
3. utilize by exposure device or to the off normal information of different alignment marks and/or measurement markers corresponding region in the level detecting apparatus acquisition rete and carry out the stress in thin film detection, can realize the online detection of stress in thin film and need not to increase independent detection step;
4. the area information that exceeds standard according to the rete internal stress promptly accounts for the long-pending ratio of film surface according to the rete internal stress zone that exceeds standard, and need can judge whether the Semiconductor substrate that this stress in thin film exceed standard done to scrap processing, has reduced useless sheet loss, has reduced production cost;
5. test has high sensitivity, and test result and other parameters of rete have nothing to do.
Description of drawings
Fig. 1 is the stress in thin film testing process schematic diagram of the explanation embodiment of the invention;
Fig. 2 is the semiconductor substrate surface structural representation of the explanation embodiment of the invention;
Fig. 3 is the semiconductor substrate surface rete internal labeling distribution schematic diagram of the explanation embodiment of the invention;
Fig. 4 A～4B is measurement markers schematic diagram in the rete of the explanation embodiment of the invention;
Fig. 5 is the contraposition off normal testing result schematic diagram of the explanation embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The step that application the inventive method is carried out the stress in thin film detection comprises: form the rete of patterning on Semiconductor substrate, described Semiconductor substrate comprises alignment mark, comprises alignment mark and/or measurement markers in the rete of described patterning; Utilize described alignment mark, alignment mark and/or measurement markers obtain different alignment marks in the rete and/or measurement markers corresponding region to bit manipulation off normal information; Determine that rete is to bit manipulation off normal standard; According to described rete to bit manipulation off normal standard differentiate different alignment marks in the described rete and/or measurement markers corresponding region to bit manipulation off normal information; Described when the bit manipulation off normal is exceeded this standard, judge that described different alignment mark and/or measurement markers corresponding region stress in thin film do not satisfy product requirement; Described when the bit manipulation off normal is satisfied this standard, judge that then described different alignment mark and/or measurement markers corresponding region stress in thin film satisfy product requirement.
Should be noted that the term of Shi Yonging " rete " means homogeneous material or the mixed material layer with level and smooth or flat surface in this article, and can exchange with term " film " or " film ".Term " contraposition " reaches " aligning " and means when forming rete or multiple film layer structure, operates for forming the benchmark that good fit carries out between subsequent film and preceding step rete or between rete and Semiconductor substrate.
Usually, the contraposition deviation exceeds standard and is considered to because the abnormal conditions in the production process cause, and is provided with unusual or because the variation of the process conditions that other condition influence cause etc. as technological parameter.Be often used as the reference items that technological parameter is provided with by the contraposition deviation information that obtains that exceeds standard.
But, consider, stress in thin film is excessive may to cause alignment mark and/or measurement markers in the rete to produce damage or distortion, and the damage of this alignment mark and/or measurement markers or distortion will change original contraposition deviation, and promptly described contraposition deviation is relevant with the distribution situation of rete internal stress.Thus, with described bit manipulation off normal information is applied in the testing process of stress in thin film among the present invention, has expanded the described processing procedure scope that bit manipulation off normal information is optimized technology of utilizing.
System to bit manipulation off normal information in the described acquisition rete comprises that exposure device (scanner) reaches level detecting apparatus (overlay).Described exposure device can be provided as the rete that forms patterning when carrying out bit manipulation to bit manipulation off normal information; Described to level detecting apparatus in order to provide behind the rete patterning to bit manipulation off normal information.Utilization is carried out the stress in thin film detection by exposure device or to the off normal information of different alignment marks and/or measurement markers corresponding region in the level detecting apparatus acquisition rete, can realize the online detection of stress in thin film and need not to increase independent detection step.
Fig. 1 is the stress in thin film testing process schematic diagram of the explanation embodiment of the invention, and as shown in Figure 1, as embodiments of the invention, the concrete steps that application the inventive method is carried out the stress in thin film detection comprise:
At first, on Semiconductor substrate, carry out the deposition-photoetching-etch step of rete, obtain the rete of patterning.
Fig. 2 is the semiconductor substrate surface structural representation of the explanation embodiment of the invention, as shown in Figure 2, comprise graph area 11 and non-graph area 12 in the described Semiconductor substrate 10, described graph area 11 is in order to make device products, described non-graph area 12 is in order to accept the various marks that need use in the actual production process, as alignment mark 13, alignment mark and measurement markers etc., and after finishing, device provides cutting channel.Described alignment mark 13 utilizes described exposure device to form the rete of patterning and the required loci that is positioned at the non-graph area of described Semiconductor substrate when carrying out bit manipulation in order to provide.
Fig. 3 is the semiconductor substrate surface rete internal labeling distribution schematic diagram of the explanation embodiment of the invention, as shown in Figure 3, described alignment mark 20 utilizes described exposure device to form the rete of patterning and the required loci that is positioned at described rete when carrying out bit manipulation in order to provide; Described measurement markers 30 is describedly carried out contraposition off normal required loci that is positioned at described rete when detecting to level detecting apparatus in order to provide to utilize.Comprise at least one alignment mark 20 and at least one measurement markers 30 in the rete of described patterning, described alignment mark 20 and measurement markers 30 are positioned at the non-graph area of Semiconductor substrate top, and are uniformly distributed in the rete.Be symmetrically distributed with at least one described measurement markers 30 around the described alignment mark 20.
The method of described deposition-photoetching-each rete of etching can adopt any traditional method, and the technical scheme that relates under any circumstance all is not considered part of the present invention, does not repeat them here.
Then, utilize described alignment mark, alignment mark and/or measurement markers obtain different alignment marks in the rete and/or measurement markers corresponding region to bit manipulation off normal information.
Different alignment marks and/or measurement markers corresponding region comprise the interval region between the same tag that any one mark in described at least one alignment mark and/or the measurement markers is adjacent in the described rete; Interval region between described same tag comprises the interval region between the measurement markers that interval region between the alignment mark that described alignment mark is adjacent and/or described measurement markers be adjacent, and relative position is identical between described measurement markers and the described measurement markers that is adjacent and each self-corresponding described alignment mark.
In the production practices, actual utilizes described exposure device to carry out to bit manipulation, but describedly can or describedly obtain level detecting apparatus by described exposure device bit manipulation off normal information.When utilizing described exposure device to be provided as to form the rete of patterning to carry out to bit manipulation to bit manipulation off normal information; Utilize described to level detecting apparatus in order to provide behind the rete patterning to bit manipulation off normal information.
It is described during to bit manipulation off normal information to utilize described exposure device to obtain, and obtains by measuring in the contraposition operating process deviation between the alignment mark in the different retes or the alignment mark in the rete and the deviation between the alignment mark in the Semiconductor substrate; Utilize describedly level detecting apparatus to be obtained described during, obtain by the deviation of measuring between the measurement markers in the different retes to bit manipulation off normal information.
Alignment mark in the described rete and the alignment mark in the described Semiconductor substrate have diagrammatic representation usually, described figure can be selected a kind of in representing of cross, terraced font or fork-shaped figures for use, by measuring deviation or alignment mark in the rete and the deviation between the alignment mark in the Semiconductor substrate between the alignment mark in the different retes in the contraposition operating process, it is described to bit manipulation off normal information to utilize described exposure device to obtain.
Measurement markers in the described rete is generally the block pattern with first size or second size, Fig. 4 A～4B is measurement markers schematic diagram in the rete of the explanation embodiment of the invention, shown in Fig. 4 A and 4B, carry out that the measurement markers of two retes of bit manipulation is had the first size 31 and second size 32 respectively.Measure the deviation between described measurement markers with first size 31 and second size 32, can utilize describedly to obtain described bit manipulation off normal information to level detecting apparatus.
Fig. 5 is the contraposition off normal testing result schematic diagram of the explanation embodiment of the invention, described carrying out the measurement markers of two retes with first size 31 and second size 32 of bit manipulation with mode fit as shown in Figure 5.
Obviously; described alignment mark; the shape of alignment mark and measurement markers and be of a size of and be convenient to concrete enforcement of the present invention and can do any selection; utilize described exposure device and described level detecting apparatus is obtained the method for contraposition deviation between different retes and can adopt any traditional method; the technical scheme that relates under any circumstance all is not considered part of the present invention; should be with above-mentioned execution mode as qualification to the inventive method execution mode; rational arbitrarily modification and equivalents that those skilled in the art make this do not influence the enforcement of the inventive method, and should be included in protection scope of the present invention.
As the first embodiment of the present invention, described to bit manipulation comprise between any two retes to bit manipulation.Described rete obtains by exposure device (scanner) or to level detecting apparatus (overlay) bit manipulation off normal information.The rete that obtains by exposure device is included in during exposure registers report bit manipulation off normal information, and described is off normal information between alignment mark in the different retes to bit manipulation off normal information; By rete that level detecting apparatus is obtained bit manipulation off normal information is included in contraposition and detects and register report, described is off normal information between measurement markers in the different retes to bit manipulation off normal information.
Described rete to bit manipulation off normal information comprise in the two dimensional surface between the alignment mark in the different retes or between measurement markers laterally, length travel deviation and angular deviation represent that its deviate is designated as X, Y and R respectively.
Consider the influence of mechanical factor, described contraposition deviation is the contraposition deviation that records through after the contraposition compensation, and the generation of promptly described contraposition deviation is only relevant with film material character.
At last, determine that rete is to bit manipulation off normal standard; According to described rete to bit manipulation off normal standard differentiate different alignment marks in the described rete and/or measurement markers corresponding region to bit manipulation off normal information; Described when the bit manipulation off normal is exceeded this standard, judge that described different alignment mark and/or measurement markers corresponding region stress in thin film do not satisfy product requirement; Described when the bit manipulation off normal is satisfied this standard, judge that then described different alignment mark and/or measurement markers corresponding region stress in thin film satisfy product requirement.
In the described rete bit manipulation off normal standard is determined according to process conditions and product requirement.As the first embodiment of the present invention, described stress in thin film criterion is between alignment mark in the different retes or the horizontal or vertical alignment mark deviation between measurement markers all is less than or equal to 10nm; Between the alignment mark in the different retes or the angular deviation between measurement markers be less than or equal to 30 °.
As the second embodiment of the present invention, the concrete steps that application the inventive method is carried out the stress in thin film detection comprise:
At first, on Semiconductor substrate, carry out the deposition-photoetching-etch step of rete, obtain the rete of patterning.
Comprise graph area and non-graph area in the described Semiconductor substrate, described graph area is in order to make device products, described non-graph area as alignment mark and measurement markers etc., and provides cutting channel in order to accept the various marks that need use in the actual production process after device is finished.Comprise alignment mark in the non-graph area of described Semiconductor substrate.Described alignment mark utilizes described exposure device to form the rete of patterning and the required loci that is positioned at the non-graph area of described Semiconductor substrate when carrying out bit manipulation in order to provide.As the second embodiment of the present invention, described to bit manipulation comprise between any rete and described Semiconductor substrate to bit manipulation.
Comprise at least one alignment mark and at least one measurement markers in the rete of described patterning, described alignment mark and measurement markers are positioned at the non-graph area of Semiconductor substrate, and are uniformly distributed in the rete.Described alignment mark utilizes described exposure device to form the rete of patterning and the required loci that is positioned at described rete when carrying out bit manipulation in order to provide; Described measurement markers is describedly carried out contraposition off normal required loci that is positioned at described rete when detecting to level detecting apparatus in order to provide to utilize.Be symmetrically distributed with at least one described measurement markers around the described alignment mark.Between described rete and substrate to bit manipulation comprise that the alignment mark that utilizes in the rete and the alignment mark in the Semiconductor substrate carry out to bit manipulation.
The method of described deposition-photoetching-each rete of etching can adopt any traditional method, and the technical scheme that relates under any circumstance all is not considered part of the present invention, does not repeat them here.
Then, utilize described alignment mark, alignment mark and/or measurement markers obtain different alignment marks in the rete and/or measurement markers corresponding region to bit manipulation off normal information.
As the second embodiment of the present invention, the deviation between the measurement markers in the different retes that deviation between the described alignment mark that bit manipulation off normal information is comprised in the alignment mark that utilizes in the rete that described exposure device obtains and the Semiconductor substrate and utilization obtain when carrying out bit manipulation to level detecting apparatus.
The rete that obtains by described exposure device is included in during exposure registers report bit manipulation off normal information, by rete that level detecting apparatus is obtained bit manipulation off normal information is included in contraposition and detects and register report.Described rete to bit manipulation off normal information comprise between alignment mark in alignment mark and the Semiconductor substrate in the described rete or between the measurement markers in the different rete laterally, length travel deviation and angular deviation represent that its deviate is designated as X, Y and R respectively.
Consider the influence of mechanical factor, described contraposition deviation is the contraposition deviation that records through after the contraposition compensation, and the generation of promptly described contraposition deviation is only relevant with film material character.
At last, determine that rete is to bit manipulation off normal standard; According to described rete to bit manipulation off normal standard differentiate different alignment marks in the described rete and/or measurement markers corresponding region to bit manipulation off normal information; Described when the bit manipulation off normal is exceeded this standard, judge that described different alignment mark and/or measurement markers corresponding region stress in thin film do not satisfy product requirement; Described when the bit manipulation off normal is satisfied this standard, judge that then described different alignment mark and/or measurement markers corresponding region stress in thin film satisfy product requirement.
In the described rete bit manipulation off normal standard is determined according to process conditions and product requirement.As the second embodiment of the present invention, described stress in thin film criterion be between alignment mark in alignment mark and the Semiconductor substrate in the described rete or between the measurement markers in the different rete laterally, the length travel deviation all is less than or equal to 10 nanometers (nm); Between the alignment mark in the alignment mark in the described rete and the Semiconductor substrate or the angular deviation between the measurement markers in the different rete be less than or equal to 30 °.
As seen, adopt the inventive method, the area information that can exceed standard according to the rete internal stress, promptly account for the long-pending ratio of film surface according to the rete internal stress zone that exceeds standard, can judge whether to need the Semiconductor substrate that this stress in thin film exceed standard done and scrap processing, reduce useless sheet loss, reduce production cost; And test has high sensitivity, and test result and other parameters of rete have nothing to do.
What need emphasize is; obtain rete to being relatively independent detection step to bit manipulation off normal standard in bit manipulation off normal information and the definite rete; its conversion of carrying out order does not influence the enforcement of the inventive method; obviously; order to above-mentioned detection step is changed; can be used as the 3rd embodiment and the 4th embodiment of the inventive method, all should be included in protection scope of the present invention.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (9)
1. film stress detecting method comprises:
Form the rete of patterning on Semiconductor substrate, described Semiconductor substrate comprises alignment mark, comprises alignment mark and/or measurement markers in the rete of described patterning;
Utilize described alignment mark, alignment mark and/or measurement markers obtain different alignment marks in the rete and/or measurement markers corresponding region to bit manipulation off normal information;
Determine that rete is to bit manipulation off normal standard;
According to described rete to bit manipulation off normal standard differentiate different alignment marks in the described rete and/or measurement markers corresponding region to bit manipulation off normal information; Described when the bit manipulation off normal is exceeded this standard, judge that described different alignment mark and/or measurement markers corresponding region stress in thin film do not satisfy product requirement; Described when the bit manipulation off normal is satisfied this standard, judge that then described different alignment mark and/or measurement markers corresponding region stress in thin film satisfy product requirement.
2. film stress detecting method according to claim 1 is characterized in that: described rete comprises homogeneous material layer or mixed material layer.
3. film stress detecting method according to claim 1 and 2 is characterized in that: described to bit manipulation comprise between rete between bit manipulation and rete and substrate to bit manipulation; Between described rete to bit manipulation comprise that the alignment mark that utilizes in the different retes carries out to bit manipulation; Between described rete and substrate to bit manipulation comprise that the alignment mark that utilizes in the rete and the alignment mark in the Semiconductor substrate carry out to bit manipulation.
4. film stress detecting method according to claim 1 is characterized in that: deviation or alignment mark in the rete and the deviation between the alignment mark in the Semiconductor substrate between the described alignment mark that bit manipulation off normal information is comprised in the different retes that obtain when utilizing exposure device to carry out bit manipulation.
5. film stress detecting method according to claim 1 is characterized in that: the deviation between the described measurement markers that bit manipulation off normal information is comprised in the different retes that obtain when utilization is carried out bit manipulation to level detecting apparatus.
6. according to claim 1 or 4 or 5 described film stress detecting methods, it is characterized in that: described bit manipulation off normal information is included in that exposure registers report or contraposition detects and to register report.
7. film stress detecting method according to claim 6 is characterized in that: described to bit manipulation off normal information comprise in the two dimensional surface between the measurement markers between the alignment mark in the different retes, in the different rete or between alignment mark in the rete and the alignment mark in the Semiconductor substrate laterally, length travel deviation and angular deviation represent.
8. film stress detecting method according to claim 7 is characterized in that: described stress in thin film criterion comprise described laterally or the length travel deviation all be less than or equal to 10 nanometers.
9. film stress detecting method according to claim 7 is characterized in that: described stress in thin film criterion comprises that described angular deviation is less than or equal to 30 degree.
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| CNB2006101193651A CN100468681C (en) | 2006-12-08 | 2006-12-08 | Film stress detecting method |
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| CNB2006101193651A CN100468681C (en) | 2006-12-08 | 2006-12-08 | Film stress detecting method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102549734A (en) * | 2009-09-21 | 2012-07-04 | 国际商业机器公司 | In-line characterization |
| CN104576429A (en) * | 2013-10-24 | 2015-04-29 | 北大方正集团有限公司 | Method and system for measuring stress of thin film layer |
| CN107560521A (en) * | 2017-08-18 | 2018-01-09 | 武汉华星光电半导体显示技术有限公司 | A kind of stacking accuracy measurement method at high offset interface and application |
| CN108292110A (en) * | 2015-10-02 | 2018-07-17 | 应用材料公司 | Overlay error corrects |
| CN116288226A (en) * | 2023-05-23 | 2023-06-23 | 江西兆驰半导体有限公司 | Electron beam evaporation metal film stress monitoring method |
| CN116543052A (en) * | 2023-06-15 | 2023-08-04 | 深圳荣耀智能机器有限公司 | Alignment deviation processing method and electronic equipment |
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2006
- 2006-12-08 CN CNB2006101193651A patent/CN100468681C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102549734A (en) * | 2009-09-21 | 2012-07-04 | 国际商业机器公司 | In-line characterization |
| CN102549734B (en) * | 2009-09-21 | 2014-08-13 | 国际商业机器公司 | In-line characterization |
| CN104576429A (en) * | 2013-10-24 | 2015-04-29 | 北大方正集团有限公司 | Method and system for measuring stress of thin film layer |
| CN108292110A (en) * | 2015-10-02 | 2018-07-17 | 应用材料公司 | Overlay error corrects |
| CN108292110B (en) * | 2015-10-02 | 2020-08-18 | 应用材料公司 | Overlay error correction |
| CN107560521A (en) * | 2017-08-18 | 2018-01-09 | 武汉华星光电半导体显示技术有限公司 | A kind of stacking accuracy measurement method at high offset interface and application |
| CN116288226A (en) * | 2023-05-23 | 2023-06-23 | 江西兆驰半导体有限公司 | Electron beam evaporation metal film stress monitoring method |
| CN116288226B (en) * | 2023-05-23 | 2023-08-18 | 江西兆驰半导体有限公司 | Electron beam evaporation metal film stress monitoring method |
| CN116543052A (en) * | 2023-06-15 | 2023-08-04 | 深圳荣耀智能机器有限公司 | Alignment deviation processing method and electronic equipment |
| CN116543052B (en) * | 2023-06-15 | 2023-11-10 | 深圳荣耀智能机器有限公司 | Alignment deviation processing method and electronic equipment |
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| CN100468681C (en) | 2009-03-11 |
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