CN115602540B - Manufacturing method of enhanced GaN power device - Google Patents
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- CN115602540B CN115602540B CN202211495729.1A CN202211495729A CN115602540B CN 115602540 B CN115602540 B CN 115602540B CN 202211495729 A CN202211495729 A CN 202211495729A CN 115602540 B CN115602540 B CN 115602540B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 46
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 7
- 229910021529 ammonia Inorganic materials 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 98
- 238000010586 diagram Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910019080 Mg-H Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a manufacturing method of an enhanced GaN power device, and belongs to the technical field of transistors. According to the invention, a complex and expensive high-selectivity p-GaN etching technology is not needed, most of the p-GaN layer is etched by using a conventional GaN etching technology, less p-GaN layer is reserved, damage to the AlGaN surface is avoided, meanwhile, the reserved p-GaN layer is contacted with the AlGaN layer, a depletion region is formed, electrons in two-dimensional electron gas are difficult to reach the AlGaN surface beyond the depletion region, and therefore the dynamic characteristics of the device are improved.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a manufacturing method of an enhanced GaN power device.
Background
The GaN-based material has the performance advantages of large forbidden bandwidth, high breakdown field intensity, high polarization coefficient, high electron mobility and charge saturation mobility, is a preferred material for preparing a new generation of high-performance power electronic devices, and has important application prospect. The high electron mobility transistor prepared by the two-dimensional electron gas generated by the polarization effect at the AlGaN/GaN heterojunction interface is a planar structure GaN-based power device mainly applied at present, and has the advantages of high voltage resistance, high power density, high working speed and the like. However, because of the presence of two-dimensional electron gas at the heterojunction interface, a relatively complex gate drive circuit is required in practical applications, and thus, enhancement mode GaN-based power devices are an important technical goal in GaN-based power device applications.
At present, the p-type GaN cap layer (p-GaN) technology has potential advantages in the aspects of interface quality, device switching characteristics and the like, and becomes a main technology attack direction of industrialization. However, the p-type GaN cap technology is difficult to implement, with the most critical process being p-GaN etching. It is necessary to exhaust the two-dimensional electron gas under the p-GaN pair gate electrode, and the two-dimensional electron gas in other regions cannot be exhausted. This necessitates a region etch of the epitaxially grown p-GaN, leaving only the p-GaN layer of the gate region, and the p-GaN of the other regions to be etched away. Since the underlying AlGaN layer remains and cannot be damaged after the p-GaN is etched, a high selectivity, low damage etching process is required, and the implementation of this etching process is very difficult. Meanwhile, after p-GaN etching, the surface of AlGaN below is damaged to form a large number of surface states, so that the dynamic characteristics of the device are poor (electrons are captured by the surface states after high voltage or large current impact, and the resistance of the device is increased).
Disclosure of Invention
The invention aims to provide a manufacturing method of an enhanced GaN power device, which does not need to adopt a complex and expensive high-selectivity p-GaN etching technology and prevents the dynamic characteristics of the device from being deteriorated.
In order to achieve the above object, the present invention provides the following technical solutions:
the invention provides a manufacturing method of an enhanced GaN power device, which comprises the following steps:
sequentially epitaxially growing a buffer layer, an AlGaN layer and a p-GaN layer on a substrate;
the p-GaN layer of the grid region is reserved, the p-GaN layer of the region outside the grid is etched, the thickness of the p-GaN layer remained after the etching is 1-10 nm, and a p-GaN etching region is formed;
coating passivation protection layers on the upper surface and the side surface of the p-GaN layer reserved in the grid region to obtain a first epitaxial wafer;
annealing the first epitaxial wafer in an ammonia atmosphere, and passivating the p-GaN etching area to obtain a second epitaxial wafer;
growing a SiN film on the upper surface of the second epitaxial wafer, and then manufacturing a source electrode and a drain electrode;
and etching the SiN film and the passivation protection layer in the gate region until part of p-GaN in the gate region is exposed, and manufacturing a gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
Preferably, the passivation protection layer comprises SiN x Layers or SiO 2 A layer.
Preferably, the passivation protection layer has a thickness > the thickness of the p-GaN layer.
Preferably, the passivation protection layer has a thickness > the thickness of the p-GaN layer and < 2 times the thickness of the p-GaN layer.
Preferably, the annealing temperature is > 600 ℃ and < 900 ℃.
Preferably, the time of the annealing is > 1min and < 20min.
Preferably, the substrate comprises a silicon substrate.
Preferably, the buffer layer includes a GaN buffer layer.
Preferably, the thickness of the p-GaN layer remained after the etching is 2-8 nm.
The invention provides a manufacturing method of an enhanced GaN power device, which comprises the following steps: sequentially epitaxially growing a buffer layer, an AlGaN layer and a p-GaN layer on a substrate; the p-GaN layer of the grid region is reserved, the p-GaN layer of the region outside the grid is etched, the thickness of the p-GaN layer remained after the etching is 1-10 nm, and a p-GaN etching region is formed; coating passivation protection layers on the upper surface and the side surface of the p-GaN layer reserved in the grid region to obtain a first epitaxial wafer; annealing the first epitaxial wafer in an ammonia atmosphere, and passivating the p-GaN etching area to obtain a second epitaxial wafer; growing a SiN film on the upper surface of the second epitaxial wafer, and then manufacturing a source electrode and a drain electrode; and etching the SiN film and the passivation protection layer in the gate region until part of p-GaN in the gate region is exposed, and manufacturing a gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
According to the invention, a complex and expensive high-selectivity p-GaN etching technology is not needed, most of the p-GaN layer is etched by using a conventional GaN etching technology, less p-GaN layer is reserved, damage to the AlGaN surface is avoided, meanwhile, the reserved p-GaN layer is contacted with the AlGaN layer, a depletion region is formed, electrons in two-dimensional electron gas are difficult to reach the AlGaN surface beyond the depletion region, and therefore the dynamic characteristics of the device are improved.
Drawings
FIG. 1 is a schematic diagram of a structure in which a buffer layer, an AlGaN layer and a p-GaN layer are epitaxially grown on a substrate in sequence;
FIG. 2 is a schematic diagram of a structure of a p-GaN layer etched in a region other than a gate electrode;
fig. 3 is a schematic structural diagram of a first epitaxial wafer;
FIG. 4 is a schematic diagram of a structure in which SiN films are grown on the upper surface of the second epitaxial wafer and source electrodes and drain electrodes are fabricated;
FIG. 5 is a schematic diagram of the overall structure of an enhanced GaN power device;
in fig. 1 to 5: 1-buffer layer, 2-AlGaN layer, 3-p-GaN layer, 4-passivation protection layer, 5-SiN film, 6-source electrode, 7-drain electrode, 8-gate electrode.
Detailed Description
The invention provides a manufacturing method of an enhanced GaN power device, which comprises the following steps:
sequentially epitaxially growing a buffer layer, an AlGaN layer and a p-GaN layer on a substrate;
the p-GaN layer of the grid region is reserved, the p-GaN layer of the region outside the grid is etched, the thickness of the p-GaN layer remained after the etching is 1-10 nm, and a p-GaN etching region is formed;
coating passivation protection layers on the upper surface and the side surface of the p-GaN layer reserved in the grid region to obtain a first epitaxial wafer;
annealing the first epitaxial wafer in an ammonia atmosphere, and passivating the p-GaN etching area to obtain a second epitaxial wafer;
growing a SiN film on the upper surface of the second epitaxial wafer, and then manufacturing a source electrode and a drain electrode;
and etching the SiN film and the passivation protection layer in the gate region until part of p-GaN in the gate region is exposed, and manufacturing a gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
As shown in FIG. 1, the buffer layer, the AlGaN layer and the p-GaN layer are sequentially epitaxially grown on the substrate.
In the present invention, the substrate preferably comprises a silicon substrate, and the buffer layer preferably comprises a GaN buffer layer. The buffer layer, the AlGaN layer and the p-GaN layer are preferably epitaxially grown in sequence in the MOCVD apparatus. The thickness and growth conditions of the buffer layer, the AlGaN layer and the p-GaN layer are not particularly required in the present invention, which is common knowledge in the art.
After the p-GaN layer is formed, the obtained epitaxial wafer is preferably cleaned, then the p-GaN layer in the region outside the grid is etched according to the p-GaN layer in the reserved grid region as shown in figure 2, and the thickness of the p-GaN layer remained after the etching is 1-10 nm, so that a p-GaN etching region is formed.
The invention performs partial etching, and aims to avoid etching AlGaN and avoid etching damage. Meanwhile, the reserved part of p-GaN can form a depletion region with AlGaN below, electrons in the two-dimensional electron gas are prevented from being captured by traps on the surface of AlGaN, and the dynamic characteristics of the device are improved. The invention can prevent the remained p-GaN part from being too thick to fully exhaust the two-dimensional electron gas below the remained p-GaN part without current by controlling the thickness of the remained p-GaN layer in the range.
After etching, as shown in fig. 3, the passivation protection layer is coated on the upper surface and the side surface of the p-GaN layer reserved in the gate region, so as to obtain a first epitaxial wafer.
Even if a small portion of p-GaN remains, there is still a problem in that the gas density of the two-dimensional electrons below decreases due to the depletion effect of p-GaN. To mitigate this effect, the remaining p-GaN needs to be passivated, but the p-GaN in the gate region cannot be passivated (which acts to fully deplete the two-dimensional electron gas under the gate). To achieve this, it is necessary to coat the p-GaN layer remaining in the gate region with a passivation layer on top and on the sides.
In the present invention, the passivation protection layer preferably includes SiN x Layers or SiO 2 A layer. In the present invention, the thickness of the passivation protection layer is preferably > the thickness of the p-GaN layer, more preferably > the thickness of the p-GaN layer and < 2 times the thickness of the p-GaN layer.
The coating method of the passivation protection layer is not particularly required, and the coating method well known in the art can be adopted. Specifically, a passivation layer can be deposited on the whole surface, then unnecessary passivation layers are removed, and only the passivation layer which is reserved above the p-GaN and covers the p-GaN side wall in the gate region is left. The method has no special requirement on the mode of removing the unnecessary passivation protection layer, and can particularly use a wet etching mode or a dry etching mode.
After the first epitaxial wafer is obtained, annealing is carried out on the first epitaxial wafer in an ammonia atmosphere, and passivation is carried out on the p-GaN etching area to obtain a second epitaxial wafer.
In the present invention, the temperature of the annealing is preferably > 600 ℃ and < 900 ℃, and the time of the annealing is preferably > 1min and < 20min.
In the annealing process, mg in the etched region p-GaN can be combined with NH 3 The decomposed H bonds combine to form Mg-H bonds, thereby reducing the hole concentration in p-GaN. The p-GaN in the gate region has a passivation layer, so that the p-GaN does not react with H bonds, and the hole concentration of the p-GaN is not affected. Therefore, a small part of p-GaN reserved in the etching region can not obviously influence the two-dimensional electron density below the etching region, and meanwhile, the etching region can also play a role in forming a depletion region between p-GaN/AlGaN, so that the dynamic characteristics of the device are improved.
After the second epitaxial wafer is obtained, a SiN film grows on the upper surface of the second epitaxial wafer, and then a source electrode and a drain electrode are manufactured. As shown in fig. 4.
The invention preferably utilizes PECVD (chemical vapor deposition) to grow a SiN film on the upper surface of the second epitaxial wafer. The growing condition and thickness of the SiN film are not particularly required, and the growing condition and thickness which are well known in the art are adopted. In the invention, the SiN film is used as a protective layer for the subsequent ohmic metal etching process.
The preparation process of the source electrode and the drain electrode is not particularly required, and the preparation process known in the art is adopted.
After preparing a source electrode and a drain electrode, etching a SiN film and a passivation protection layer in a gate region until part of p-GaN in the gate region is exposed, and manufacturing the gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
The invention has no special requirements on the process for etching the SiN film and the passivation protection layer, and the conventional etching process is adopted.
The preparation method of the gate electrode has no special requirement, and the preparation method known in the art can be adopted.
The following describes the method for manufacturing the enhanced GaN power device according to the present invention in detail with reference to examples, but they should not be construed as limiting the scope of the present invention.
Example 1
Placing the Si substrate into MOCVD equipment, and sequentially epitaxially growing a GaN buffer layer (5 μm thick), an AlGaN layer (15 nm thick) and a P-GaN layer (80 nm thick);
after cleaning, the p-GaN layer of the grid region is reserved and Cl is adopted 2 Etching the p-GaN layer in the area outside the grid electrode, wherein the thickness of the p-GaN layer left after the etching is 5nm, so as to form a p-GaN etching area;
coating passivation protection layers, specifically SiN, on the upper surface and the side surface of the p-GaN layer reserved in the grid region, wherein the thickness of the passivation protection layers is 100nm, and obtaining a first epitaxial wafer;
putting the first epitaxial wafer into LPCVD equipment, introducing ammonia gas, annealing in an ammonia gas atmosphere at 750 ℃ for 2min, and passivating the p-GaN etching area to obtain a second epitaxial wafer;
growing a SiN film on the upper surface of the second epitaxial wafer, and then manufacturing a source electrode and a drain electrode;
and etching the SiN film and the passivation protection layer in the gate region until part of p-GaN in the gate region is exposed, and manufacturing a gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (4)
1. The manufacturing method of the enhanced GaN power device is characterized by comprising the following steps of:
sequentially epitaxially growing a buffer layer, an AlGaN layer and a p-GaN layer on a substrate;
the p-GaN layer of the grid electrode region is reserved, the p-GaN layer of the region outside the grid electrode is etched, the thickness of the p-GaN layer remained after the etching is 1-10 nm, and a p-GaN etching region is formed;
coating passivation protection layers on the upper surface and the side surface of the p-GaN layer reserved in the grid region to obtain a first epitaxial wafer; the passivation protection layer comprises SiN x Layers or SiO 2 The thickness of the passivation protection layer is more than the thickness of the p-GaN layer and less than 2 times of the thickness of the p-GaN layer;
annealing the first epitaxial wafer in an ammonia atmosphere, and passivating the p-GaN etching area to obtain a second epitaxial wafer; the annealing temperature is more than 600 ℃ and less than 900 ℃, and the annealing time is more than 1min and less than 20min;
growing a SiN film on the upper surface of the second epitaxial wafer, and then manufacturing a source electrode and a drain electrode;
and etching the SiN film and the passivation protection layer in the gate region until part of p-GaN in the gate region is exposed, and manufacturing a gate electrode on the exposed p-GaN surface to obtain the enhanced GaN power device.
2. The method of manufacturing according to claim 1, wherein the substrate comprises a silicon substrate.
3. The method of manufacturing according to claim 1, wherein the buffer layer comprises a GaN buffer layer.
4. The method according to claim 1, wherein the thickness of the p-GaN layer remaining after the etching is 2 to 8nm.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103022119A (en) * | 2011-09-27 | 2013-04-03 | 富士通株式会社 | Semiconductor device |
| CN108962752A (en) * | 2018-09-04 | 2018-12-07 | 苏州能屋电子科技有限公司 | Enhanced HEMT device of p-type grid and preparation method thereof |
| CN109920850A (en) * | 2017-12-12 | 2019-06-21 | 中国科学院苏州纳米技术与纳米仿生研究所 | Enhancement transistor and preparation method thereof based on III race's oxide passivation |
| CN110690284A (en) * | 2019-11-19 | 2020-01-14 | 南方科技大学 | Gallium nitride-based field effect transistor and preparation method thereof |
| CN111952176A (en) * | 2020-08-17 | 2020-11-17 | 深圳方正微电子有限公司 | Semiconductor structure, enhanced high electron mobility transistor and preparation method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022119A (en) * | 2011-09-27 | 2013-04-03 | 富士通株式会社 | Semiconductor device |
| CN109920850A (en) * | 2017-12-12 | 2019-06-21 | 中国科学院苏州纳米技术与纳米仿生研究所 | Enhancement transistor and preparation method thereof based on III race's oxide passivation |
| CN108962752A (en) * | 2018-09-04 | 2018-12-07 | 苏州能屋电子科技有限公司 | Enhanced HEMT device of p-type grid and preparation method thereof |
| CN110690284A (en) * | 2019-11-19 | 2020-01-14 | 南方科技大学 | Gallium nitride-based field effect transistor and preparation method thereof |
| CN111952176A (en) * | 2020-08-17 | 2020-11-17 | 深圳方正微电子有限公司 | Semiconductor structure, enhanced high electron mobility transistor and preparation method thereof |
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