CN109709151B - Dielectric film electrical property measuring system - Google Patents
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Abstract
The invention discloses a dielectric film electrical property measuring system which comprises a probe station, an electrical testing device and a computer, wherein a preposed trans-impedance amplifier in the electrical testing device comprises two CMOS operational amplifiers, four MOS field effect tubes, four CMOS inverters, six resistors and two capacitors. The leakage current of the dielectric film is usually between tens of fA and tens of pA, the output voltage of the preposed transimpedance amplifier can reach the magnitude of several muV to tens of muV by reasonably selecting the peripheral resistor, the output voltage signal is sequentially amplified by the intermediate voltage amplifier and the rear voltage amplifier, can be accurately measured by the current measuring device, and is finally sent to a computer for processing and displaying. By utilizing the unique processing mode of the invention, the interference signal brought by the operational amplifier is effectively filtered from the signal source.
Description
Technical Field
The invention relates to the technical field of nano material measurement, in particular to a dielectric film electrical property measurement system.
Background
Dielectric films are often required in semiconductor processing. In the research and application of the dielectric thin film, it is often necessary to test and grasp a leakage current characteristic, i.e., a voltage-current characteristic curve, of the dielectric thin film. However, in a usual dielectric thin film voltage-current, the leakage current of most dielectric thin films is extremely weak, typically several tens of fA (10) due to its high insulation property-15A) To tens of pA (10)-12A) In the case of a dielectric thin film having a high impurity content and a poor insulation property, the leakage current is generally only nA (10)-9A) Magnitude.
For such weak current signals, the measurement current cannot be directly measured, and the weak current signals must first be converted and amplified to nV (10)-9V) to μ V (10)-6V) magnitude weak voltage signal, and then further amplifying and measuring the weak voltage signal. In various measurement circuits, an operational amplifier is often the core of an amplification circuit. Practical operational amplifiers have a variety of specifications.
In an ideal operational amplifier, when the input voltage of the operational amplifier is 0, the output voltage should also be 0, but in practice this is not always the case, so the input offset voltage (Vos) means that in order to make the output terminal of the operational amplifier reach 0V, a compensation voltage needs to be applied between the two input terminals. The polarity of Vos is random, with typical values of Vos below 10 mV. The offset voltage has a certain relation with the manufacturing process, wherein the input offset voltage of the bipolar process (namely the standard silicon process) is +/-1-10 mV; the input offset voltage is larger by adopting the field effect transistor as the input stage. The input offset voltage is very critical for small signal processing.
The ideal operational amplifier has infinite input impedance, so no current flows into the input terminal, and in general, the bias currents of the CMOS and the JFET are smaller than those of the bipolar transistor, and the input bias current is not generally considered. However, in the amplification circuit of the extremely weak signal, the value of the input bias current is often much larger than the value of the signal to be measured.
In addition, the operational amplifier also has an input offset current, the current flows to an external resistor, even if the current is in the order of K omega, offset voltage of dozens of mu V can be generated, and the offset voltage can be easily amplified to enable the output voltage to be in the mV level.
In addition, various electrical noises and interferences cannot be avoided. The input offset voltage, the input bias current, various electrical noises and interferences of the practical operational amplifier are often far larger than the leakage current in the dielectric film, the leakage current in the dielectric film is submerged in the abnormal signals, in each stage of amplifying circuit, the current to be measured is amplified, meanwhile, the impurity signals such as various interferences, noises, circuit offsets and the like are also amplified, and the factors make the measurement of the leakage current of the dielectric film difficult. Even if a signal amplification circuit is built by using a commercial operational amplifier with excellent performance, the conventional structure of the amplification circuit cannot be used for accurately measuring the leakage current characteristic of the dielectric film, namely, the voltage-current characteristic curve.
Disclosure of Invention
In order to solve the problems of the prior art, an object of the present invention is to provide a system for measuring electrical properties of a dielectric thin film, which can accurately measure a leakage current characteristic, i.e., a voltage-current characteristic curve of the dielectric thin film.
The specific technical scheme for realizing the purpose of the invention is as follows:
a dielectric film electrical property measuring system comprises a probe station, an electrical testing device and a computer;
the probe station comprises a sample station, an optical microscope, two XYZ three-way probe moving stations and two conductive test probes, wherein the XYZ three-way probe moving stations comprise probe holders and XYZ three-way precise moving mechanisms, the probe holders are used for holding and fixing the probes, and the XYZ three-way probe moving stations are used for adjusting the positions of the probes in X, Y, Z directions; the sample stage is used for placing a dielectric film sample; two conductive test probes for electrical connection to two electrodes on the dielectric film sample; the optical microscope is used for observing the position of the tip of the conductive test probe, and accurately moving and reliably contacting the two electrodes on the dielectric film sample;
the electrical testing apparatus comprises: the device comprises a program control voltage signal source, a transimpedance amplifier, a current measuring device, a computer interface circuit, an A/D converter and a coaxial cable, wherein the program control voltage signal source is controlled by a computer through the computer interface circuit to generate and output a test voltage signal; the current measuring device is used for measuring weak current passing through the dielectric film sample, converting an analog measurement result into a digital measurement result through the A/D converter, and feeding the digital measurement result back to the computer through a computer interface circuit of the electrical testing device;
and the computer is used for controlling the electrical testing device and receiving and recording the measurement data returned by the electrical testing device.
The transimpedance amplifier comprises: the pre-transimpedance amplifier is characterized in that: the CMOS digital-to-analog converter comprises two CMOS operational amplifiers, four MOS field effect transistors, four CMOS phase inverters, six resistors and two capacitors;
the first MOS field effect transistor, the first feedback resistor, the second MOS field effect transistor, the first resistor and the second feedback resistor are sequentially connected in series, the drain electrode of the first MOS field effect transistor is electrically connected to an input signal source, the common connecting end of the first MOS field effect transistor and the first feedback resistor is electrically connected to the inverting input end of the first operational amplifier, the common connecting end of the first feedback resistor and the second MOS field effect transistor is electrically connected to the output end of the first operational amplifier, a first capacitor is electrically connected between the common connecting end of the second MOS field effect transistor and the first resistor and the ground end, the common connecting end of the first resistor and the second feedback resistor is electrically connected to the inverting input end of the second operational amplifier, and the other end of the second feedback resistor is electrically connected to the output end of the second operational amplifier; the source electrode of the third MOS field effect transistor is electrically connected to the input signal source, and the drain electrode of the third MOS field effect transistor is electrically connected to the ground end; the third resistor is electrically connected between the non-inverting input end and the ground end of the first operational amplifier; the fourth MOS field effect transistor, the second resistor and the third feedback resistor are sequentially connected in series, the source electrode of the fourth MOS field effect transistor is electrically connected to the output end of the first operational amplifier, and the other end of the third feedback resistor is electrically connected to the ground end; a second capacitor is electrically connected between the common connection end of the fourth MOS field effect transistor and the second resistor and the ground end; the common connecting end of the second resistor and the third feedback resistor is electrically connected to the non-inverting input end of the second operational amplifier; the grid of the third MOS field effect transistor is electrically connected to the external clock signal input end, the external clock signal input end is also electrically connected with a first CMOS phase inverter, the output end of the first CMOS phase inverter is electrically connected to the grid of the first MOS field effect transistor and the input end of a second CMOS phase inverter, the output end of the second CMOS phase inverter is electrically connected to the input end of a third CMOS phase inverter, the output end of the third CMOS phase inverter is electrically connected to the input end of a fourth CMOS phase inverter and the grid of the second MOS field effect transistor, and the output end of the fourth CMOS phase inverter is electrically connected to the grid of the fourth MOS field effect transistor; the output end of the second operational amplifier is electrically connected to the input end of the intermediate voltage amplifier;
the frequency of the external clock signal is in the order of MHz, preferably the frequency of the external clock signal is 1-100MHz, and more preferably the frequency of the external clock signal is 10-100 MHz; according to the circuit simulation result, when the frequency of an external clock signal is too low, various offset signals and noise signals are difficult to effectively eliminate; when the frequency of an external clock signal is too high, extra digital noise is brought to a circuit behind, the switching characteristics of each MOS tube are deteriorated under ultrahigh frequency, the transition effect is obvious, and the signal output begins to obviously deviate from an ideal state; the use of ultra-high frequency MOS transistors can overcome the above problems to some extent, but significantly increase the cost. Considering comprehensively, the frequency of the external clock signal is more preferably 10-100 MHz.
The four MOS field effect transistors work in a switching state, and the switching state of the four MOS field effect transistors is controlled by an external clock signal; under the condition of not considering transmission time delay of each phase inverter, the first MOS field effect transistor and the second MOS field effect transistor are simultaneously turned on or off, the third MOS field effect transistor and the fourth MOS field effect transistor are simultaneously turned off or on, and the switching states of the first MOS field effect transistor and the second MOS field effect transistor are always opposite to the switching states of the third MOS field effect transistor and the fourth MOS field effect transistor, namely when the first MOS field effect transistor and the second MOS field effect transistor are in a conducting low-resistance state, the third MOS field effect transistor and the fourth MOS field effect transistor are both in a cut-off state, and vice versa.
Ideally, the second CMOS inverter, the third CMOS inverter, and the fourth CMOS inverter are not necessary and may be omitted, however, in the present invention, in order to better achieve fidelity of signal amplification, the second CMOS inverter, the third CMOS inverter, and the fourth CMOS inverter are intentionally introduced. When the actual operational amplifier works, after the electric signal passes through the internal amplifying circuit of the operational amplifier, a small phase difference always exists between the output end and the input end of the operational amplifier. The invention utilizes the transition characteristic of the actual CMOS inverter during working, namely, the output end and the input end of the actual CMOS inverter have a tiny phase difference, and the invention realizes the matching of the tiny phase difference with the input end and the output end of the transport amplifier by additionally inserting the redundant CMOS inverter, thereby avoiding the problem that the switching action of the second MOS field effect transistor and the fourth field effect transistor is not completely matched with the response speed of the first operational amplifier. Optionally, 2N series-connected CMOS inverters may be further added between the second CMOS inverter and the third CMOS inverter, where N is a positive integer, and a value of N is determined by an actual response speed of the first operational amplifier.
Optionally, the computer Interface circuit of the electrical testing apparatus is a GPIB (General-Purpose Interface Bus) Interface circuit, a BNC (BayonetNut Connector, BNC) Interface circuit, or a USB (Universal Serial Bus, USB) Interface circuit.
In the prior art, no evidence has been found to suggest that there is a design identical or similar to the present invention, i.e., employing redundant CMOS inverters to match operational amplifier response speed. Since the prior art does not adopt the pre-transimpedance amplifier similar to the present invention, there is no motivation for those skilled in the art to adopt redundant CMOS inverters in such a pre-transimpedance amplifier to match the response speed of the operational amplifier.
In addition, the additionally added CMOS phase inverter further enhances the driving capability of external clock pulses, and ensures that the second MOS field effect transistor and the fourth MOS field effect transistor are reliably and rapidly turned on and off.
By adopting the pre-amplification circuit, the amplification circuit is cut into two paths according to the time slice wheel by the high-frequency switch circuit, and then the two paths are combined into one by the subtraction circuit, so that the interference signal is effectively filtered from the signal source by utilizing the mode, the useful signal to be detected is extracted and amplified as much as possible, the signal-to-noise ratio (SNR) is improved, the noise is effectively inhibited, and the leakage current characteristic of the dielectric film, namely the voltage-current characteristic curve is accurately measured and obtained.
Description of the drawings:
FIG. 1: a schematic diagram of a dielectric film electrical property measurement system of the present invention;
FIG. 2: the pre-transimpedance amplifier in the electrical test apparatus 2 of the present invention.
Detailed Description
For the convenience of understanding, the technical scheme of the invention is specifically described by combining the examples.
As shown in fig. 1, a dielectric thin film electrical property measurement system includes a probe station 1, an electrical test apparatus 2, and a computer 3;
the probe station comprises a sample station, an optical microscope, two XYZ three-way probe moving stations and two conductive test probes, wherein the XYZ three-way probe moving stations comprise probe holders and XYZ three-way precise moving mechanisms, the probe holders are used for holding and fixing the probes, and the XYZ three-way probe moving stations are used for adjusting the positions of the probes in X, Y, Z directions; the sample stage is used for placing a dielectric film sample; the two conductive test probes are used for being electrically connected to the two electrodes of the film sample; the dielectric thin film, for example: al (Al)2O3、ZrO2、TiO2A film;
the electrical testing apparatus comprises: the device comprises a program control voltage signal source, a transimpedance amplifier, a current measuring device, a computer interface circuit, an A/D converter and a coaxial cable, wherein the program control voltage signal source is controlled by a computer through the computer interface circuit to generate and output a test voltage signal; the current measuring device is used for measuring weak current passing through the film sample, converting an analog measurement result into a digital measurement result through the A/D converter, and feeding the digital measurement result back to the computer through the computer interface circuit;
the transimpedance amplifier comprises: the device comprises a front-end trans-impedance amplifier, a middle voltage amplifier and a rear-end voltage amplifier.
As shown in fig. 2, the pre-transimpedance amplifier includes two CMOS operational amplifiers, four MOS field effect transistors, four CMOS inverters, six resistors, and two capacitors;
wherein, the first MOS field effect transistor T1A first feedback resistor Rf1A second MOS FET transistor T2A first resistor R1A second feedback resistor Rf2Sequentially connected in series, the first MOS field effect transistor T1Is electrically connected to the drainInput signal source, first MOS FET1And a first feedback resistor Rf1Is electrically connected to the inverting input terminal of the first operational amplifier A1, a first feedback resistor Rf1And a second MOS field effect transistor T2Is electrically connected to the output terminal of the first operational amplifier A1, and a second MOS field effect transistor T2And a first resistor R1A first capacitor C is electrically connected between the common connection end and the ground end1First resistance R1And a second feedback resistor Rf2Is electrically connected to the inverting input terminal of the second operational amplifier a2, a second feedback resistor Rf2The other end of the first operational amplifier is electrically connected to the output end of the second operational amplifier A2; third MOS FET3The source electrode is electrically connected to the input signal source, and the drain electrode is electrically connected to the ground end; third resistor R3The non-inverting input terminal of the first operational amplifier A1 is electrically connected to the ground terminal; fourth MOS FET transistor T4A second resistor R2A third feedback resistor Rf3Sequentially connected in series, a fourth MOS field effect transistor T4A source electrode of the first operational amplifier A1, a third feedback resistor Rf3The other end of the first switch is electrically connected to the ground end; fourth MOS FET transistor T4And a second resistor R2A second capacitor C is electrically connected between the common connection end and the ground end2(ii) a A second resistor R2And a third feedback resistor R3Is electrically connected to the non-inverting input of the second operational amplifier a 2; third MOS FET3The grid electrode of the first CMOS phase inverter PI is electrically connected to the external clock signal input end which is also electrically connected with the first CMOS phase inverter PI1First CMOS inverter PI1The output end of the first MOS field effect transistor is electrically connected to the first MOS field effect transistor T1And the second CMOS inverter PI2Second CMOS inverter PI2The output end of the second CMOS inverter PI is electrically connected to the second CMOS inverter3Input terminal of (1), third CMOS inverter PI3The output end of the second CMOS inverter PI is electrically connected to the second CMOS inverter PI4And a second MOS field effect transistor T2The fourth CMOS inverter PI4Is electrically connected with the output endIs connected to a fourth MOS field effect transistor T4A gate electrode of (1); the output end of the second operational amplifier A2 is electrically connected to the input end of the intermediate voltage amplifier;
the frequency of the external clock signal is in the order of MHz, preferably the frequency of the external clock signal is in the range of 1-100MHz, more preferably the frequency of the external clock signal is in the range of 10-100 MHz.
Ideally, the second CMOS inverter PI2And a third CMOS inverter PI3And a fourth CMOS inverter PI4It is not essential and can be omitted, however, in the present invention, in order to better achieve the fidelity of the signal amplification, a second CMOS inverter PI is purposely introduced2And a third CMOS inverter PI3And a fourth CMOS inverter PI4。
Optionally, 2N series-connected CMOS inverters may be further added between the second CMOS inverter and the third CMOS inverter, where N is a positive integer, and a value of N is determined by an actual response delay of the first operational amplifier a 1.
The four MOS field effect transistors work in a switching state, and the switching state of the four MOS field effect transistors is controlled by an external clock signal; wherein, the first MOS field effect transistor T does not consider the transmission time delay of each phase inverter1And a second MOS FET2Simultaneously turning on or off the third MOS FET3And a fourth MOS FET4Are simultaneously turned off or on, and the first MOS field effect transistor T1And a second MOS FET2And the third MOS field effect transistor T3And a fourth MOS FET4Is always in the opposite state, i.e. the first MOSFET T1And a second MOS FET2When in the on low-resistance state, the third MOS field effect transistor T3And a fourth MOS FET4Then both are in the off state and vice versa.
As shown in FIG. 2, the virtual equivalent model of the first operational amplifier A1 is shown in the large dashed box, and the ideal operational amplifier A1' is shown in the small dashed box, where the virtual equivalent offset voltage U of the virtual equivalent operational amplifier of the first operational amplifier is shownI0Operational amplifier equivalent inputBias current Ib-、Ib+In addition, I in the figurefilmFor the leakage current to be measured in the dielectric film, Inoise(t) is the equivalent current of the electrical noise and interference signals introduced by the external environment of the circuit, and the current is a value changing along with time.
When the first MOS FET T1And a second MOS FET2A third MOS FET transistor T simultaneously in conduction low resistance state3And a fourth MOS FET4When both are in the cut-off state, the first capacitor C1The voltages on are:
UC1＝-IfilmRf1+UI0+Ib+R3+Ib-Rf1 (1)
when the first MOS FET T1And a second MOS FET2Third MOS FET transistor T in cut-off state3And a fourth MOS FET4When the two capacitors are in a conducting low-resistance state, the second capacitor C2The voltages on are:
UC2＝-UI0+Ib+R3+Ib-Rf1 (2)
reasonably selecting the first capacitor C1And a second capacitor C2Value of (1), first resistance R1A second feedback resistor Rf2A second resistor R2And a third feedback resistor R3A value of (A) such that (R)1+Rf2)C1、(R2+Rf3)C2These two products are much larger than the period of the external clock signal, preferably (R)1+Rf2)C1、(R2+Rf3)C2Both products are more than 100 times the period of the external clock signal. Under such conditions, the first capacitor C is in the period of an external clock signal1And a second capacitor C2The voltage value of (d) can be regarded as constant, and therefore, the output voltage value of the second operational amplifier is:
is usually taken
Substituting the formulas (1) and (2) into the formula (3), and simplifying to obtain the final product
It can be seen that by using the pre-transimpedance amplifier of the present invention, the various input offset voltages U of the operational amplifier itselfI0Input bias current Ib-、Ib+Are eliminated. Under a given circuit, the output voltage signal value of the pre-transimpedance amplifier is proportional to the magnitude of the leakage current of the dielectric film. The magnitude of leakage current of dielectric thin films is usually between several tens of fA (10)-15A) To tens of pA (10)-12A) By reasonably selecting the first resistor R1A second feedback resistor Rf2A second resistor R2And a third feedback resistor R3The output voltage of the pre-transresistance amplifier can reach several mu V to dozens of mu V magnitude, the output voltage signal is successively amplified by the middle voltage amplifier and the rear voltage amplifier, can be accurately measured by the current measuring device, and finally is sent back to the computer for processing and displaying.
The computer controls the voltage signal source through software to generate a series of voltage signals to be applied to the film sample, the electric testing device measures the leakage current value of the film sample under the series of voltage signals and transmits the leakage current value back to the computer, the computer stores the measured values, and the leakage current characteristic of the dielectric film, namely a voltage-current characteristic curve, is displayed on a screen.
Matters not specifically described in the present specification are within the routine skill of those skilled in the art and need not be further disclosed.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and it should be understood that any equivalent substitution, obvious modification made by those skilled in the art in the light of the present specification are within the spirit scope of the present specification, and the present invention should be protected.
Claims (9)
1. A dielectric thin film electrical property measurement system, comprising: the measuring system comprises a probe station, an electrical testing device and a computer, wherein the probe station is used for placing and fixing a dielectric film sample, the electrical testing device is used for measuring the leakage current characteristic of the dielectric film, namely a voltage-current characteristic curve, and the computer is used for controlling the electrical testing device and receiving and recording the measurement data returned by the electrical testing device;
the electrical testing device comprises: the computer program controls a voltage signal source, a trans-impedance amplifier, a current measuring device, a computer interface circuit, an A/D converter and a coaxial cable; the transimpedance amplifier comprises: the front-end trans-impedance amplifier, the middle voltage amplifier and the rear-end voltage amplifier;
the pre-transimpedance amplifier is characterized in that: the CMOS digital-to-analog converter comprises two CMOS operational amplifiers, four MOS field effect transistors, four CMOS phase inverters, six resistors and two capacitors; wherein,
the first MOS field effect transistor, the first feedback resistor, the second MOS field effect transistor, the first resistor and the second feedback resistor are sequentially connected in series, the drain electrode of the first MOS field effect transistor is electrically connected to an input signal source, the common connecting end of the first MOS field effect transistor and the first feedback resistor is electrically connected to the inverting input end of the first operational amplifier, the common connecting end of the first feedback resistor and the second MOS field effect transistor is electrically connected to the output end of the first operational amplifier, a first capacitor is electrically connected between the common connecting end of the second MOS field effect transistor and the first resistor and the ground end, the common connecting end of the first resistor and the second feedback resistor is electrically connected to the inverting input end of the second operational amplifier, and the other end of the second feedback resistor is electrically connected to the output end of the second operational amplifier; the source electrode of the third MOS field effect transistor is electrically connected to the input signal source, and the drain electrode of the third MOS field effect transistor is electrically connected to the ground end; the third resistor is electrically connected between the non-inverting input end and the ground end of the first operational amplifier; the fourth MOS field effect transistor, the second resistor and the third feedback resistor are sequentially connected in series, the source electrode of the fourth MOS field effect transistor is electrically connected to the output end of the first operational amplifier, and the other end of the third feedback resistor is electrically connected to the ground end; a second capacitor is electrically connected between the common connection end of the fourth MOS field effect transistor and the second resistor and the ground end; the common connecting end of the second resistor and the third feedback resistor is electrically connected to the non-inverting input end of the second operational amplifier; the grid of the third MOS field effect transistor is electrically connected to the external clock signal input end, the external clock signal input end is also electrically connected with a first CMOS phase inverter, the output end of the first CMOS phase inverter is electrically connected to the grid of the first MOS field effect transistor and the input end of a second CMOS phase inverter, the output end of the second CMOS phase inverter is electrically connected to the input end of a third CMOS phase inverter, the output end of the third CMOS phase inverter is electrically connected to the input end of a fourth CMOS phase inverter and the grid of the second MOS field effect transistor, and the output end of the fourth CMOS phase inverter is electrically connected to the grid of the fourth MOS field effect transistor; the output end of the second operational amplifier is electrically connected to the input end of the intermediate voltage amplifier;
the first MOS field effect transistor, the second MOS field effect transistor, the third MOS field effect transistor and the fourth MOS field effect transistor work in a switching state, and the switching states are controlled by external clock signals; the high-frequency switch circuit with MHz magnitude cuts the amplifying circuit into two paths according to the time slice wheel, and then the two paths are combined into one by the subtraction circuit, so that interference signals are effectively filtered, useful signals to be detected are extracted and amplified, the signal-to-noise ratio is improved, and the leakage current characteristic of the dielectric film, namely a voltage-current characteristic curve, is accurately measured.
2. A dielectric thin film electrical property measurement system as claimed in claim 1, wherein: the probe station comprises a sample station, an optical microscope, two XYZ three-way probe moving stations and two conductive test probes, wherein the XYZ three-way probe moving stations comprise probe holders and XYZ three-way precise moving mechanisms, the probe holders are used for holding and fixing the probes, and the XYZ three-way probe moving stations are used for adjusting the positions of the probes in X, Y, Z directions; the sample stage is used for placing a dielectric film sample; two conductive test probes are used to electrically connect to two electrodes on the dielectric film sample.
3. A dielectric thin film electrical property measurement system as claimed in claim 2, wherein: an optical microscope is used to observe the position of the conductive test probe tip and accurately move and reliably contact the two electrodes on the dielectric film sample.
4. A dielectric thin film electrical property measurement system as claimed in claim 1, wherein: the frequency of the external clock signal is 1-100 MHz.
5. The dielectric thin film electrical property measurement system of any one of claims 1-4, wherein: and 2N CMOS inverters connected in series are additionally arranged between the second CMOS inverter and the third CMOS inverter, N is a positive integer, and the value of N enables the overall response speed of all the CMOS inverters to be matched with the response speed of the first operational amplifier.
6. The dielectric thin film electrical property measurement system of any one of claims 1-4, wherein: the computer interface circuit of the electrical testing device is a GPIB interface circuit, a BNC interface circuit or a USB interface circuit.
7. The dielectric thin film electrical property measurement system of any one of claims 1-4, wherein: the program control voltage signal source is controlled by a computer through a computer interface circuit to generate and output a test voltage signal, the transimpedance amplifier is used for amplifying a weak current passing through the dielectric film sample, the front end of the transimpedance amplifier is electrically connected to an electrode on the dielectric film sample through a coaxial cable and a probe in sequence, and the rear end of the transimpedance amplifier is electrically connected to the current measuring device; the current measuring device is used for measuring weak current passing through the dielectric film sample, converting an analog measurement result into a digital measurement result through the A/D converter, and feeding the digital measurement result back to the computer through a computer interface circuit of the electrical testing device.
8. The dielectric thin film electrical property measurement system of any one of claims 1-4, wherein: under the condition of not considering the transmission time delay of each phase inverter, the first MOS field effect transistor and the second MOS field effect transistor are simultaneously turned on or off, the third MOS field effect transistor and the fourth MOS field effect transistor are simultaneously turned off or on, and the switching states of the first MOS field effect transistor and the second MOS field effect transistor are always opposite to the switching states of the third MOS field effect transistor and the fourth MOS field effect transistor, namely when the first MOS field effect transistor and the second MOS field effect transistor are in a conducting low-resistance state, the third MOS field effect transistor and the fourth MOS field effect transistor are both in a cut-off state, and vice versa.
9. The dielectric thin film electrical property measurement system of any one of claims 1-4, wherein: the computer controls the voltage signal source through software to generate a series of voltage signals to be applied to the film sample, the electric testing device measures the leakage current value of the film sample under the series of voltage signals and transmits the leakage current value back to the computer, the computer stores the measured values, and the leakage current characteristic of the dielectric film, namely a voltage-current characteristic curve, is displayed on a screen.
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| CN201910094588.4A CN109709151B (en) | 2019-01-30 | 2019-01-30 | Dielectric film electrical property measuring system |
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| CN201910094588.4A CN109709151B (en) | 2019-01-30 | 2019-01-30 | Dielectric film electrical property measuring system |
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