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CN109478543B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109478543B
CN109478543B CN201680087903.5A CN201680087903A CN109478543B CN 109478543 B CN109478543 B CN 109478543B CN 201680087903 A CN201680087903 A CN 201680087903A CN 109478543 B CN109478543 B CN 109478543B
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semiconductor device
solder
intermediate plate
semiconductor chip
semiconductor
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CN109478543A (zh
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中田洋辅
佐佐木太志
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

半导体芯片(3)经由第1焊料(2)而接合于电极基板(1)的上表面。引线框(5)经由第2焊料(4)而接合于半导体芯片(3)的上表面。在电极基板(1)和半导体芯片(3)之间，中间板(6)设置于第1焊料(2)中。中间板(6)的屈服强度在半导体装置的整个使用温度范围比电极基板(1)及第1焊料(2)的屈服强度大。

Description

半导体装置
技术领域
本发明涉及IGBT、MOSFET、二极管等电力用半导体装置。
背景技术
公开了经由焊料将半导体芯片接合于铝电极基板，经由焊料将铜电极接合于半导体芯片上表面的半导体装置(例如，参照专利文献1)。
专利文献1：国际公开第2015/029186号
发明内容
但是，在冷热循环及功率循环的温度范围、即半导体装置的使用温度范围，存在铝电极基板与焊料的屈服强度关系逆转的点。因此，铝电极基板和焊料各自产生变形，不会回到原来的位置。存在如果变形量进一步积蓄，则最终，半导体芯片产生变形而使可靠性降低的问题。特别地，就对应于高温的SiC芯片等而言，使用温度范围宽且温度应力严重。
例如，通过用传递模塑树脂覆盖半导体芯片的上表面，能够抑制半导体芯片的变形。但是，就焊料接合于半导体芯片上表面的半导体装置而言，存在由于半导体芯片的上表面被容易变形的焊料覆盖，因此不能够由模塑树脂进行固定而难以抑制半导体芯片的变形的问题。
本发明就是为了解决上述课题而提出的，其目的在于得到能够提高相对于冷热循环及功率循环的可靠性的半导体装置。
本发明涉及的半导体装置的特征在于具备：电极基板；半导体芯片，其经由第1焊料而接合于所述电极基板的上表面；引线框，其经由第2焊料而接合于所述半导体芯片的上表面；以及中间板，其在所述电极基板和所述半导体芯片之间，设置于所述第1焊料中，所述中间板的屈服强度在半导体装置的整个使用温度范围比所述电极基板及所述第1焊料的屈服强度大。
发明的效果
在本发明中，在电极基板和半导体芯片之间，在第1焊料中设置有中间板。而且，中间板的屈服强度在半导体装置的整个使用温度范围比电极基板及第1焊料的屈服强度大。由此，能够提高相对于冷热循环及功率循环的可靠性。
附图说明
图1是表示实施方式1涉及的半导体装置的剖面图。
图2是表示电极基板、第1及第2焊料和中间板的屈服强度的温度依赖性的图。
图3是表示实施方式2涉及的中间板的俯视图。
图4是沿图3的I-II的剖面图。
图5是表示实施方式3涉及的半导体装置的剖面图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同标号，有时省略重复说明。
实施方式1.
图1是表示实施方式1涉及的半导体装置的剖面图。本实施方式涉及的半导体装置例如用于对汽车动力用电动机进行驱动的电源。半导体芯片3经由第1焊料2而接合于电极基板1的上表面。引线框5经由第2焊料4而接合于半导体芯片3的上表面。
半导体芯片3是例如由硅形成的IGBT或MOSFET等开关半导体元件、或二极管等续流用半导体元件。与耐压等级对应地对半导体芯片3的厚度进行优化。例如，如果考虑到大多用于混合动力汽车或电动车的锂离子电池的电压，则希望半导体芯片3的耐压等级为600V至800V。特别是为了改善电气特性中的DC损耗，希望半导体芯片3的厚度小于或等于100μm。
电极基板1例如在绝缘基板之上通过轧制或铸造而形成为板状。此外，在绝缘基板的下表面设置导体基板，在该导体基板设置有多个冷却用凸起。通过使冷却水直接接触导体基板和多个冷却用凸起，从而能够有效地对从半导体芯片3产生的热进行冷却。电极基板1、导体基板及多个冷却用凸起能够通过铝铸造对绝缘基板进行镶铸而一体形成。电极基板1等的主要材料为铝。由此，能够在维持电传导性以及热传导性的同时，确保相对于冷却水的耐腐蚀性，抑制成本及重量。另外，为了改善热传导，希望采用大于或等于99％的高纯度铝。
第1及第2焊料2、4是例如Sn-Cu系、Sn-Ag系、或Sn-Ag-Cu系无铅焊料。由此，能够在还原环境中容易地将半导体芯片3电接合以及热接合于引线框5或电极基板1。而且，第1及第2焊料2、4在半导体芯片3的使用温度范围200℃以下，也能够保持固相状态。
引线框5的主要材料是例如铜。例如，引线框5是在将Cu材料进行轧制而形成了Cu板材后，通过冲裁加工而被加工为任意形状的。引线框5与第2焊料4电连接。
此外，在半导体芯片3的上表面和下表面分别通过电解电镀法、溅射、或蒸镀等气相沉积法形成有由包含Ni的材料构成的焊料接合用金属膜。上表面和下表面的焊料接合用金属膜分别与第1及第2焊料2、4电连接以及热连接。
在电极基板1和半导体芯片3之间，中间板6设置于第1焊料2中。中间板6的主要材料为铜。例如，中间板6是在将Cu材料进行轧制而形成了Cu板材后，通过冲裁加工而被加工为任意形状的。
电极基板1的上表面、第1焊料2、半导体芯片3、第2焊料4、中间板6、引线框5的一部分被封装材料7覆盖。作为封装材料7，能够使用传递模塑树脂或灌封树脂。在封装材料7与半导体芯片3直接接触的部分，能够抑制半导体芯片3的变形。
接着，对本实施方式涉及的半导体装置的制造方法进行说明。首先，在电极基板1之上按顺序层叠中间板6、第1焊料2、半导体芯片3。接着，在还原环境中对第1焊料2进行加热而使其熔融，经由第1焊料2及中间板6将半导体芯片3的下表面电接合以及热接合于电极基板1的上表面。为了最大限度地得到热接合，希望使半导体芯片3的下表面的大致整个面得到接合。另外，为了防止空气混入第1焊料2而产生空隙，希望通过在减压下使第1焊料2熔融，然后恢复压力，从而将空气从第1焊料2排出。层叠中间板6和第1焊料2的顺序也可以相反，在半导体芯片3的正下方配置中间板6的情况下，通过配置为使得中间板6的冲裁加工的毛边朝向第1焊料2侧，从而能够防止损伤半导体芯片3而提高成品率。
然后，使用第2焊料4将引线框5电连接于半导体芯片3的上表面。这里，半导体芯片3的上表面不需要热接合于引线框5。另外，需要确保半导体芯片3的端部和引线框5的沿面距离。然后，需要使用导体导线等连接半导体芯片3的上表面的信号端子和外部电极。因此，引线框5与半导体芯片3的上表面局部接合。接着，由封装材料7将电极基板1的上表面、第1焊料2、半导体芯片3、第2焊料4、中间板6、引线框5的至少一部分覆盖。通过上述工序制造本实施方式涉及的半导体装置。
图2是表示电极基板、第1及第2焊料和中间板的屈服强度的温度依赖性的图。这里，屈服强度示出的是0.2％屈服强度，是在未表现出屈服现象的大量金属材料中，在卸除载荷时使金属材料产生0.2％塑性变形的应力。电极基板1的屈服强度和第1及第2焊料2、4的屈服强度的大小关系在半导体装置的使用温度范围存在逆转的点。因此，对于第1焊料2和电极基板1而言，在各自不同的温度区域产生变形。例如，在第1焊料2产生变形时电极基板1难以变形，在电极基板1产生变形时第1焊料2难以变形。因此，各自的材料不会返回至原来的位置而是变形量积蓄起来，通过反复进行冷热循环，从而变形量逐渐变大。
因此，在本实施方式中，在电极基板1和半导体芯片3之间，在第1焊料2中设置有中间板6。而且，中间板6的屈服强度在半导体装置的整个使用温度范围比电极基板1及第1焊料2的屈服强度大。因此，即使电极基板1及第1焊料2在冷热循环中产生变形，中间板6也不产生变形，因此能够抑制半导体芯片3的变形。特别地，对于第2焊料4的正下方而言，由于半导体芯片3没有与封装材料7直接接触，因此封装材料7的固定力没有波及到，在第2焊料4由于冷热循环及功率循环的应力而产生了变形时，失去约束力，变得容易产生变形。相对于此，由于在半导体芯片3之下设置有难以变形的中间板6，因此能够抑制半导体芯片3的变形。其结果，能够提高相对于冷热循环及功率循环的可靠性。此外，在本实施方式中第1及第2焊料2、4为相同的材料，但即使是不同的材料，只要具有上述屈服强度关系也会得到同样的效果。
另外，在使用碳化硅等对应于高温的半导体芯片的情况下，使用温度范围的高温侧扩大到200℃。另外，在汽车用途中，低温侧扩大到-55℃。因此，电极基板1和第1焊料2的变形量容易变大，需要通过中间板6抑制半导体芯片3的变形。
另外，由于中间板6和第1焊料2的线膨胀系数不同而产生由冷热循环造成的应力。该应力在半导体芯片3的端部最大。如果通过中间板6将第1焊料2分割开，则半导体芯片3的端部的第1焊料2的厚度变薄，应力变大。特别地，在中间板6在第1焊料2中倾斜的情况下，第1焊料2的端部的厚度局部变得更薄，应力显著地增加。因此，使中间板6比半导体芯片3及第1焊料2小，在俯视观察时配置于半导体芯片3及第1焊料2的内侧。由此，能够使中间板6完全埋入于第1焊料2，能够防止在第1焊料2的端部使第1焊料2被中间板6分割开。其结果，能够进一步提高相对于冷热循环的可靠性。
另外，使中间板6的端部从半导体芯片3的端部向内侧后退，使中间板6不从第1焊料2露出。具体而言，使半导体芯片3的端部和中间板6的端部之间的间隔d1比第1焊料2的厚度t1大。由此，即使在中间板6在第1焊料2中倾斜的情况下，在半导体芯片3的端部，第1焊料2的厚度也不会变薄，能够发挥稳定的可靠性。
另外，第2焊料4在俯视观察时配置于中间板6的内侧。如果由于功率循环的应力而使第2焊料4产生变形，则半导体芯片3会产生变形。因此，通过利用中间板6进行支撑，从而能够抑制半导体芯片3的变形。
实施方式2.
图3是表示实施方式2涉及的中间板的俯视图。图4是沿图3的I-II的剖面图。本实施方式除了中间板6的结构之外与实施方式1相同。
在中间板6，例如通过冲裁加工而设置了多个贯穿孔8。由此，第1焊料2能够从贯穿孔8通过而在上下两面润湿扩展，因此不需要在中间板6的上表面侧和下表面侧这两者设置第1焊料2。因此，能够削减第1焊料2的部件件数和组装作业，能够降低制造成本。
另外，镀膜9将中间板6的表面覆盖。镀膜9的主要材料为镍，镀膜9与中间板6相比相对于第1焊料2的湿润性高。由此，能够提高焊料湿润性，因此能够降低空隙不良率，能够降低制造损耗成本。
另外，由于是在对贯穿孔8进行冲裁加工后形成镀膜9，因此在多个贯穿孔8的侧壁也形成有镀膜9。由此，第1焊料2在贯穿孔8的侧壁也润湿扩展而填充于贯穿孔8的内侧，因此能够抑制空隙的产生，提高可靠性。
另外，优选贯穿孔8的大小小于或等于500μmΦ。如果向多个贯穿孔8混入空气，则在第1焊料2中形成空隙，但在空隙直径小于或等于500μm时热不良影响小，不易产生热阻的恶化及短路耐受量的降低。另外，在超过500μmΦ的空气混入至多个贯穿孔8的情况下，通过第1焊料2的表面张力，空隙被多个贯穿孔8细化，因此不易产生超过500μmΦ的空隙，能够提高制造成品率。
另外，在第1焊料2和镀膜9之间形成金属间化合物。由于在该金属间化合物之上通过冷热循环产生柯肯达尔空隙，因此有时导致焊料裂缝。因此，希望与实施方式1相同地不使中间板6从第1焊料2露出。
实施方式3.
图5是表示实施方式3涉及的半导体装置的剖面图。在电极基板1和半导体芯片3的端部之间，通过铝导线等设置有多个凸块10。由于通过凸块能够确保半导体芯片3和电极基板1的距离，因此能够防止半导体芯片3倾斜地安装而使第1焊料2局部变薄。
另外，中间板6在俯视观察时配置于多个凸块10的内侧。由此，焊料接合工序中的中间板6的动作被凸块10限制，从而能够防止中间板6流动到半导体芯片3外侧而从第1焊料2露出。
另外，中间板6的厚度t2比凸块的高度h1薄。由此，在焊料接合工序中，即使中间板6在熔融状态的第1焊料2中倾斜，也能够通过凸块10而维持半导体芯片3的高度。
此外，在实施方式1～3中，在半导体芯片3的厚度小于或等于100μm的情况下，能够降低半导体芯片3的损耗，但随着周边部件的变形，半导体芯片3容易产生变形。因此，设置中间板6以防止可靠性的降低的必要性高。
另外，中间板6的主要材料也可以是钼。在该情况下，例如在将钼材料进行轧制而形成了钼板材后，通过利用冲裁加工而加工为任意形状来形成中间板6。通过使用钼而能够使中间板6的线膨胀系数接近作为半导体芯片3的主要材料的硅，因此能够降低由两者的热膨胀系数差产生的应力。因此，能够进一步减轻由于热循环或功率循环而施加于半导体芯片3的应力，因此能够在维持电传导性以及热传导性的同时进一步提高可靠性。
另外，通过将化合物半导体用于半导体芯片3，从而直至高温为止都能够使用。特别地，通过作为主要材料而使用具有碳的SiC等化合物半导体，从而直至更高温为止都能够使用。另外，由与硅相比带隙大的宽带隙半导体形成的半导体芯片3的耐压性、容许电流密度高，因此能够小型化。通过使用该被小型化后的半导体芯片3，从而组装有该半导体芯片3的半导体装置也能够小型化。另外，由于半导体芯片3的耐热性高，因此能够将散热器的散热片小型化，能够将水冷部空冷化，因此能够进一步将半导体装置小型化。另外，由于半导体芯片3的功率损耗低且高效，因此能够使半导体装置高效化。宽带隙半导体除了SiC之外，例如是氮化镓类材料或金刚石。
标号的说明
1电极基板，2第1焊料，3半导体芯片，4第2焊料，5引线框，6中间板，9镀膜，8贯穿孔，10凸块。

Claims (21)

1.一种半导体装置，其特征在于，具备：
电极基板；
半导体芯片，其经由第1焊料而接合于所述电极基板的上表面；
引线框，其经由第2焊料而接合于所述半导体芯片的上表面；
中间板，其在所述电极基板和所述半导体芯片之间，设置于所述第1焊料中；以及
多个凸块，它们设置于所述电极基板和所述半导体芯片之间，
所述中间板的屈服强度在半导体装置的整个使用温度范围比所述电极基板及所述第1焊料的屈服强度大，
所述中间板在俯视观察时配置于所述多个凸块的内侧。
2.根据权利要求1所述的半导体装置，其特征在于，
所述使用温度范围为-55℃至200℃。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述中间板在俯视观察时配置于所述半导体芯片及所述第1焊料的内侧。
4.根据权利要求3所述的半导体装置，其特征在于，
所述半导体芯片的端部和所述中间板的端部的间隔比所述第1焊料的厚度大。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述第2焊料在俯视观察时配置于所述中间板的内侧。
6.根据权利要求1或2所述的半导体装置，其特征在于，
还具备镀膜，该镀膜覆盖所述中间板的表面，与所述中间板相比相对于所述第1焊料的湿润性高。
7.根据权利要求6所述的半导体装置，其特征在于，
所述镀膜的主要材料为镍。
8.根据权利要求1或2所述的半导体装置，其特征在于，
在所述中间板设置有多个贯穿孔。
9.根据权利要求6所述的半导体装置，其特征在于，
在所述中间板设置多个贯穿孔，
在所述多个贯穿孔的侧壁也形成有所述镀膜。
10.根据权利要求7所述的半导体装置，其特征在于，
在所述中间板设置多个贯穿孔，
在所述多个贯穿孔的侧壁也形成有所述镀膜。
11.根据权利要求8所述的半导体装置，其特征在于，
所述贯穿孔的大小小于或等于500μmΦ。
12.根据权利要求9所述的半导体装置，其特征在于，
所述贯穿孔的大小小于或等于500μmΦ。
13.根据权利要求10所述的半导体装置，其特征在于，
所述贯穿孔的大小小于或等于500μmΦ。
14.根据权利要求1所述的半导体装置，其特征在于，
所述中间板的厚度比所述多个凸块的高度薄。
15.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体芯片的厚度小于或等于100μm。
16.根据权利要求1或2所述的半导体装置，其特征在于，
所述电极基板的主要材料为铝。
17.根据权利要求1或2所述的半导体装置，其特征在于，
所述中间板的主要材料为铜。
18.根据权利要求1或2所述的半导体装置，其特征在于，
所述中间板的主要材料为钼。
19.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体芯片使用化合物半导体。
20.根据权利要求19所述的半导体装置，其特征在于，
所述化合物半导体的主要材料具有碳。
21.根据权利要求1或2所述的半导体装置，其特征在于，
该半导体装置被用于对汽车动力用电动机进行驱动的电源。
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Publication number Priority date Publication date Assignee Title
WO2020213167A1 (ja) * 2019-04-19 2020-10-22 三菱電機株式会社 半導体装置およびその製造方法
JP2022549450A (ja) * 2019-10-23 2022-11-25 アルファ・アセンブリー・ソリューションズ・インコーポレイテッド 電子アセンブリのための工学材料
JP7543655B2 (ja) * 2020-02-14 2024-09-03 富士電機株式会社 半導体モジュール
CN114743947B (zh) * 2022-04-11 2023-09-19 中国工程物理研究院电子工程研究所 基于to形式的功率器件封装结构及封装方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224560A (ja) * 2008-03-17 2009-10-01 Denso Corp 半導体装置およびその製造方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665650U (zh) * 1979-10-23 1981-06-01
JPS56172938U (zh) * 1980-05-23 1981-12-21
DE3685647T2 (de) * 1985-07-16 1993-01-07 Nippon Telegraph & Telephone Verbindungskontakte zwischen substraten und verfahren zur herstellung derselben.
JPS63251127A (ja) * 1987-04-06 1988-10-18 Ngk Insulators Ltd セラミック製部材と金属製部材の結合方法
US5188280A (en) * 1989-04-28 1993-02-23 Hitachi Ltd. Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
EP0568313A2 (en) * 1992-05-01 1993-11-03 Nippon CMK Corp. A method of manufacturing a multilayer printed wiring board
JP2989406B2 (ja) * 1993-01-29 1999-12-13 シャープ株式会社 半導体装置用プリプレーテッドフレーム及びその製造方法
US6070321A (en) * 1997-07-09 2000-06-06 International Business Machines Corporation Solder disc connection
US6158644A (en) * 1998-04-30 2000-12-12 International Business Machines Corporation Method for enhancing fatigue life of ball grid arrays
JP2000332369A (ja) * 1999-05-25 2000-11-30 Mitsui Mining & Smelting Co Ltd プリント回路板及びその製造方法
US6197618B1 (en) * 2000-05-04 2001-03-06 General Semiconductor Ireland Semiconductor device fabrication using adhesives
TW524030B (en) * 2000-10-02 2003-03-11 Matsushita Electric Ind Co Ltd Card-type recording medium and its manufacture method
JP2002203942A (ja) * 2000-12-28 2002-07-19 Fuji Electric Co Ltd パワー半導体モジュール
US20040078964A1 (en) * 2001-03-07 2004-04-29 Kazuhiro Itou Land portion of printed wiring board, method for manufacturing printed wiring board, and printed wiring board mounting method
JP4848539B2 (ja) * 2001-08-23 2011-12-28 Ｄｏｗａメタルテック株式会社 放熱板およびパワー半導体モジュール、ｉｃパッケージ
US6821667B2 (en) * 2001-10-01 2004-11-23 Delphi Technologies, Inc. Fuel cell stack having foil interconnects and laminated spacers
JP2003133337A (ja) 2001-10-23 2003-05-09 Nissan Motor Co Ltd 半導体実装構造および半導体実装方法
EP1737034A4 (en) * 2004-04-05 2010-11-03 Mitsubishi Materials Corp AI / AIN CONNECTING MATERIAL, BASE PLATE FOR A POWER MODULE, POWER MODULE AND PROCESS FOR PRODUCING AN AI / AIN COMPOUND MATERIAL
JP5491682B2 (ja) * 2004-08-13 2014-05-14 日立金属株式会社 太陽電池用平角導体及びその製造方法並びに太陽電池用リード線
JP4343117B2 (ja) * 2005-01-07 2009-10-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP4421528B2 (ja) * 2005-07-28 2010-02-24 シャープ株式会社 半田付け実装構造およびその製造方法、並びにその利用
JP4569423B2 (ja) * 2005-08-31 2010-10-27 株式会社日立製作所 半導体装置の製造方法
JP2007157863A (ja) * 2005-12-02 2007-06-21 Hitachi Ltd パワー半導体装置及びその製造方法
US20090186195A1 (en) * 2006-09-08 2009-07-23 Reactive Nanotechnologies, Inc. Reactive Multilayer Joining With Improved Metallization Techniques
JP2008098607A (ja) * 2006-09-13 2008-04-24 Hitachi Cable Ltd 太陽電池用接続リード線及びその製造方法並びに太陽電池
JP5272191B2 (ja) * 2007-08-31 2013-08-28 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP5241344B2 (ja) * 2008-06-30 2013-07-17 日立オートモティブシステムズ株式会社 パワーモジュール及び電力変換装置
US9236330B2 (en) 2010-11-29 2016-01-12 Toyota Jidosha Kabushiki Kaisha Power module
JP5325917B2 (ja) * 2011-03-17 2013-10-23 株式会社東芝 半導体装置及びその製造方法
JP2013113638A (ja) 2011-11-25 2013-06-10 Toyota Motor Corp 半導体装置
KR102007780B1 (ko) * 2012-07-31 2019-10-21 삼성전자주식회사 멀티 범프 구조의 전기적 연결부를 포함하는 반도체 소자의 제조방법
JP2014041876A (ja) 2012-08-21 2014-03-06 Mitsubishi Electric Corp 電力用半導体装置
JP5686128B2 (ja) * 2012-11-29 2015-03-18 トヨタ自動車株式会社 半導体装置
US8896118B2 (en) * 2013-03-13 2014-11-25 Texas Instruments Incorporated Electronic assembly with copper pillar attach substrate
CN105493272B (zh) * 2013-08-29 2019-03-15 三菱电机株式会社 半导体模块、半导体装置以及汽车
JP6399738B2 (ja) 2013-09-25 2018-10-03 富士電機株式会社 半導体装置
JP2016046403A (ja) * 2014-08-25 2016-04-04 トヨタ自動車株式会社 半導体装置
CN105575924B (zh) * 2014-10-15 2018-07-03 台达电子工业股份有限公司 功率模块
US9633957B2 (en) * 2014-11-28 2017-04-25 Infineon Technologies Ag Semiconductor device, a power semiconductor device, and a method for processing a semiconductor device
KR102430984B1 (ko) * 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224560A (ja) * 2008-03-17 2009-10-01 Denso Corp 半導体装置およびその製造方法

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US12009332B2 (en) 2024-06-11
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