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CN108321139A - 半导体器件和半导体器件的制造方法 - Google Patents

半导体器件和半导体器件的制造方法 Download PDF

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Publication number
CN108321139A
CN108321139A CN201711385296.3A CN201711385296A CN108321139A CN 108321139 A CN108321139 A CN 108321139A CN 201711385296 A CN201711385296 A CN 201711385296A CN 108321139 A CN108321139 A CN 108321139A
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CN
China
Prior art keywords
recess portion
semiconductor chip
electrode plate
conductive paste
bonding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711385296.3A
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English (en)
Inventor
榊原明德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Toyota Motor Corp
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Filing date
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Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Publication of CN108321139A publication Critical patent/CN108321139A/zh
Pending legal-status Critical Current

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Abstract

本发明涉及半导体器件和半导体器件的制造方法。一种半导体器件的制造方法包括将包含金属粒子的导电膏涂覆到电极板中的指定区域，电极板在其表面中包括凹部，指定区域与凹部相邻。半导体器件的制造方法包括将半导体芯片放置在导电膏上，使得半导体芯片的外周边缘位于凹部上方。所述半导体器件的制造方法包括通过在朝向电极板的方向上向半导体芯片施加压力的同时加热导电膏，使该导电膏硬化。

Description

半导体器件和半导体器件的制造方法
技术领域
本说明书要公开的技术涉及半导体器件和半导体器件的制造方法。
背景技术
日本专利申请公开No.2016-115865公开了用于将半导体芯片和电极板接合在一起的技术。在该技术中，将包含金属粒子的导电膏涂覆到电极板的表面，并且将半导体芯片布置在该导电膏上。此后，通过在朝向电极板的方向上向半导体芯片施加压力的同时加热导电膏来使导电膏硬化。因此，通过由于导电膏硬化而产生的接合层将半导体芯片和电极板接合在一起。
发明内容
为了用导电膏将半导体芯片和电极板接合在一起，必需在对半导体芯片和电极板之间的导电膏施加压力的同时加热导电膏。当导电膏被加热而硬化时，接合层被接合于半导体芯片和电极板。此后，当半导体芯片、接合层和电极板恢复到室温时，随着温度降低，这些成分收缩。在该处理期间，由于半导体芯片和接合层之间的线性膨胀系数的差异，导致高热应力作用于半导体芯片。特别地，高热应力作用于半导体芯片的外周边缘的附近。作用于半导体芯片的该热应力影响半导体芯片的可靠性。本发明提供了用于在通过导电膏将电极板和半导体芯片接合在一起的同时减小作用于半导体芯片的外周边缘附近的热应力的技术。
本发明的第一方面是一种半导体器件的制造方法。所述半导体器件的制造方法包括将包含金属粒子的导电膏涂覆到电极板中的指定区域，电极板在所述电极板的表面中包括凹部，所述指定区域与所述凹部相邻。所述半导体器件的制造方法包括将半导体芯片放置在所述导电膏上，使得所述半导体芯片的外周边缘位于所述凹部上方。所述半导体器件的制造方法包括通过在朝向所述电极板的方向上向所述半导体芯片施加压力的同时加热所述导电膏，使所述导电膏硬化。
当在硬化步骤中在朝向电极板的方向上向半导体芯片施加压力时，导电膏的被挤压在半导体芯片和电极板之间的部分朝向凹部流出。已经流出的导电膏与半导体芯片在外周边缘附近的部分和凹部的内表面接触。当被加热而硬化时，导电膏形成其中金属粒子相互接合的接合层。指定区域与半导体芯片之间的导电膏在高压下硬化。因此，指定区域和半导体芯片之间的导电膏硬化，形成低空隙率的接合层。通过该低空隙率接合层将指定区域和半导体芯片牢固接合在一起。另一方面，不向凹部和半导体芯片之间的导电膏施加此高压力。因此，凹部和半导体芯片之间的导电膏硬化，形成高空隙率的接合层。用该高空隙率接合层将凹部和半导体芯片接合在一起。当半导体芯片、接合层和电极板在导电膏硬化之后恢复到室温时，热应力作用于半导体芯片。如上所述，接合层与半导体芯片的外周边缘附近接合的部分具有高空隙率。因此，接合层的该部分有可能根据热应力而变形。因此，半导体芯片的外周边缘附近出现的热应力减轻。如以上已经描述的，根据该制造方法，能够减少半导体芯片的外周边缘附近出现的热应力。
在以上方面，在涂覆导电膏的步骤中，可不将导电膏涂覆到凹部的底表面，并且在使导电膏硬化的步骤中，已经从指定区域流入凹部的导电膏可与凹部的底表面接触。
根据该方面，接合层的与半导体芯片的外周边缘相邻的部分的表面呈现出相对于半导体芯片的下表面倾斜，以在延伸远离所述指定区域的同时朝向凹部的底表面偏移的形状。因此，接合层中不太可能出现裂缝。
在以上方面，可在凹部上方并且靠近半导体芯片的外周边缘的位置设置夹具。
根据该方面，可使导电膏免于向上隆起。
本发明的第二方面涉及半导体器件。所述半导体器件包括电极板，所述电极板包括凹部和与所述凹部相邻的指定区域，所述凹部在所述电极板的表面中。所述半导体器件包括接合层，所述接合层由金属构成并且覆盖从所述指定区域延伸至所述凹部的区域。所述半导体器件包括半导体芯片，所述半导体芯片被设置成面对所述指定区域和所述凹部，所述半导体芯片在所述指定区域和所述凹部上方与所述接合层接合，并且所述半导体芯片的外周边缘位于所述凹部上方。所述凹部中的接合层的空隙率高于所述指定区域中的所述接合层的空隙率。
根据该方面，将半导体芯片的外周边缘和电极板的凹部接合在一起的接合层具有高空隙率，使得能够抑制作用于半导体芯片的外周边缘的热应力。
在以上方面，接合层的与半导体芯片的外周边缘相邻的部分的表面可相对于半导体芯片的下表面倾斜，以在延伸远离所述指定区域的同时朝向凹部的底表面偏移。
根据该方面，接合层中不太可能出现裂缝。
在以上方面，接合层可以是导电膏。
在以上方面，凹部按环状形状在电极板的表面中延伸，包围所述半导体芯片，并且指定区域可以是被所述凹部包围的区域。
附图说明
以下，将参照附图来描述本发明的示例性实施例的特征、优点和技术和工业意义，在附图中，类似的标号表示类似的元件，并且其中：
图1是半导体器件10的垂直截面图；
图2是接合层14的第一部分14a的截面图；
图3是接合层14的第二部分14b的截面图；
图4是图示了半导体器件10的制造过程的视图(凹部20周边的放大截面图)；
图5是图示了半导体器件10的制造过程的视图(凹部20周边的放大截面图)；
图6是图示了半导体器件10的制造过程的视图(凹部20周边的放大截面图)；
图7是图示了比较例中的制造过程的视图；
图8是图示了修改例中的制造过程的视图(凹部20周边的放大截面图)；以及
图9是图示了修改例中的制造过程的视图(凹部20周边的放大截面图)。
具体实施方式
如图1中所示，实施例的半导体器件10具有半导体芯片12、接合层14和电极板16。半导体器件10包括除了接合层14和电极板16之外的布线构件(例如，其他电极板和键合引线)，但是这些在图1中未示出。
电极板16是由金属构成的导电板。在电极板16的上表面中设置凹部20。凹部20是按环状形状在电极板16的上表面中延伸的沟槽。电极板16的上表面被凹部20划分成中心部分22和外周部分24。中心部分22是被凹部20包围的部分。外周部分24是位于外周侧上比凹部20更远的部分。
半导体芯片12包括半导体基板和设置在半导体基板表面上的电极、绝缘层等。尽管并未示出，但是半导体芯片12的下表面被电极覆盖。半导体芯片12设置在电极板16上。半导体芯片12的外周边缘12a位于凹部20的上方。因此，半导体芯片12设置在电极板16上，使得当在平面图中沿着其堆叠方向观察半导体芯片12和电极板16时，整个外周边缘12a与凹部20重叠。
接合层14设置在电极板16和半导体芯片12之间。接合层14与电极板16和半导体芯片12(更具体地，构成半导体芯片12的下表面的电极)二者接合。电极板16和半导体芯片12通过接合层14彼此电连接。接合层14与电极板16的中心部分22和凹部20的内表面接合，并且不与外周部分24接触。接合层14与半导体芯片12的下表面的整个区域接合。接合层14在半导体芯片12和电极板16之间暴露于凹部20上方。接合层14的暴露表面相对于半导体芯片12的下表面倾斜。接合层14的暴露表面在从半导体芯片12的外周边缘12a朝向外周部分24延伸的同时(即，在延伸远离中心22的同时)，朝向凹部20的底表面偏移。图2和图3示意性示出了接合层14的横截面。如图2和图3中所示，接合层14具有其中金属粒子60彼此连接的结构。在金属粒子60之间存在空隙62。接合层14具有第一部分14a和第二部分14b。图2示出了处于预定位置的第一部分14a的横截面，图3示出了处于预定位置的第二部分14b的横截面。术语空隙率是指每单位体积的空隙62的比率。高空隙率是指每单位体积金属粒子60的比率低(即，金属粒子60的密度低)。空隙率从第一部分14a朝向第二部分14b增大。因此，第一部分14a的平均空隙率低于第二部分14b的平均空隙率。高空隙率的第二部分14b比低空隙率的第一部分14a更有可能经历弹性变形。如图1中所示，第一部分14a设置在电极板16的中心部分22和半导体芯片12之间，而第二部分14b设置在电极板16的凹部20和半导体芯片12之间。
接下来，将描述半导体器件10的制造方法。首先，如图4中所示，将导电膏30涂覆到电极板16的上表面的中心部分22。导电膏30是含有溶剂和扩散在溶剂中的金属粒子的膏剂。这里，导电膏30被涂覆到中心部分22的整个区域上方。导电膏30不被涂覆到凹部20和外周部分24。
接下来，如图5中所示，半导体芯片12被放置在导电膏30上。这里，半导体芯片12被布置成使得中心部分22的整个上侧被半导体芯片12覆盖，并且半导体芯片12的外周边缘12a位于凹部20的上方。
接下来，如图5中的箭头100所指示的朝向电极板16a的方向上向半导体芯片12施加压力的同时，将电极板16、导电膏30和半导体芯片12的层叠加热。随着压力因此在朝向电极板16的方向上施加到半导体芯片12，压力被施加到导电膏30。结果，如图5中箭头102所示，导电膏30从半导体芯片12和中心部分22之间的位置流向外侧。已经流出的导电膏30流入凹部20中。因此，如图6中所示，凹部20的内表面被导电膏30覆盖。换句话讲，导电膏30与凹部20的底表面和侧表面接触。虽然在图6中导电膏30在外周部分24一侧与凹部20的侧表面接触，但是导电膏30不需要与该侧表面接触。如图6中所示，已经从半导体芯片12和中心部分22之间的位置向外流向外侧的导电膏30与位于凹部20上方的半导体芯片12的下表面的部分接触。
加热使来自导电膏30的溶剂挥发。此外，当导电膏30在压力下被加热时，包含在导电膏30中的金属粒子彼此接合。因此，如图6中所示，导电膏30形成接合层14。这里，在高压下对位于中心部分22和半导体芯片12之间的导电膏30进行加热，使得导电膏30的该部分形成低空隙率的第一部分14a。另一方面，在相对低压下对位于凹部20和半导体芯片12之间的导电膏30进行加热，使得导电膏30的该部分形成高空隙率的第二部分14b。导电膏30如箭头102所指示地流入凹部20，使得接合层14在半导体芯片12和电极板16之间的表面呈现出倾斜以在从半导体芯片12的外周边缘12a朝向外周部分24延伸的同时向着凹部20的底表面偏移的形状。
此后，当电极板16、导电膏30和半导体芯片12的层叠被冷却到室温时，电极板16、导电膏30和半导体芯片12中的每个都收缩。由于线性膨胀系数的差异，导致在电极板16、导电膏30和半导体芯片12之中收缩量有所不同。因此，热应力作用于半导体芯片12。相比于半导体芯片12的中心部分中，在半导体芯片12的外周部分(即，外周边缘12a附近的部分)中有可能出现较高的热应力。然而，在该制造方法中，接合层14的高空隙率的第二部分14b与半导体芯片12的外周部分接合。因具有高空隙率，第二部分14b有可能经历弹性变形。第二部分14b的弹性变形使作用在半导体芯片12的外周部分上的热应力减轻。因此，根据该制造方法，可提高半导体芯片12的可靠性。此外，通过接合层14的第一部分14a，使其中有可能出现高热应力的半导体芯片12的中心部分牢固地接合于电极板16。因此，可确保半导体芯片12和电极板16之间的接合强度足够高。
图7示出了以下情况：当电极板16的上表面平坦(即，没有设置凹部20)时，电极板16和半导体芯片12通过接合层14(即，导电膏30)接合。当电极板16的上表面平坦时，已经在压力作用下从半导体芯片12和电极板16之间的区域流向外侧的导电膏30在与半导体芯片12的外周边缘12a相邻的位置处向上隆起，由此形成突出部120。突出部120可与半导体芯片12的外周边缘12a接触，这会导致半导体芯片12内部的元件短路。此外，当形成突出部120时，由于应力，导致有可能在突出部120中出现裂缝。如果已经在突出部120中出现的裂缝例如扩大直至半导体芯片12和电极板16之间的区域，则接合层14的电阻升高。相比之下，在用以上制造方法制造的半导体器件10中，接合层14的表面具有倾斜以在从半导体芯片12的外周边缘12a朝向外周部分24延伸的同时朝向凹部20的底表面偏移的形状。可使具有这种形状的接合层14免于与半导体芯片12的外周边缘12a接触。由此，可避免半导体芯片12内部的元件短路。此外，在具有这种形状的接合层14中，不太可能出现裂缝，使得可避免接合层14的电阻升高。
公知的是使用焊料将半导体芯片连接到电极板的技术。该技术有时涉及在电极板的表面中形成凹部，以使焊料免于过度润湿并且在电极板的表面上方扩散。通常，此凹部的外侧设置得比半导体芯片的外周边缘更远。相比之下，使用本说明书所公开的用于导电膏的凹部，使得半导体芯片的外周边缘位于该凹部上方。因此，因使用了凹部，通过允许导电膏流入凹部，可扩大导电膏的面积。本说明书所公开的凹部其次还具有使导电膏免于从指定区域扩散到超出凹部的外侧的功能。
在以上的制造方法中，由于制造变化，导致流入凹部20中的导电膏30的量会变得过大。如果倾向于出现这种现象，则在硬化导电膏30的步骤中，可在凹部20上方安装夹具80，如图8和图9中所示。夹具80靠近半导体芯片12的外周边缘12a设置，并且保持导电膏30向上隆起。在夹具80与电极板16的外周部分24之间留有间隙，以允许导电膏30朝向外周部分24流动。当大量导电膏30流入凹部20时，导电膏30从凹部20流向外周部分24的上侧，如图8和图9中的箭头104所示。因此，使导电膏30免于在凹部20中向上隆起。因此，在这种情况下，同样，接合层14的与半导体芯片12的外周边缘12a相邻的部分的表面呈现出在朝向外周部分24延伸的同时朝向凹部20的底表面偏移的形状。因此，能够使接合层14免于与外周边缘12a接触并且避免在接合层14中出现裂缝。

Claims (7)

1.一种半导体器件的制造方法，所述制造方法的特征在于，包括：
(a)将包含金属粒子的导电膏涂覆到电极板中的指定区域，所述电极板在所述电极板的表面中包括凹部，所述指定区域与所述凹部相邻；
(b)将半导体芯片放置在所述导电膏上，使得所述半导体芯片的外周边缘位于所述凹部上方；以及
(c)通过在朝向所述电极板的方向上向所述半导体芯片施加压力的同时加热所述导电膏，使所述导电膏硬化。
2.根据权利要求1所述的半导体器件的制造方法，其特征在于，
在所述步骤(a)中，不将所述导电膏涂覆到所述凹部的底表面，以及
在所述步骤(c)中，已经从所述指定区域流入所述凹部中的所述导电膏与所述凹部的所述底表面接触。
3.根据权利要求1或2所述的半导体器件的制造方法，其特征在于，还包括：(d)在所述凹部上方并且靠近所述半导体芯片的所述外周边缘的位置设置夹具。
4.一种半导体器件，所述半导体器件的特征在于，包括：
电极板，所述电极板包括凹部和与所述凹部相邻的指定区域，所述凹部在所述电极板的表面中；
接合层，所述接合层由金属构成，并且覆盖从所述指定区域延伸至所述凹部的区域；以及
半导体芯片，所述半导体芯片被设置成面对所述指定区域和所述凹部，所述半导体芯片在所述指定区域和所述凹部上方与所述接合层接合，并且所述半导体芯片的外周边缘位于所述凹部上方，其中，
所述凹部中的所述接合层的空隙率高于所述指定区域中的所述接合层的空隙率。
5.根据权利要求4所述的半导体器件，其特征在于，所述接合层的与所述半导体芯片的所述外周边缘相邻的部分的表面相对于所述半导体芯片的下表面倾斜，以在延伸远离所述指定区域的同时朝向所述凹部的底表面偏移。
6.根据权利要求4或5所述的半导体器件，其特征在于，所述接合层是导电膏。
7.根据权利要求4至6中的任一项所述的半导体器件，其特征在于，
所述凹部按环状形状在所述电极板的所述表面中延伸，以包围所述半导体芯片，以及
所述指定区域是被所述凹部包围的区域。
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