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CN108140636B - 半导体封装、半导体堆叠封装及存储器模块 - Google Patents

半导体封装、半导体堆叠封装及存储器模块 Download PDF

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Publication number
CN108140636B
CN108140636B CN201680042425.6A CN201680042425A CN108140636B CN 108140636 B CN108140636 B CN 108140636B CN 201680042425 A CN201680042425 A CN 201680042425A CN 108140636 B CN108140636 B CN 108140636B
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package
substrate
chip
pad
integrated
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CN108140636A (zh
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宋永僖
李�赫
宋基洪
郑准熙
尹圣植
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Priority claimed from KR1020150108804A external-priority patent/KR101961377B1/ko
Priority claimed from KR1020150108808A external-priority patent/KR101672967B1/ko
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Abstract

本发明的半导体封装包括：集成基板；底部芯片堆叠，安装在所述集成基板上，以芯片上芯片方式层叠有多个存储器半导体管芯，以负责整个存储器容量的一部分；至少一个顶部芯片堆叠，安装在所述底部芯片堆叠上，层叠有多个存储器半导体管芯，以负责整个存储器容量的剩余部分；集成电线，用于使所述底部芯片堆叠与所述顶部芯片堆叠电连接；及集成保护部件，用于密封所述集成电线。

Description

半导体封装、半导体堆叠封装及存储器模块
技术领域
本发明涉及在边缘(edge)包括侧垫(side pad)的封装基板、芯片堆叠、半导体封装及存储器模块，更具体而言，涉及根据固态硬盘(SSD)标准化的趋势，即使封装薄型化并小型化，也需要提供高容量超高速服务，最适合于此的LGA型NAND快闪存储器半导体封装得以实现，且即使未来所需的存储器容量翻倍，也使用分开的芯片堆叠来进行一次封装，并且使用LGA封装基板侧面的侧垫来以引线键合各个基板的方式对多个多种存储器芯片堆叠进行集成封装，从而，即使使用相同的面积也能够满足薄型化和小型化的需求的半导体封装。
背景技术
近年来，随着电子产品功能的增加，尺寸越来越小，从而需要在同一面积安装更多的半导体。因此，仅通过简单的芯片堆叠技术或封装堆叠技术无法满足最近电子便携式装置的小型化以及移动产品的各种功能。
图1为示出根据现有技术的16段多芯片封装的构成的侧面图。
参照图1，在现有半导体NAND快闪存储器封装10中层叠一个或更多管芯14。但是，如果考虑批量生产，则可层叠管芯14的数量受到很大限制。这成为在实现高容量半导体NAND闪存中的容量限制的原因。
尽管如此，如果考虑到高容量存储器的趋势形成16段堆叠，则从基板12的距离较远的上管芯14的电特性劣化，导致收率降低，且在整体上焊线16的长度变长。
另一方面，为了改善收率降低，已经引入了封装叠加(Package on Package)技术。
图2为示出根据现有技术的BGA封装叠加构成的侧面图。
参照图2，PoP封装20通过球栅阵列(BGA)连接封装相互之间，因此，由于焊球22而无法实现SSD的薄型化和小型化的需求。
发明内容
发明要解决的问题
因此，本发明为了解决如上所述的现有技术的问题而提出，本发明的目的在于，提供能够实现高容量化和超薄型化的需求的半导体封装。
本发明的另一目的在于，在垂直排列有存储器半导体管芯的半导体封装中，即使存储器容量增加，封装高度也可以最小化且保持电特性的半导体封装。
用于解决问题的方案
为达到上述目的，根据本发明的一个特征，本发明的半导体封装包括：集成基板；底部芯片堆叠，安装在所述集成基板上，以芯片上芯片方式层叠有多个存储器半导体管芯，以负责整个存储器容量的一部分；至少一个顶部芯片堆叠，安装在所述底部芯片堆叠上，层叠有多个存储器半导体管芯，以负责整个存储器容量的剩余部分；集成电线，用于使所述底部芯片堆叠与所述顶部芯片堆叠电连接；及集成保护部件，用于密封所述集成电线。
根据本发明的另一个特征，本发明的芯片堆叠包括：基板，在上面印刷基板垫和侧垫；多芯片封装类型的多个存储器半导体管芯；连接部件，用于使所述存储器半导体管芯电连接；及底部保护部件，用于覆盖所述半导体管芯和所述连接部件全部及所述基板的一部分。
根据本发明的再一特征，本发明的封装基板包括：绝缘PCB主体；上布线图案，在所述印刷电路板主体的上面内侧印刷基板垫，而在上面边缘印刷侧垫；及再布线图案，用于在所述PCB主体内部使所述基板垫与所述侧垫电连接。
本发明的一种半导体堆叠封装，包括：集成基板；底部封装，附着于所述集成基板上；顶部封装，通过接合部件层叠在所述底部封装上；集成电线，用于使所述底部封装与所述顶部封装电连接；以及集成保护部件，用于密封所述集成电线。
本发明的一种半导体堆叠封装，包括：集成基板；底部封装，层叠在所述集成基板上；顶部封装，通过接合部件层叠在所述底部封装上；集成电线，用于使所述底部封装与所述顶部封装电连接，且使所述底部封装的基板与所述顶部封装的基板电连接；以及集成保护部件，用于密封所述集成电线。
本发明的一种存储器模块，包括：模块基板；多个DRAM存储器封装，安装在所述模块基板上；多个接触端子，以预定间隔排列在所述模块基板的一侧，用于电连接所述DRAM存储器封装，其中，所述DRAM存储器封装包括：集成基板；底部封装，层叠在所述集成基板上，使底部基板的边缘没有被底部保护部件覆盖而暴露；顶部封装，通过接合部件层叠在所述底部封装上，使顶部基板的边缘没有被顶部保护部件覆盖而暴露；集成电线，使所述底部封装与所述顶部封装电连接，且使所暴露的所述底部基板的边缘与所述顶部基板的边缘电连接；以及集成保护部件，用于密封所述集成电线。
发明的效果
如上所述，根据本发明的结构，可期待如下效果。
第一，由于存储器半导体管芯不是被强制地垂直排列，而是被分成多个芯片堆叠并被封装，因此，可以从根本上防止由半导体管芯的垂直层叠引起的收率降低。
第二，由于各个基板介于多个存储器半导体管芯之间并在各个基板的侧表面通过引线键合使分开的封装电连接，因此导电线的长度原本被缩短，并且引线键合工艺变得容易。
第三，由于各个基板介于多个存储器半导体管芯之间，因此通过有效地分散在高容量存储器半导体管芯中产生的高热量来能够防止热特性劣化的效果。
附图说明
图1为示出根据现有技术的16段多芯片封装(MCP)构成的侧面图。
图2为示出根据现有技术的BGA封装叠加(PoP)构成的侧面图。
图3为示出根据本发明的LGA半导体封装构成的透视图。
图4及图5为根据各种多芯片封装实施例的图3的侧面图。
图6为示出根据本发明的芯片堆叠构成的透视图。
图7a和图7b为以硬封装和软封装分别表示根据本发明的包括4个4段芯片堆叠的一实施例的LGA半导体封装的构成的侧面图。
图8a和图8b为以硬封装和软封装分别表示根据本发明的包括4个4段芯片堆叠的另一实施例的LGA半导体封装的构成的侧面图。
图9为示出根据本发明的包括4个4段芯片堆叠的另一实施例的LGA半导体封装构成的侧面图。
图10、图11及图12为分别示出将根据本发明的侧垫应用于BOC封装的构成的侧面图。
图13为示出将根据本发明的侧垫应用于BGA半导体封装的构成的侧面图。
图14为示出根据本发明的柔性4堆叠半导体封装的构成的侧面图。
图15为示出包括应用根据本发明的DRAM存储器半导体封装的高密度存储器模块构成的电子电路设备构成的框图。
具体实施方式
通过参照与附图1同详细说明的实施例，将更加明确本发明的优点、特征及用于实现其的方法。但是本发明并不局限于以下公开的实施例，而可以以多种不同的形态来体现，本实施例仅仅用于使本发明的公开更加完整，并向本发明所属技术领域的普通技术人员完整地告知本发明的范畴，本发明仅由发明要求保护范围来定义。为了明确对本发明的说明，可夸张显示附图中的模块及单元的位置及相对大小。在说明书全文中，相同的附图标记表示相同的结构要素。
在此，参考作为本发明的理想实施例的示意图的横截示意图来描述本发明的实施例。这样，可以预料诸如制造技术和/或公差可能导致示意图的变化。因此，本发明的实施例不应该被理解为局限于在此示出的特定形状，而且包括例如由于制造而导致的形状的偏差。因此，在图中示出的区域实际上是示意性的，并且其形状用于描述区域的实际形状，并且不用于限定本发明的范围。
下面，参照附图对具有上述构成的根据本发明的LGA半导体封装的优选实施例进行详细说明。
作为一个例子，本发明的LGA半导体封装将16段芯片堆叠NAND闪存半导体管芯分为4个4段芯片堆叠封装来进行封装，然后重新将其封装在集成基板上。
若在高容量层叠式存储器半导体管芯被分割并封装的状态下进行最终封装，则能够解决由于大容量层叠而导致的收率降低问题，并且可以保持电特性。
参照图1至图6，本发明的LGA半导体封装100包括：集成基板110；分割的底部芯片堆叠200，安装在所述集成基板110上，多个存储器半导体管芯220以芯片上芯片(chip-on-chip)方式层叠在所述底部芯片堆叠200上，以负责整个存储器容量的一部分；分割的顶部芯片堆叠300，使用接合部件120安装在所述底部芯片堆叠200上，多个存储器半导体管芯220层叠在所述顶部芯片堆叠300上，以负责整个存储器容量的剩余部分；集成电线130，用于使所述底部芯片堆叠200与所述顶部芯片堆叠300电连接；及集成保护部件140，用于密封所述集成电线130。
在本发明的实施例中，芯片堆叠被分为底部芯片堆叠200和顶部芯片堆叠300，但只要多个上述封装可以相互接合，就在包括至少两个封装的前提下，如图7a和图8a所示，优选分成4个封装。例如，芯片堆叠可以分为第一芯片堆叠200、第二芯片堆叠300a、第三芯片堆叠300b及第四芯片堆叠300c。
然而，为了方便说明，设置在集成基板110侧的至少一个封装为底部芯片堆叠200，而接合在底部芯片堆叠200上的至少一个封装为顶部芯片堆叠300。
尤其，参照图6，底部芯片堆叠200包括：底部基板210；多个存储器半导体管芯220，以芯片上芯片方式层叠在所述底部基板210上；贯通电极或焊线的连接部件230,所述贯通电极或焊线用于电连接多个存储器半导体管芯220；及底部保护部件240，用于覆盖底部基板210和半导体管芯220。
底部基板210包括：绝缘PCB主体(没有附图标记)；上布线图案(图中未示出)，在PCB主体的上面包括基板垫212和侧垫214；下布线图案(图中未示出)，在PCB主体的底面包括外部连接终端；及贯通电极和/或再布线图案(图中未示出)，在PCB主体内部使基板垫212与外部连接终端连接或使基板垫212与侧垫214电连接。
本发明的绝缘PCB主体可以包括具有柔性的柔性印刷线路板(Flexible PrintedCircuit Board；FPCB)基板。例如，最近已经开发了自由弯曲的柔性半导体基板和半导体管芯，此外，已经开发了包括上述基板和管芯的可自由弯曲的柔性半导体封装，使得绝缘PCB主体可以使用FPCB来构成。即，柔性LGA半导体封装可以通过柔性基板、柔性管芯、柔性线和柔性模制来实现(参见图7b和图8b)。
例如，底部芯片堆叠200可以由柔性半导体封装构成。为此，底部基板210可以弯曲或卷绕。为此，底部基板210可以由聚合物材料形成。例如，柔性基板通常可以由聚酰亚胺(PI)、聚酯(polyester)、聚萘二甲酸乙二醇酯(PEN)、特氟龙(Teflon)、聚对苯二甲酸乙二醇酯(PET)或其他聚合物(polymeric)材料形成。
基板垫212形成在底部基板210上，且包括作为柔性材料的铜(Cu)、钛(Ti)、铝(Al)或金属合金，以能够形成弯曲的导电膜。上述基板垫212可以包括通过借助光刻工艺的沉积和蚀刻形成的导电金属线，但可以包括通过印刷工艺印刷导电油墨而形成的导电金属线，以便更易弯曲。
存储器半导体管芯220的元件集成在硅基板上，且但硅基板的厚度不超过几十微米，使得硅基能够弯曲。
另一方面，用于接合存储器半导体管芯220的粘合构件(图中未示出)需要包括具有优异粘合力的聚合物材料，以便具有高粘合力的物质，使得即使底部基板210弯曲或卷绕，在基板210与半导体管芯220之间也不会发生剥离或分离现象。
底部保护部件240可以由弯曲或卷绕的材料形成。例如，保护部件240包括能够提供应力的材料，且可以包括聚合物材料(polymer)或橡胶(rubber)材料。尤其，保护部件240可以包括聚酰亚胺(polyimide)。
因此，即使半导体封装200被任意地弯曲或卷绕，其也是柔性且可拉伸的，而且，即使由于伸长和收缩而出现应力，也能防止由应力造成的损伤。尤其，当底部基板210被弯曲或拉伸时，形成在基板210上的基板垫212不会切断或从基板210剥离，从而可以防止由于接触不良(contact fail)而引起的功能失效。
另一方面，根据本发明的一实施例，通过使用再布线图案来将基板垫212直接连接到侧垫214，从而可以省略外部连接终端。
底部芯片堆叠200可以由各种类型的存储器半导体管芯以各种形式层叠在底部基板210上的常规半导体封装组成。其中，多层存储器半导体管芯可以采用如下的多芯片封装(Multi Chip Package；MCP)的形式。
如图4所示，存储器半导体管芯220可以以阶梯方式层叠排列，或者如图5所示，可以垂直层叠排列(参见附图标记200)或锯齿层叠排列(参见附图标记300)。使存储器半导体管芯的堆叠不会超过8段堆叠，以防止由于高速操作而导致的电特性的劣化。然而，不排除平面阵列部分结合，并且考虑到SSD的大小和存储容量来可以确定各种阵列形式。并且，这也不会妨碍与逻辑半导体管芯的对齐。
参照图5，在不是通过引线键合而是通过贯通电极(图中未示出)电连接层叠在芯片堆叠300的存储器半导体管芯220彼此之间的情况下，当上下垂直层叠的半导体管芯需要垂直对齐时，半导体管芯220可以设计成直接垂直层叠。
如上所述，本发明的底部基板210，进一步形成有侧垫214，以便将顶部芯片堆叠300电连接到存储器半导体管芯220未被接合的边缘。上述侧垫214是通过集成电线130使顶部芯片堆叠300和底部芯片堆叠200电连接的区域，也是通过再分布线RDL连接到各个半导体管芯220的区域。
在本发明中，由于顶部芯片堆叠300和底部芯片堆叠200通过LGA类型的集成电线130在一侧连接，因此，多个封装没有通过BGA连接，从而可以从根本上防止封装的高度(High)增加并且可以使封装薄型化。
并且，通过将多个封装分割成单独的芯片堆叠，导电线的长度变短，从而，尽管进行高速操作，电特性得以保持。例如，每个基板210介于各个多个存储器半导体管芯220之间，并且各个基板210用作导线穿过的终端，结果，可以防止导电线的长度变长。
侧垫214通过与底部基板210的再分布线RDL连接来与层叠在底部基板210上的多个存储器半导体管芯220电连接。可以通过集成电线130连接各个芯片堆叠200和300之间，而使用现有外部连接终端来连接底部芯片堆叠200和集成基板110之间。
反而，在本发明的实施例中，无需用于使底部芯片堆叠200与外部电连接的外部接触端子设置在下部，而可以省略所述外部接触端子。例如，如果侧垫214和多个存储器半导体管芯220通过再分布线RDL连接，则由于不将外部接触端子设置在下部而可以显着减小半导体封装的高度(High)。
结果，每个基板210插入于多个存储器半导体管芯220之间，从而可以通过具有优异导热率的各个基板210有效地排出存储器半导体管芯220中产生的热量，以便能够改善热特性。
通过如上所述分割底部芯片堆叠200和顶部芯片堆叠300，可以被独立地设计相关封装的功能，无论封装在相关封装中的半导体管芯的种类如何，都可以层叠任何类型的半导体管芯，从而可以更广泛地使用封装。
由于本发明的存储器半导体管芯可以分成多个芯片堆叠来用于LGA封装，并且每个LGA芯片堆叠可以通过使用设置在LGA封装基板的侧面空间中的侧垫来电连接，而无需引线键合，因此，没有必要只采用上下垂直排列，而如图9所示，在LGA封装基板上可以通过各种方式组装各种不同的分割的芯片堆叠。
作为一个例子，本发明的BGA半导体封装将16段芯片堆叠的DRAM半导体管芯分为4个4段芯片堆叠封装来进行封装，然后重新将其封装在集成基板上。
如上所述，若在高容量层叠式存储器半导体管芯被分割并封装的状态下进行最终封装，则能够解决由于大容量层叠而导致的收率降低问题，并且可以保持电特性。
参照图10，本发明的BOC半导体堆叠封装1100包括：集成基板1110；分割的BOC底部封装1200，附着于集成基板1110上；分割的BOC顶部封装1300，通过接合部件1120层叠在底部封装1200上；集成电线1130，使底部封装1200与顶部封装1300电连接；及集成保护部件1140，用于密封集成电线1130。
BOC底部封装1200包括：底部基板1210，在中心具有窗口1202；第一芯片1222，以面对活性面的方式结合在底部基板1210上，且第一焊垫1222a通过所述窗口1202向下暴露；及第二芯片1224，第二芯片1224的非活性面与第一芯片1222的非活性面接合，第二焊垫1224a形成在第二芯片1224的活性面。
第一焊垫1222a通过窗口1202与底部基板1210的底面引线键合，且第一焊垫1222a和第一焊线1222b由第一保护部件1222c模制而成。
第二焊垫1224a与底部基板1210的上面引线键合，且第二焊垫1224a和第二焊线1224b由第二保护部件1224c模制而成。在底部基板1210的底面形成有焊球1212。
BOC顶部封装1300包括：顶部基板1310，在中心具有窗口1302；第一芯片1322，以面对活性面的方式结合在顶部基板1310上，且第一焊垫1322a通过所述窗口1302向下(以附图为基准向上)暴露；及第二芯片1324，第二芯片1324的非活性面与第一芯片1322的非活性面接合，第二焊垫1324a形成在第二芯片1324的活性面。
第一焊垫1322a通过窗口1302与顶部基板1310的底面引线键合，且第一焊垫1322a和第一焊线1322b由第一保护部件1322c模制而成。
第二焊垫1324a与顶部基板1310的上面引线键合，且第二焊垫1324a和第二焊线1324b由第二保护部件1324c模制而成。由于在顶部基板1310的底面设有集成电线1130，因此不形成额外的焊球。
尤其是，在底部基板1210和顶部基板1310中没有被第二保护部件1224c和第二保护部件1324c覆盖的边缘区域中还包括侧垫(图中未示出)，从而，集成电线1130连接在侧垫之间以使顶部封装1300和底部封装1200电连接。
另一方面，本发明的存储器半导体堆叠封装提供柔性存储器封装，以便应用于需要高容量和高规格的可穿戴设备。
作为一个例子,BOC底部封装1200可以由柔性半导体封装构成。为此，底部基板1210可以弯曲或卷绕。为此，底部基板1210可以由聚合物材料形成。例如，柔性基板通常可以由聚酰亚胺(PI)、聚酯(polyester)、聚萘二甲酸乙二醇酯(PEN)、特氟龙(Teflon)、聚对苯二甲酸乙二醇酯(PET)或其他聚合物(polymeric)材料形成。
形成在底部基板1210上的焊垫1222a包括作为柔性材料的铜(Cu)、钛(Ti)、铝(Al)或金属合金，以能够形成弯曲的导电膜。上述焊垫1222a可以包括通过借助光刻工艺的沉积和蚀刻形成的导电金属线，但可以包括通过印刷工艺印刷导电油墨而形成的导电金属线，以便更易弯曲。
存储器第一芯片1222或第二芯片1224的元件集成在硅基板上，且但硅基板的厚度不超过几十微米，使得硅基板能够弯曲。
另一方面，用于接合第一芯片1222或第二芯片1224的粘合构件(图中未示出)需要包括具有优异粘合力的聚合物材料，以便具有高粘合力的物质，使得即使底部基板1210弯曲或卷绕，在底部基板1210与半导体管芯1220之间也不会发生剥离或分离现象。
保护部件1224c可以由弯曲或卷绕的材料形成。例如，保护部件1224c包括能够提供应力的材料，且可以包括聚合物材料(polymer)或橡胶(rubber)材料。尤其，保护部件1224c可以包括聚酰亚胺(polyimide)。
因此，即使BOC半导体封装1200被任意地弯曲或卷绕，其也是柔性且可拉伸的，而且，即使由于伸长和收缩而出现应力，也能防止由应力造成的损伤。尤其，当底部基板1210被弯曲或拉伸时，形成在基板1210上的焊垫1222a不会切断或从基板1210剥离，从而可以防止由于接触不良(contact fail)而引起的功能失效。
参照图11，本发明的另一实施例的BOC半导体堆叠封装1100包括：集成基板1110；分割的BOC第一封装1200；分割的BOC第二封装1300，通过第一隔片1120层叠在第一封装1200上；分割的BOC第三封装1400，通过第二隔片1120层叠在第二封装1300上；集成电线1130，用于使第一封装1200、第二封装1300和第三封装1400电连接；及集成保护部件1140，用于密封集成电线1130。
此时，第一隔片和第二隔片1120执行在第一封装1200的保护部件1224c和第二封装1300的基板1310之间提供空间并接合第一封装1200和第二封装1300两者的功能。
参照图12，根据本发明的再一实施例的BOC半导体堆叠封装1100包括：集成基板1110；分割的BOC第一封装1200；分割的BOC第二封装1300，通过在第一封装1200上且与第一封装1200部分重叠的接合部件1120以阶梯形式层叠；分割的BOC第三封装1400,通过在第二封装1300上且与第二封装1300部分重叠的接合部件1120层叠；集成电线1130，用于使第一封装1200、第二封装1300和第三封装1400电连接；及集成保护部件1140，用于密封集成电线1130。
随着电子产品的小型化及轻量化，封装尺寸逐渐减小。根据开发上述高集成度和高性能封装的努力，已经引入了球栅阵列(Ball Grid Array:BGA)封装，在所述球栅阵列中封装的外部电连接装置采用栅格阵列(grid array)方式。
然而，如上所述，BGA半导体封装具有能够应对半导体芯片的输入输出引脚数量的增加，将封装尺寸减小至半导体芯片的水平，同时减少电连接部的电感成分等优点，但与此相反，当以表面安装型(Surface Mounting Technology)半导体封装方式通过焊球安装在PCB上时，焊料量不均匀，从而可能发生接触不良(contact fail)。尤其，如果焊料量过多，则在焊接过程中相邻焊球之间可能发生短路。
参照图13，根据本发明的一实施例的BGA半导体堆叠封装2100包括：集成基板2110；BGA底部封装2220，层叠在集成基板2110上；BGA顶部封装2230，通过接合部件2120层叠在底部封装2220上；集成电线2130，使BGA底部封装2220和BGA顶部封装2230电连接；及集成保护部件2140，用于密封集成电线2130。
BGA底部封装2220由底部基板2210和在底部基板2210上的多个芯片2222、2224、2226、2228构成。各个存储器半导体芯片2222、2224、2226、2228包括：集成电路(图中未示出)，形成在各个存储器半导体芯片内部；多个芯片垫2222a、2224a、2226a，与所述集成电路电连接；及多个贯通电极(图中未示出)，使多个芯片垫2222a、2224a、2226a电连接。多个芯片2222、2224、2226、2228可以通过粘合构件2222b、2224b、2226b层叠。
多个芯片2222、2224、2226、2228可以包括存储器半导体芯片。存储器半导体芯片可以包括非易失性存储器和易于访问的易失性存储器。例如，可以包括闪存存储器芯片、DRAM芯片、PRAM芯片或其组合。
焊球2212形成在底部基板2210的底面，而覆盖多个芯片2222、2224、2226、2228的保护部件2214形成在底部基板2210的上面。
BGA顶部封装2230由顶部基板2310和在顶部基板2310上的多个芯片2322、2324、2326、2328构成。各个存储器半导体芯片2322、2324、2326、2328包括：集成电路(图中未示出)，形成在各个存储器半导体芯片内部；多个芯片垫2322a、2324a、2326a，与所述集成电路电连接；及多个贯通电极(图中未示出)，电连接多个芯片垫2322a、2324a、2326a。多个芯片2322、2324、2326、2328可以通过粘合构件2322b、2324b、2326b层叠。
多个芯片2322、2324、2326、2328也同样地可以包括包含易失性或非易失性存储器的存储器半导体芯片。
覆盖多个芯片2322、2324、2326、2328的保护部件2314形成在顶部基板2310的上面，但在顶部基板2310的底面未形成焊球而省略。
尤其，在没有被保护部件2214覆盖的底部基板2210和没有被保护部件2314覆盖的顶部基板2310的边缘区域还包括侧垫2310d、2210e，从而，集成电线2130连接到侧垫2310d、2210e之间，以使顶部封装2230和底部封装2220电连接。
例如，顶部基板2310可以包括：裸基板2310a；连接垫2310b，暴露于裸基板2310a的上面；再布线图案2310c，用于在裸基板2310a的内部电连接连接垫2310b；侧垫2310d，通过再布线图案2310c与连接垫2310b连接；及钝化层，涂布在裸基板2310a上，以便使所述连接垫2310b暴露且保护再布线图案2310c。
裸基板2310a可以包括硅基板、玻璃基板或蓝宝石基板，尤其，可以包括柔性基板。
例如，底部基板2210可以包括：裸基板2210a；上连接垫2210b，暴露于裸基板2210a的上面；下连接垫2210c,暴露于裸基板2210a的底面；再布线图案2210d，用于在裸基板2210a的内部电连接上连接垫2210b和下连接垫2210c；侧垫2210e，通过再布线图案2210d与上连接垫2210b和下连接垫2210c连接；及钝化层(图中未示出)，涂布在裸基板2210a上，以便上连接垫2210b和下连接垫2210c暴露且保护再布线图案2210d。
另一方面，图14示出用于构成高密度存储器模块的根据本发明的4叠层半导体封装的结构。相关半导体堆叠封装可以由柔性封装构成。
参照图14，根据本发明的另一实施例的半导体4堆叠封装2100包括：集成基板2110；BGA第一封装2200,层叠在集成基板2110上；BGA第二封装2300，通过接合部件2120层叠在第一封装2200上；BGA第三封装2400,通过接合部件2122层叠在第二封装2300上；BGA第四封装2500,通过接合部件2124层叠在第三封装2400上；集成电线2130，用于电连接第一封装2200和第二封装2300；集成电线2132，用于电连接第二封装2300和第三封装2400；集成电线2134，用于电连接第三封装2400和第四封装2500；及集成保护部件2140，用于密封集成电线2130、2132、2134。
图15为示意性示出根据本发明的一实施例的包括DRAM存储器封装的高密度存储器模块的构成。
参照图15，本发明的高密度存储器模块400包括：模块基板410；多个DRAM存储器封装420，安装在模块基板410上；及多个接触端子430，以预定间隔排列在模块基板410的一侧，用于电连接DRAM存储器封装420。
模块基板410可以包括PCB基板，尤其，可以包括柔性PCB。模块基板410的两面都可以使用。尽管图中示出了8个所述DRAM存储器封装420，但是不限于此。并且，模块基板410还可包括用于控制DRAM存储器封装420的半导体封装。
DRAM存储器封装420可以包括根据本发明的至少一个DRAM存储器半导体封装1100、底部封装1200或顶部封装1200、1300。
接触端子430可以包括用于数据输入输出的导电金属。接触端子430可以根据高密度存储器模块400的标准规格而不同地设定。
根据本发明的一实施例的电子电路装置包括：微处理器，布置在电路板上；主存储电路和子存储电路，与微处理器进行通信；输入信号处理电路，向微处理器发送命令；输出信号处理电路，从微处理器接受命令；及通信信号处理电路，用于与其他电路板交换电信号。箭头可以被理解为意味着电信号可以被传输的路径。
微处理器可以接收并处理各种电信号，输出处理结果，控制电子电路装置的其他部件。例如，微处理器可以被理解为中央处理单元(central processing unit；CPU)和/或主控制单元(main control unit；MCU)等。
主存储电路可以临时存储微处理器总是或经常需要的数据。主存储电路需要快速响应，因此可以由半导体存储器构成。更详细而言，主存储电路可以是被称为高速缓冲(cache)存储器的半导体存储器，或者可以由SRAM、DRAM、RRAM及其应用半导体存储器、其他半导体存储器构成。在本实施例中，主存储电路可以包含根据本发明的至少一个DRAM存储器半导体封装1100，或底部封装1200或顶部封装1200、1300。
子存储电路可以是大容量存储装置，也可以是非易失性半导体存储器或使用磁场的硬盘驱动器。子存储电路可以包括根据本发明的至少一个DRAM存储器半导体封装1100，或底部封装1200或顶部封装1200、1300。
输入信号处理电路可以将外部命令转换为电信号，或者将从外部传输的电信号传输至微处理器。输入信号处理电路可以包括例如键盘、鼠标、触摸板、图像识别装置等。输入信号处理电路可以包括根据本发明的至少一个DRAM存储器半导体封装1100或底部封装1200或顶部封装1200、1300。
输出信号处理电路可以是用于向外传输由微处理器处理的电信号的组件。例如，输出信号处理电路可以是图形卡、图像处理器、光学换能器、光束板卡或各种功能接口电路。所述输出信号处理电路可以包括根据本发明的至少一个DRAM存储器半导体封装1100或底部封装1200或顶部封装1200、1300。
通信电路是用于不是通过所述输入信号处理电路或输出信号处理电路而是直接将电信号发送到其他电子系统或其他电路板或从其他系统或其他电路板接收电信号的组件。例如，通信电路可以是个人计算机系统的调制解调器、适配器或各种接口电路等。通信电路可以包括根据本发明的至少一个DRAM存储器半导体封装1100或底部封装1200或顶部封装1200或1300。
如上所述，以往通过将半导体管芯单独封装并且完成测试的半导体管芯上下层叠的封装叠加(package on package；POP)来实现高容量存储器，然而，本发明的技术思想如下构成，即，由于随着堆叠管芯数量的增加，成品率成比例增加，因此本发明的BGA半导体封装被分割成4段或8段芯片堆叠来进行封装，并且每个芯片堆叠以使用基板侧面的侧垫来引线键合的方式进行整合，从而实现16段高容量存储器。在如上所述的本发明的基本技术思想的范围内，本领域所属领域的技术人员可以做出许多其他修改。
工业实用性
本发明的存储器封装可能被用于应用在需要高容量的SSD产品和可穿戴设备的柔性存储器封装，或者可能被用于应用在需要高容量的可穿戴设备的柔性存储器封装。

Claims (8)

1.一种半导体封装，其特征在于，包括：
集成基板；
底部芯片堆叠，安装在所述集成基板上，所述底部芯片堆叠包括：
底部基板;
存储器半导体管芯，层叠在所述底部基板上；
底部保护部件，覆盖层叠在所述底部基板上的所述存储器半导体管芯；以及
至少一第一侧垫，设置在所述底部基板的边缘区域，其中所述底部基板具有被所述底部保护部件覆盖的表面区域以及未被所述底部保护部件覆盖的另一表面区域，且所述底部基板的边缘区域位在未被所述底部保护部件覆盖的所述另一表面区域；
两个以上的顶部芯片堆叠，安装在所述底部芯片堆叠上，且所述顶部芯片堆叠彼此层叠，每一所述顶部芯片堆叠包括：
顶部基板；
存储器半导体管芯，层叠在所述顶部基板上；
顶部保护部件，覆盖层叠在所述顶部基板上的所述存储器半导体管芯；以及
至少一第二侧垫，设置在所述顶部基板的边缘区域，其中所述顶部基板具有被所述顶部保护部件覆盖的表面区域以及未被所述顶部保护部件覆盖的另一表面区域，且所述顶部基板的边缘区域位在未被所述顶部保护部件覆盖的所述另一表面区域，
其中，所述至少一第一侧垫以及所述至少一第二侧垫分别设置在所述底部保护部件以及所述顶部保护部件的外部，
其中，所述底部芯片堆叠的所述至少一第一侧垫与彼此层叠的两个以上的所述顶部芯片堆叠的所述至少一第二侧垫排列成上升阶梯状。
2.根据权利要求1所述的半导体封装，其特征在于，
所述底部芯片堆叠还包括：
多芯片封装类型的所述存储器半导体管芯;以及
连接部件，电连接所述存储器半导体管芯。
3.根据权利要求1所述的半导体封装，其特征在于，
所述底部基板包括：
印刷电路板主体；
上布线图案，在所述印刷电路板主体的上面，包括基板垫和所述至少一第一侧垫；
下布线图案，在所述印刷电路板主体的底面，包括外部连接终端；以及
贯通电极或再布线图案，在所述印刷电路板主体内部使所述基板垫连接到所述外部连接终端，或者，使所述基板垫电连接到所述至少一第一侧垫。
4.根据权利要求3所述的半导体封装，其特征在于，
所述基板垫由所述底部保护部件覆盖，且
所述至少一第一侧垫由集成保护部件覆盖。
5.根据权利要求4所述的半导体封装，其特征在于，
所述顶部芯片堆叠包括3个封装，以将16段堆叠分成4个4段芯片堆叠。
6.一种半导体堆叠封装，其特征在于，包括：
集成基板；
底部封装，附着于所述集成基板上，
所述底部封装包括：
底部基板，在中心具有窗口；
第一芯片，以面对活性面的方式结合在所述底部基板上，且第一焊垫通过所述窗口向下暴露；
第二芯片，所述第二芯片的非活性面与所述第一芯片的非活性面接合，且第二焊垫形成在所述第二芯片的活性面的一侧；
第一焊线，用于使所述第一焊垫通过所述窗口与所述底部基板的底面引线键合；
第一保护部件，用于覆盖所述第一焊线；
第二焊线，用于使所述第二焊垫与所述底部基板的上面引线键合；以及
第二保护部件，用于覆盖所述第二焊线，
其中所述底部基板在没有被所述第二保护部件覆盖的边缘区域还包括第一侧垫；
顶部封装，通过接合部件层叠在所述底部封装上，其中所述顶部封装包括顶部保护部件以及设置在所述顶部保护部件的外部的第二侧垫；
第三封装，通过所述接合部件层叠在所述顶部封装上，其中所述第三封装包括第三保护部件以及设置在所述第三保护部件的外部的第三侧垫；
集成电线，用于使所述底部封装、所述顶部封装与所述第三封装电连接；以及
集成保护部件，用于密封所述集成电线，
其中，所述底部基板的所述第一侧垫、所述顶部封装的所述第二侧垫及所述第三封装的所述第三侧垫排列成上升阶梯状。
7.根据权利要求6所述的半导体堆叠封装，其特征在于，
所述第一侧垫、所述第二侧垫及所述第三侧垫与所述集成电线连接。
8.一种存储器模块，其特征在于，包括：
模块基板；
多个DRAM存储器封装，安装在所述模块基板上；
多个接触端子，以预定间隔排列在所述模块基板的一侧，用于电连接所述DRAM存储器封装，
其中，所述DRAM存储器封装中的每一个包括：
集成基板；
底部封装，层叠在所述集成基板上，
所述底部封装包括：
底部基板，在中心具有窗口；
第一芯片，以面对活性面的方式结合在所述底部基板上，且第一焊垫通过所述窗口向下暴露；
第二芯片，所述第二芯片的非活性面与所述第一芯片的非活性面接合，且第二焊垫形成在所述第二芯片的活性面的一侧；
第一焊线，用于使所述第一焊垫通过所述窗口与所述底部基板的底面引线键合；
第一保护部件，用于覆盖所述第一焊线；
第二焊线，用于使所述第二焊垫与所述底部基板的上面引线键合；以及
第二保护部件，用于覆盖所述第二焊线，其中所述底部基板包括设置在所述第二保护部件的外部的第一侧垫；
顶部封装，通过接合部件层叠在所述底部封装上，其中所述顶部封装包括：
第二基板；
顶部保护部件，其中所述第二基板的边缘没有被所述顶部保护部件覆盖而暴露；以及
第二侧垫，设置在所述顶部保护部件的外部；
第三封装，通过所述接合部件层叠在所述顶部封装上，其中所述第三封装包括：
第三基板；
第三保护部件，其中所述第三基板的边缘没有被所述第三保护部件覆盖而暴露；以及
第三侧垫，设置在所述第三保护部件的外部；
集成电线，使所述底部封装、所述顶部封装与所述第三封装电连接，且使所暴露的所述底部基板的边缘、所述顶部封装的边缘与所述第三封装的边缘电连接；以及
集成保护部件，用于密封所述集成电线，
其中，所述底部基板的所述第一侧垫、所述顶部封装的所述第二侧垫及所述第三封装的所述第三侧垫排列成上升阶梯状。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6939568B2 (ja) * 2016-01-15 2021-09-22 ソニーグループ株式会社 半導体装置および撮像装置
DE102017114771B4 (de) 2017-06-29 2022-01-27 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur Herstellung einer Drahtverbindung sowie Bauelementanordnung mit Drahtverbindung
US10622342B2 (en) * 2017-11-08 2020-04-14 Taiwan Semiconductor Manufacturing Company Ltd. Stacked LED structure and associated manufacturing method
KR102653837B1 (ko) * 2018-07-27 2024-04-02 에스케이하이닉스 주식회사 메모리 모듈 및 데이터 처리 시스템
US10978424B2 (en) * 2018-08-03 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US11139283B2 (en) * 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
US11990449B2 (en) * 2019-01-14 2024-05-21 Intel Corporation Dual RDL stacked die package using vertical wire
KR102613513B1 (ko) 2019-05-17 2023-12-13 삼성전자주식회사 반도체 모듈
KR102699633B1 (ko) 2019-06-25 2024-08-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN111106123A (zh) * 2019-12-19 2020-05-05 江苏中科智芯集成科技有限公司 一种三维堆叠存储芯片结构及其封装方法
KR102599631B1 (ko) * 2020-06-08 2023-11-06 삼성전자주식회사 반도체 칩, 반도체 장치, 및 이를 포함하는 반도체 패키지
DE102020122662A1 (de) 2020-08-31 2022-03-03 Infineon Technologies Ag Biegehalbleiterchip für eine Verbindung bei verschiedenen vertikalen Ebenen
KR102709409B1 (ko) * 2020-10-13 2024-09-24 삼성전자주식회사 반도체 칩, 적층 반도체 칩 구조체, 및 이를 포함하는 반도체 패키지
CN112366140B (zh) * 2020-11-11 2022-09-23 苏州钜升精密模具有限公司 一种用于5g智能设备的多存储芯片堆叠封装构件及其制备方法
CN115188746B (zh) * 2021-04-07 2024-05-24 中国科学院国家空间科学中心 一种用于计算机微系统的电子封装结构
US20230011439A1 (en) * 2021-07-07 2023-01-12 Western Digital Technologies, Inc. Semiconductor Device Package Die Stacking System and Method
CN114975415A (zh) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 扇出堆叠型半导体封装结构及其封装方法
KR20240151061A (ko) * 2023-04-10 2024-10-17 에센코어 리미티드 메모리 장치를 처리하는 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI331392B (en) * 2005-06-20 2010-10-01 Stats Chippac Ltd Module having stacked chip scale semiconductor packages
CN104137260A (zh) * 2012-01-09 2014-11-05 英维萨斯公司 可堆叠微电子封装结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6201439B1 (en) * 1997-09-17 2001-03-13 Matsushita Electric Industrial Co., Ltd. Power splitter/ combiner circuit, high power amplifier and balun circuit
KR100335717B1 (ko) * 2000-02-18 2002-05-08 윤종용 고용량 메모리 카드
US8847413B2 (en) 2007-01-15 2014-09-30 Stats Chippac Ltd. Integrated circuit package system with leads having multiple sides exposed
KR101623880B1 (ko) * 2008-09-24 2016-05-25 삼성전자주식회사 반도체 패키지
UY4342U (es) * 2010-07-05 2010-08-31 Guillermo Victor Pintos Pintos Sistema de generación de voltaje por peso aplicable a vehiculos a motor electrico conformado por sistema mixto: neumático-mecanico
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
KR102324628B1 (ko) * 2015-07-24 2021-11-10 삼성전자주식회사 솔리드 스테이트 드라이브 패키지 및 이를 포함하는 데이터 저장 시스템

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI331392B (en) * 2005-06-20 2010-10-01 Stats Chippac Ltd Module having stacked chip scale semiconductor packages
CN104137260A (zh) * 2012-01-09 2014-11-05 英维萨斯公司 可堆叠微电子封装结构

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