CN108117043B

CN108117043B - Semiconductor device, preparation method and electronic device

Info

Publication number: CN108117043B
Application number: CN201611067307.9A
Authority: CN
Inventors: 黄风建; 毛益平; 刘杰; 吴悠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-28
Filing date: 2016-11-28
Publication date: 2020-06-09
Anticipated expiration: 2036-11-28
Also published as: CN108117043A

Abstract

The invention relates to a semiconductor device, a preparation method and an electronic device. The method comprises the steps of providing a first wafer, and forming a zero-layer mark in the first wafer; forming a passivation layer on the first wafer to cover the zero layer mark; patterning the passivation layer to form an alignment mark in the passivation layer over the zero layer mark; providing a second wafer and combining with the first wafer; patterning the second wafer to form an opening and expose the alignment mark; and forming a functional material layer on the surface of the opening and the surface of the alignment mark. The alignment mark is exposed by the second wafer, and the alignment mark can still be exposed after the functional material layer (such as a contact hole material layer) is formed, and can not be covered, so that the problem of alignment failure can be avoided.

Description

Semiconductor device, preparation method and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method and an electronic device.

Background

With the development of semiconductor technology, MEMS devices fabricated by Micro Electro Mechanical Systems (MEMS) technology have attracted attention. MEMS devices are used as sensors, oscillators, and the like, in which minute MEMS structures are fabricated on a semiconductor substrate. The MEMS is provided with a fixed electrode and a movable electrode, and the characteristics as a MEMS device are obtained by detecting electrostatic capacitance or the like generated in the fixed electrode using the deflection of the movable electrode.

The MEMS devices are of various types, wherein MEMS humidity sensors and pressure sensors have been widely used in the fields of industrial control, automotive electronics, environmental monitoring, biomedicine, etc., and MEMS accelerometers have also been widely used in industrial and consumer electronics.

The MEMS inertial sensor is widely used because of its advantages of small size, low cost, and high reliability, in the fabrication process of the MEMS inertial sensor, a CMOS device is first fabricated, and a zero mark is formed in a first wafer having the CMOS device, and after the first wafer and a second wafer having the MEMS device formed thereon are bonded, the zero mark may be covered by the second wafer, thereby causing the zero mark to fail.

In addition, a contact hole material layer may be deposited during the fabrication of the MEMS device, and the zero mark may be covered and fail after the deposition of the contact hole material layer, so that an etching step is also required to expose the zero mark for use as an alignment mark, which is cumbersome and adds many additional steps.

Therefore, the above drawbacks are a problem to be solved to further improve the performance and yield of the device.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

providing a first wafer, and forming a zero-layer mark in the first wafer;

forming a passivation layer on the first wafer to cover the zero layer mark;

patterning the passivation layer to form an alignment mark in the passivation layer over the zero layer mark;

providing a second wafer and combining with the first wafer;

patterning the second wafer to form an opening and expose the alignment mark;

and forming a functional material layer on the surface of the opening and the surface of the alignment mark.

Optionally, the method for forming the zero layer mark and the alignment mark includes:

providing a first wafer, wherein a plurality of first grooves which are mutually spaced are formed in the first wafer and are used as the zero-layer marks;

depositing the passivation layer to fill the first groove and cover the first wafer;

and patterning the passivation layer to form a plurality of second grooves which are spaced from each other in the passivation layer to be used as the alignment marks.

Optionally, the first wafer and the second wafer are bonded by fusion bonding.

Optionally, the method of forming the functional material layer includes:

depositing the functional material layer to cover the second wafer, the surface of the opening and the surface of the alignment mark;

a planarization step is performed to remove the functional material layer on the second wafer.

Optionally, a CMOS device is formed in the first wafer;

the second wafer has MEMS devices formed therein.

The invention also provides a semiconductor device prepared based on the method, which is characterized by comprising the following components:

a first wafer;

a zero layer mark in the first wafer;

a passivation layer on the first wafer;

an alignment mark in the passivation layer over the zero layer mark;

and the second wafer is integrally bonded with the first wafer through the passivation layer, wherein an opening is formed in the second wafer, and the alignment mark is exposed.

Optionally, the zero-layer mark comprises a plurality of first grooves spaced from each other;

the alignment mark comprises a plurality of second grooves which are spaced from each other.

Optionally, a functional material layer is further formed on the surface of the opening and the surface of the alignment mark.

Optionally, the semiconductor device comprises an inertial sensor.

The invention also provides an electronic device comprising the semiconductor device.

In order to solve the problems in the prior art, the present application provides a method for manufacturing a semiconductor device, in which, in order to avoid covering a zero layer mark in a first wafer, after a passivation layer covering the zero layer mark is formed, an alignment mark is formed in the passivation layer, the alignment mark is exposed by a second wafer, and after a functional material layer (e.g., a contact hole material layer) is formed, the alignment mark can still be exposed and cannot be covered, so that the problem of misalignment can be avoided.

The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 shows a flow chart of a process for fabricating a semiconductor device according to the present invention;

FIGS. 2A to 2F are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In order to solve the above problems in the current process, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a first wafer, and forming a zero-layer mark in the first wafer;

forming a passivation layer on the first wafer to cover the first wafer;

patterning the passivation layer to form an alignment mark in the passivation layer above the zero layer mark;

providing a second wafer and combining with the first wafer;

patterning the second wafer to form an opening to expose the alignment mark;

The method for forming the zero layer mark and the alignment mark comprises the following steps:

Example one

A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings, and fig. 1 shows a flow chart of a manufacturing process of the semiconductor device according to the present invention; FIGS. 2A to 2F are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.

The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:

step S1: providing a first wafer, and forming a zero-layer mark in the first wafer;

step S2: forming a passivation layer on the first wafer to cover the zero layer mark;

step S3: patterning the passivation layer to form an alignment mark in the passivation layer over the zero layer mark;

step S4: providing a second wafer and combining with the first wafer;

step S5: patterning the second wafer to form an opening and expose the alignment mark;

step S6: and forming a functional material layer on the surface of the opening and the surface of the alignment mark.

Next, a detailed description will be given of a specific embodiment of the method for manufacturing a semiconductor device of the present invention.

First, step one is executed to provide a first wafer 201, in which a zero layer mark 10 is formed.

Specifically, as shown in fig. 2A, the first wafer 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.

In this embodiment, CMOS devices are formed in the first wafer, for example, conventional devices such as active devices and interconnection structures are formed in the first wafer, or CMOS image sensors and the like may also be formed.

A zero layer mark 10 is formed in the first wafer for alignment of various patterns, e.g. for lithography, etching, etc. of various patterns.

Secondly, a plurality of first grooves which are mutually spaced are formed in the first wafer and are used as the zero-layer marks.

Specifically, the method for forming the first recess includes first forming a patterned photoresist layer or Organic Distribution Layer (ODL), a silicon-containing bottom anti-reflective coating (Si-BARC), and a top patterned photoresist layer (not shown) on the first wafer, wherein the pattern on the photoresist defines the pattern of the first recess, then etching the Organic distribution layer or bottom anti-reflective coating to form the pattern of the first recess, and then etching the first wafer to form the first recess, using the Organic distribution layer or bottom anti-reflective coating as a mask.

Specifically, dry etching or wet etching is selected in the step, and a C-F etchant is preferably used for etching the first wafer in the invention, wherein the C-F etchant is CF₄、CHF₃、C₄F₈And C₅F₈One or more of (a). In this embodiment, the dry etching may be CF₄、CHF₃In addition, N is added₂、CO₂As an etching atmosphere, wherein the gas flow rate is CF₄10-200sccm，CHF₃10-200sccm，N₂Or CO₂Or O₂10-400sccm, the etching pressure is 30-150mTorr, and the etching time is 5-120s, preferably 5-60s, more preferably 5-30 s.

The first grooves are arranged at intervals, and the specific number and the interval distance are not limited to a certain numerical range.

And step two, forming a passivation layer on the first wafer to cover the first wafer.

Specifically, as shown in fig. 2A, a passivation layer 202 is deposited to fill the first recess in the first wafer and cover the first wafer.

The passivation layer 202 may be a silicon dioxide layer, a silicon nitride layer, or the like, as long as the passivation film has a compact and stable structure, is not easily damaged, and can block the attack of various ions and water molecules, and is not limited to the above examples.

The deposition method of the passivation layer 202 may be one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. Chemical Vapor Deposition (CVD) is preferred in the present invention.

And step three, patterning the passivation layer to form an alignment mark 20 above the zero layer mark in the passivation layer.

Specifically, as shown in fig. 2B, the passivation layer is patterned in this step to form an alignment mark 20 in a region of the passivation layer corresponding to the zero layer mark 10.

For example, a plurality of second grooves spaced apart from each other are formed in the second wafer as the alignment marks 20.

Specifically, the method for forming the second recess includes first forming a patterned photoresist layer or Organic Distribution Layer (ODL), a silicon-containing bottom anti-reflective coating (Si-BARC), and a top patterned photoresist layer (not shown) on the second wafer, wherein the pattern on the photoresist defines the pattern of the second recess, then etching the Organic distribution layer or the bottom anti-reflective coating to form the pattern of the second recess, and then etching the second wafer to form the second recess by using the Organic distribution layer or the bottom anti-reflective coating as a mask.

The size and the number of the second grooves can be the same as those of the first grooves, and can be different from those of the first grooves, and the sizes and the numbers of the second grooves are selected and arranged according to actual needs.

Step four is executed, a second wafer 203 is provided and is bonded with the first wafer.

Specifically, as shown in fig. 2C, a MEMS device, such as a sensor mass forming an inertial sensor, is formed in the second wafer.

Wherein the second wafer may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.

The bonding method of the first wafer and the second wafer can be thermocompression bonding or Van der Waals eutectic bonding.

In this embodiment, the first wafer and the second wafer are bonded by fusion bonding.

Optionally, the second wafer may be pre-cleaned to improve the bonding performance of the second wafer.

Specifically, diluted hydrofluoric acid DHF (containing HF and H) is used in the step₂O₂And H₂O) pre-cleaning the surface of the second wafer to ensure that the second wafer has good performance (lead good mechanism).

The concentration of DHF is not critical, but preferred is HF: H in the present invention₂O₂:H₂O＝0.1-1.5:1:5。

And step five, patterning the second wafer to form an opening to expose the alignment mark.

Specifically, as shown in fig. 2D, the second wafer is patterned in this step to expose the alignment marks.

Optionally, a photoresist layer is formed on the second wafer, and then exposed and developed to form an opening to expose the second wafer.

And etching the second wafer by using the photoresist as a mask so as to transfer the opening into the second wafer.

Wherein the opening completely exposes the alignment mark.

And step six is executed, and a functional material layer is formed on the surface of the opening and the surface of the alignment mark.

Specifically, the functional material layer includes a contact hole material layer, such as various conductive materials and the like.

Optionally, the method for forming the functional material layer on the surface of the opening and the surface of the alignment mark includes:

depositing a functional material layer to cover the second wafer, the surface of the opening and the surface of the alignment mark, as shown in fig. 2E;

a planarization step is performed to remove the functional material layer on the second wafer, as shown in fig. 2F.

Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.

In order to solve the problems in the prior art, the present application provides a method for manufacturing a semiconductor device, in which, in order to avoid covering a zero layer mark in a first wafer, after a passivation layer covering the zero layer mark is formed, an alignment mark is formed in the passivation layer, the alignment mark is exposed by a second wafer, and after a functional material layer, such as a contact hole material layer, is formed, the alignment mark can still be exposed and not covered, so that the problem of misalignment can be avoided.

Example two

The invention also provides a semiconductor device prepared by the method in the first embodiment.

The semiconductor device includes:

a first wafer;

a zero layer mark in the first wafer;

a passivation layer on the first wafer and filling the zero layer mark;

an alignment mark in the passivation layer and over the zero layer mark;

and the second wafer is integrally bonded with the first wafer through the passivation layer.

And an opening is formed in the second wafer, and the alignment mark is exposed.

And a functional material layer is further formed on the surface of the opening and the surface of the alignment mark.

Wherein the semiconductor device includes an inertial sensor.

The first wafer 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.

And forming a passivation layer on the first wafer to cover the first wafer.

An alignment mark 20 is formed in the passivation layer above the zero layer mark.

The second wafer 203 is bonded to the first wafer.

Wherein MEMS devices, such as proof masses forming inertial sensors, are formed in the second wafer.

An opening is formed in the second wafer to expose the alignment mark.

Wherein the opening completely exposes the alignment mark.

In order to solve the problems in the prior art, in a manufacturing method of a semiconductor device, in order to avoid covering a zero layer mark in a first wafer, after a passivation layer covering the zero layer mark is formed, an alignment mark is formed in the passivation layer, the alignment mark is exposed by a second wafer, and after a functional material layer, such as a contact hole material layer, is formed, the alignment mark can still be exposed and cannot be covered, so that the problem of alignment failure can be avoided.

EXAMPLE III

Another embodiment of the present invention provides an electronic device, which includes a semiconductor device, wherein the semiconductor device is the semiconductor device in the second embodiment or the semiconductor device manufactured by the method of manufacturing the semiconductor device in the first embodiment.

The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.

The electronic device also has the above-described advantages because the semiconductor device included has higher performance.

Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.

Wherein the mobile phone handset comprises the semiconductor device or the semiconductor device manufactured by the manufacturing method of the semiconductor device according to the first embodiment, the semiconductor device comprises: a first wafer; a zero layer mark in the first wafer; a passivation layer on the first wafer and filling the zero layer mark; an alignment mark in the passivation layer and over the zero layer mark; and the second wafer is integrally bonded with the first wafer through the passivation layer. In order to avoid covering the zero layer mark in the first wafer in the preparation method of the semiconductor device, after a passivation layer covering the zero layer mark is formed, an alignment mark is formed in the passivation layer, the alignment mark is exposed by the second wafer, and the alignment mark can still be exposed and not covered after a functional material layer, such as a contact hole material layer, is formed, so that the problem of alignment failure can be avoided.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a first wafer, and forming a zero-layer mark in the first wafer;

forming a passivation layer on the first wafer to cover the zero layer mark;

providing a second wafer and combining with the first wafer;

patterning the second wafer to form an opening and expose the alignment mark;

2. The method of claim 1, wherein the method of forming the zero layer mark and the alignment mark comprises:

3. The method of claim 1, wherein the first wafer and the second wafer are bonded by fusion bonding.

4. The method of claim 1, wherein forming the functional material layer comprises:

5. The method of claim 1, wherein the first wafer has CMOS devices formed therein;

the second wafer has MEMS devices formed therein.

6. A semiconductor device prepared based on the method of any one of claims 1 to 5, wherein the semiconductor device comprises:

a first wafer;

a zero layer mark in the first wafer;

a passivation layer on the first wafer;

an alignment mark in the passivation layer over the zero layer mark;

the second wafer is integrally bonded with the first wafer through the passivation layer, wherein an opening is formed in the second wafer and the alignment mark is exposed;

and a functional material layer is also formed on the surface of the opening and the surface of the alignment mark.

7. The semiconductor device of claim 6, wherein the zero-level mark comprises a plurality of first grooves spaced apart from each other;

8. The semiconductor device according to claim 6, wherein the semiconductor device comprises an inertial sensor.

9. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 6 to 8.