CN108117043A - A kind of semiconductor devices and preparation method, electronic device - Google Patents
A kind of semiconductor devices and preparation method, electronic device Download PDFInfo
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- CN108117043A CN108117043A CN201611067307.9A CN201611067307A CN108117043A CN 108117043 A CN108117043 A CN 108117043A CN 201611067307 A CN201611067307 A CN 201611067307A CN 108117043 A CN108117043 A CN 108117043A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/002—Aligning microparts
- B81C3/005—Passive alignment, i.e. without a detection of the position of the elements or using only structural arrangements or thermodynamic forces
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method, electronic devices.The described method includes the first wafer is provided, zero layer mark is formed in first wafer；Passivation layer is formed on first wafer, is marked with covering the zero layer；The passivation layer is patterned, to form alignment mark in the passivation layer above zero layer mark；Second wafer is provided and is engaged with first wafer；Second wafer is patterned, to form opening and expose the alignment mark；Function material layer is formed on the surface of the opening and the surface of the alignment mark.Heretofore described alignment mark is exposed by the second wafer, and still can expose the alignment mark after function material layer (such as contact hole material layer) is formed, and will not be capped, thus can be to avoid that can not be aligned the problem of.
Description
Technical field
The present invention relates to technical field of semiconductors, are filled in particular to a kind of semiconductor devices and preparation method, electronics
It puts.
Background technology
With the continuous development of semiconductor technology, microelectromechanical systems (Micro Electro Mechanical are used
System, MEMS) MEMS device that forms of fabrication techniques is very noticeable.MEMS device be make on a semiconductor substrate it is micro-
Small MEMS structure body, to be used as the purposes such as sensor, oscillator.Fixed electrode and movable electricity are equipped on the MEMS structure body
Pole results from electrostatic capacitance etc. of fixed electrode, to obtain as MEMS device by using the flexure of movable electrode to detect
Characteristic.
The MEMS device species is various, wherein, MEMS humidity sensors and pressure sensor Industry Control,
The fields such as automotive electronics, environmental monitoring, biomedicine are widely used, and mems accelerometer is in industry, consumer electronics
In application also very extensively.
MEMS inertial sensor has many advantages, such as that size is small, at low cost and higher reliability is obtained extensively due to it
Using, prepare cmos device first in the preparation process of MEMS inertial sensor, and it is brilliant first with cmos device
Zero flag is formed in circle, after first wafer is engaged with the second wafer for being formed with MEMS device, the zero standard
Note can be covered by second wafer, be failed so as to cause zero flag.
In addition, in MEMS device preparation process may Deposit contact Porous materials layer, Deposit contact Porous materials layer it
The zero flag can equally be capped and fail afterwards, therefore also need to perform etching step to expose the zero flag, for use as
The mark of alignment, the process is cumbersome, adds many additional steps.
Therefore above-mentioned drawback becomes the problem of urgent need to resolve, to further improve the performance of device and yield.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of preparation method of semiconductor devices, the methods
Including：
First wafer is provided, zero layer mark is formed in first wafer；
Passivation layer is formed on first wafer, is marked with covering the zero layer；
The passivation layer is patterned, to form alignment mark in the passivation layer above zero layer mark；
Second wafer is provided and is engaged with first wafer；
Second wafer is patterned, to form opening and expose the alignment mark；
Function material layer is formed on the surface of the opening and the surface of the alignment mark.
Optionally, forming the method for the zero layer mark and the alignment mark includes：
First wafer is provided, several the first spaced grooves are formed in first wafer, using as described
Zero layer marks；
The passivation layer is deposited, to fill first groove and cover first wafer；
The passivation layer is patterned, to form several the second spaced grooves in the passivation layer, using as institute
State alignment mark.
Optionally, first wafer and second wafer are engaged by melting the method for bonding.
Optionally, forming the method for the function material layer includes：
The function material layer is deposited, to cover the surface of second wafer, the opening and the alignment mark
Surface；
Planarisation step is performed, to remove the function material layer on second wafer.
Optionally, it is formed with cmos device in first wafer；
MEMS device is formed in second wafer.
The present invention also provides a kind of semiconductor devices being prepared based on the above method, which is characterized in that described half
Conductor device includes：
First wafer；
Zero layer marks, in first wafer；
Passivation layer, on first wafer；
Alignment mark, in the passivation layer of zero layer mark top；
Second wafer, second wafer are combined into one by the passivation layer and first wafer, wherein, it is described
Opening is formed in second wafer and exposes the alignment mark.
Optionally, the zero layer mark includes several the first spaced grooves；
The alignment mark includes several the second spaced grooves.
Optionally, it is also formed with function material layer on the surface on the surface of the opening and the alignment mark.
Optionally, the semiconductor devices includes inertial sensor.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the application, provides a kind of preparation method of semiconductor devices,
In order to avoid the zero layer in first wafer is marked covering in the method, the passivation of the covering zero layer mark is being formed
After layer, alignment mark is formed in the passivation layer, the alignment mark is exposed by the second wafer, and is forming function material
The alignment mark still can be exposed after the bed of material (such as contact hole material layer), will not be capped, therefore can be to avoid nothing
The problem of method is aligned.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2A -2F show that the preparation method implementation of semiconductor devices described in one embodiment of the invention obtains cuing open for structure
Face schematic diagram；
Fig. 3 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device overturning in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation sides of semiconductor devices
Method, the described method includes：
First wafer is provided, zero layer mark is formed in first wafer；
Passivation layer is formed on first wafer, to cover first wafer；
The passivation layer is patterned, the top marked with the zero layer described in the passivation layer forms alignment mark；
Second wafer is provided and is engaged with first wafer；
Second wafer is patterned, to form opening, exposes the alignment mark；
Function material layer is formed on the surface of the opening and the surface of the alignment mark.
Wherein, forming the method for the zero layer mark and the alignment mark includes：
First wafer is provided, several the first spaced grooves are formed in first wafer, using as described
Zero layer marks；
The passivation layer is deposited, to fill first groove and cover first wafer；
The passivation layer is patterned, to form several the second spaced grooves in the passivation layer, using as institute
State alignment mark.
In order to solve the problems in the existing technology the application, provides a kind of preparation method of semiconductor devices,
In order to avoid the zero layer in first wafer is marked covering in the method, the passivation of the covering zero layer mark is being formed
After layer, alignment mark is formed in the passivation layer, the alignment mark is exposed by the second wafer, and is forming function material
The alignment mark still can be exposed after the bed of material (such as contact hole material layer), will not be capped, therefore can be to avoid nothing
The problem of method is aligned.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2A -2F show the system of semiconductor devices described in one embodiment of the invention
Preparation Method is implemented to obtain the diagrammatic cross-section of structure；Fig. 3 shows showing for electronic device according to an embodiment of the present invention
It is intended to.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step bag of the preparation method
It includes：
Step S1：First wafer is provided, zero layer mark is formed in first wafer；
Step S2：Passivation layer is formed on first wafer, is marked with covering the zero layer；
Step S3：The passivation layer is patterned, to be formed in the passivation layer above zero layer mark to fiducial mark
Note；
Step S4：Second wafer is provided and is engaged with first wafer；
Step S5：Second wafer is patterned, to form opening and expose the alignment mark；
Step S6：Function material layer is formed on the surface of the opening and the surface of the alignment mark.
In the following, the specific embodiment of the preparation method of the semiconductor devices of the present invention is described in detail.
First, step 1 is performed, the first wafer 201 is provided, zero layer mark 10 is formed in first wafer.
Specifically, as shown in Figure 2 A, first wafer 201 can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI) are stacked silicon (SSOI) on insulator, are stacked SiGe (S-SiGeOI) and insulation on insulator
SiGe (SiGeOI) etc. on body.
Cmos device is formed in first wafer in this embodiment, such as is formed in first wafer
The device of the routine such as active device and interconnection architecture can also be formed with cmos image sensor etc..
Zero layer mark 10 is formed in first wafer, for the alignment of various patterns, such as various patterns
Photoetching, etching etc..
Secondly, several the first spaced grooves are formed in first wafer, to be marked as the zero layer.
Specifically, forming the method for first groove includes forming patterned photoetching on first wafer first
Glue-line or organic distribution layer (Organic distribution layer, ODL), siliceous bottom antireflective coating (Si-
BARC the photoresist layer (not shown) of the patterning) and positioned at top, wherein the pattern definition on the photoresist
Then the pattern of first groove etches organic distribution layer, bottom anti-reflective by mask layer of the photoresist layer
Coating forms the pattern of the first groove, then using organic distribution layer, bottom antireflective coating as mask, etching described first
Wafer, to form first groove.
Specifically, dry etching or wet etching are selected in this step, preferred C-F etchants lose in the present invention
First wafer is carved, the C-F etchants are CF4、CHF3、C4F8And C5F8In one or more.In this embodiment,
The dry etching can select CF4、CHF3, in addition plus N2、CO2In it is a kind of as etching atmosphere, wherein gas flow is
CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr,
Etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
Wherein, the distance at the spaced setting of the first groove, specific number and interval is not limited to a certain
Numberical range.
Step 2 is performed, passivation layer is formed on first wafer, to cover first wafer.
Specifically, as shown in Figure 2 A, deposit passivation layer 202, to fill first groove in first wafer simultaneously
Cover first wafer.
Wherein, the passivation layer 202 can be silica or silicon nitride layer etc., as long as the passivation film structure causes
Erosion that is close, stable, being not easily susceptible to destruction, can stop various ions and hydrone, it is not limited to above-mentioned example.
The deposition method of the passivation layer 202 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method or atomic layer deposition (ALD) method
Select one kind in epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Step 3 is performed, patterns the passivation layer, the top formation pair marked with the zero layer described in the passivation layer
Fiducial mark note 20.
Specifically, as shown in Figure 2 B, the passivation layer is patterned in this step, in the passivation layer with
Alignment mark 20 is formed in the 10 corresponding region of zero layer mark.
Such as several the second spaced grooves are formed in second wafer, using as the alignment mark 20.
Specifically, forming the method for second groove includes forming patterned photoetching on second wafer first
Glue-line or organic distribution layer (Organic distribution layer, ODL), siliceous bottom antireflective coating (Si-
BARC the photoresist layer (not shown) of the patterning) and positioned at top, wherein the pattern definition on the photoresist
Then the pattern of second groove etches organic distribution layer, bottom anti-reflective by mask layer of the photoresist layer
Coating forms the pattern of the second groove, then using organic distribution layer, bottom antireflective coating as mask, etching described second
Wafer, to form second groove.
Wherein, the size and number of second groove can be identical with first groove, naturally it is also possible to different, root
It makes choice and sets according to actual needs.
Step 4 is performed, the second wafer 203 is provided and is engaged with first wafer.
Specifically, as shown in Figure 2 C, wherein, MEMS device is formed in second wafer, such as forms inertia and pass
Sensing quality block of sensor etc..
Wherein, second wafer can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) is stacked on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx are stacked on insulator
(SiGeOI) etc..
Wherein, the joint method of first wafer and second wafer can be that thermocompression bonding or Van der Waals force are total to
Crystalline substance bonding is integrated.
It selects and is engaged first wafer and second wafer in this embodiment by melting the method for bonding.
Optionally, prerinse can also be carried out to second wafer, to improve the Joint Properties of second wafer.
Specifically, in this step with diluted hydrofluoric acid DHF (wherein comprising HF, H2O2And H2O it is) brilliant to described second
Round surface carries out prerinse, so that second wafer has good performance (lead good mechanism).
Wherein, the concentration of the DHF does not limit strictly, in the present invention preferred HF:H2O2:H2O=0.1-1.5:1:5.
Step 5 is performed, patterns second wafer, to form opening, exposes the alignment mark.
Specifically, as shown in Figure 2 D, second wafer is patterned in this step, to expose the alignment mark.
Optionally, photoresist layer is formed on second wafer, then exposure imaging, opening is formed, with described in exposing
Second wafer.
Using the photoresist as the second wafer described in mask etch, the opening is transferred in second wafer.
Wherein, the opening is completely exposed the alignment mark.
Step 6 is performed, function material layer is formed on the surface of the opening and the surface of the alignment mark.
Specifically, the function material layer includes contact hole material layer, such as various conductive materials etc..
Optionally, the method bag of function material layer is formed on the surface of the opening and the surface of the alignment mark
It includes：
Function material layer is deposited, to cover second wafer, the surface of the opening and the surface of alignment mark, is such as schemed
Shown in 2E；
Planarisation step is performed, to remove the function material layer on second wafer, as shown in Figure 2 F.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, other correlation steps can also be included, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the problems in the existing technology the application, provides a kind of preparation method of semiconductor devices,
In order to avoid the zero layer in first wafer is marked covering in the method, the passivation of the covering zero layer mark is being formed
After layer, alignment mark is formed in the passivation layer, the alignment mark is exposed by the second wafer, and is forming function material
The alignment mark still can be exposed after the bed of material, such as contact hole material layer, will not be capped, therefore can be to avoid can not
The problem of alignment.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices is prepared by method described in embodiment one
It obtains.
The semiconductor devices includes：
First wafer；
Zero layer marks, in first wafer；
Passivation layer on first wafer and fills zero layer mark；
Alignment mark, in the passivation layer and positioned at zero layer mark top；
Second wafer, second wafer are combined into one by the passivation layer and first wafer.
Wherein, it is formed with opening in second wafer and exposes the alignment mark.
Wherein, it is also formed with function material layer on the surface on the surface of the opening and the alignment mark.
Wherein, the semiconductor devices includes inertial sensor.
First wafer 201 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Silicon (SSOI) is stacked on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) are stacked on insulator
Deng.
Cmos device is formed in first wafer in this embodiment, such as is formed in first wafer
The device of the routine such as active device and interconnection architecture can also be formed with cmos image sensor etc..
Zero layer mark 10 is formed in first wafer, for the alignment of various patterns, such as various patterns
Photoetching, etching etc..
Secondly, several the first spaced grooves are formed in first wafer, to be marked as the zero layer.
Wherein, the distance at the spaced setting of the first groove, specific number and interval is not limited to a certain
Numberical range.
Passivation layer is formed on first wafer, to cover first wafer.
Wherein, the passivation layer 202 can be silica or silicon nitride layer etc., as long as the passivation film structure causes
Erosion that is close, stable, being not easily susceptible to destruction, can stop various ions and hydrone, it is not limited to above-mentioned example.
The deposition method of the passivation layer 202 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method or atomic layer deposition (ALD) method
Select one kind in epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
The top that the zero layer described in the passivation layer marks is formed with alignment mark 20.
Such as several the second spaced grooves are formed in second wafer, using as the alignment mark
20。
Wherein, the size and number of second groove can be identical with first groove, naturally it is also possible to different, root
It makes choice and sets according to actual needs.
Second wafer 203 is engaged with first wafer.
Wherein, MEMS device is formed in second wafer, such as form the sensing quality block of inertial sensor etc..
Wherein, second wafer can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) is stacked on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx are stacked on insulator
(SiGeOI) etc..
Wherein, the joint method of first wafer and second wafer can be that thermocompression bonding or Van der Waals force are total to
Crystalline substance bonding is integrated.
It selects and is engaged first wafer and second wafer in this embodiment by melting the method for bonding.
Opening is formed in second wafer, exposes the alignment mark.
Wherein, the opening is completely exposed the alignment mark.
Function material layer is formed on the surface on the surface of the opening and the alignment mark.
Specifically, the function material layer includes contact hole material layer, such as various conductive materials etc..
In order to solve the problems in the existing technology the application, provides a kind of semiconductor devices, in the semiconductor
In order to avoid the zero layer in first wafer is marked covering in the preparation method of device, the zero layer mark is covered being formed
Passivation layer after, alignment mark is formed in the passivation layer, the alignment mark is exposed by the second wafer, and is being formed
The alignment mark still can be exposed after function material layer, such as contact hole material layer, will not be capped, therefore can keep away
The problem of exempting from not being aligned.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic device, and including semiconductor devices, which is
Half obtained by the preparation method of semiconductor devices in previous embodiment two or the semiconductor devices according to embodiment one
Conductor device.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
Since the semiconductor devices part included has higher performance, which equally has the advantages that above-mentioned.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices or the semiconductor device according to embodiment one
Semiconductor devices obtained by the preparation method of part, the semiconductor devices include：First wafer；Zero layer marks, positioned at described
In first wafer；Passivation layer on first wafer and fills zero layer mark；Alignment mark, positioned at the passivation
In layer and positioned at zero layer mark top；Second wafer, second wafer are brilliant with described first by the passivation layer
Circle is combined into one.It is covered in the preparation method of the semiconductor devices in order to avoid the zero layer in first wafer is marked
Lid after the passivation layer for covering the zero layer mark is formed, forms alignment mark, the alignment mark in the passivation layer
It is exposed by the second wafer, and the alignment still can be exposed after function material layer, such as contact hole material layer is formed
Mark, will not be capped, therefore can be to avoid that can not be aligned the problem of.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, which is characterized in that the described method includes：
First wafer is provided, zero layer mark is formed in first wafer；
Passivation layer is formed on first wafer, is marked with covering the zero layer；
The passivation layer is patterned, to form alignment mark in the passivation layer above zero layer mark；
Second wafer is provided and is engaged with first wafer；
Second wafer is patterned, to form opening and expose the alignment mark；
Function material layer is formed on the surface of the opening and the surface of the alignment mark.
2. according to the method described in claim 1, it is characterized in that, form the side of the zero layer mark and the alignment mark
Method includes：
First wafer is provided, several the first spaced grooves are formed in first wafer, using as the zero layer
Mark；
The passivation layer is deposited, to fill first groove and cover first wafer；
The passivation layer is patterned, to form several the second spaced grooves in the passivation layer, using as described right
Fiducial mark is remembered.
3. according to the method described in claim 1, it is characterized in that, by melting the method being bonded by first wafer and institute
The second wafer is stated to engage.
4. according to the method described in claim 1, it is characterized in that, forming the method for the function material layer includes：
The function material layer is deposited, to cover the surface on the surface of second wafer, the opening and the alignment mark；
Planarisation step is performed, to remove the function material layer on second wafer.
5. according to the method described in claim 1, it is characterized in that, it is formed with cmos device in first wafer；
MEMS device is formed in second wafer.
6. a kind of semiconductor devices being prepared based on one of claim 1 to 5 the method, which is characterized in that described half
Conductor device includes：
First wafer；
Zero layer marks, in first wafer；
Passivation layer, on first wafer；
Alignment mark, in the passivation layer of zero layer mark top；
Second wafer, second wafer are combined into one by the passivation layer and first wafer, wherein, described second
Opening is formed in wafer and exposes the alignment mark.
7. semiconductor devices according to claim 6, which is characterized in that the zero layer mark includes several spaced
First groove；
The alignment mark includes several the second spaced grooves.
8. semiconductor devices according to claim 6, which is characterized in that on the surface of the opening and the alignment mark
Surface be also formed with function material layer.
9. semiconductor devices according to claim 6, which is characterized in that the semiconductor devices includes inertial sensor.
10. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor device described in one of claim 6 to 9
Part.
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