CN108109990B - Through silicon via adapter plate for system-in-package - Google Patents
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention relates to a Through Silicon Via (TSV) adapter plate for system-in-package (SIP), comprising: a Si substrate (101); a plurality of lateral diodes (102) disposed within the Si substrate (101); isolation regions (103) disposed at both sides of each of the lateral diodes (102) to form a device region between adjacent two isolation regions; TSV regions (104) disposed at both sides of a region formed by the device region and the isolation region; an interconnect line (105) connecting in series a first end face of the TSV region (104) and the lateral diode (102); wherein the isolation region (103) and the TSV region (104) both penetrate the Si substrate (101) up and down. According to the through silicon via adapter plate provided by the invention, the diode is processed on the through silicon via adapter plate to serve as an ESD protection device, so that the problem that the integrated circuit system-in-package antistatic capability based on the TSV process is weak is solved, and the antistatic capability of the integrated circuit system-in-package is enhanced.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a through silicon via adapter plate for system-in-package.
Background
Moore's law is increasingly difficult to follow as the feature size of semiconductor devices continues to shrink. In particular, in recent years, with the advance of moore's law, system-in-package has become one of the mainstream directions for future development of the semiconductor industry. A system-in-package based on a Through-Silicon Via (TSV) technology has the advantages of high integration density, low signal delay, low power consumption, and the like, and thus becomes a hot spot for research in academia and industry. At present, it is recognized in the industry that the difficulty of 3D technology for three-dimensionally stacking and wiring semiconductor devices is serious, and 2.5D packaging technology for introducing an interposer between a semiconductor device and a packaging substrate is one of important technologies that can make chips continue to develop forward along the blueprint of moore's law.
On the other hand, in the semiconductor industry, with the increase of the integration level of integrated circuits and the reduction of the feature size of devices, the potential damage caused by electrostatic Discharge (ESD) in the integrated circuits has become more and more obvious. It is reported that nearly 35% of failures in the integrated circuit field are caused by ESD, so the ESD protection structure is designed inside the chip to improve the reliability of the device.
An interposer generally refers to the functional layer of interconnection and pin redistribution between a chip and a package substrate. The adapter plate can redistribute dense I/O leads, high-density interconnection of multiple chips is achieved, and the adapter plate becomes one of the most effective means for electrical signal connection between a nanoscale integrated circuit and a millimeter-scale macroscopic world. When the adapter plate is used for realizing integration of multifunctional chips, the antistatic capacity of different chips is different, and the antistatic capacity of the packaged whole system can be influenced by the chips with weak antistatic capacity when the chips are stacked in three dimensions, so that how to improve the antistatic capacity of the system-in-package based on the TSV process becomes a problem to be solved urgently in the semiconductor industry.
Disclosure of Invention
In order to improve the antistatic capability of the system-in-package of the TSV process, the invention provides a through silicon via adapter plate for the system-in-package; the technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a Through Silicon Via (TSV) adapter plate for system-in-package (SIP), which comprises:
a Si substrate 101;
a plurality of lateral diodes 102 disposed within the Si substrate 101;
TSV regions 104 disposed at both sides of the device region and isolation region forming region;
an interconnection line 105 connecting the first end surface of the TSV region 104 and the lateral diode 102 in series;
the isolation region 103 and the TSV region 104 both penetrate the Si substrate 101 from top to bottom.
In one embodiment of the present invention, a tungsten plug 106 is disposed between the lateral diode 102 and the interconnect line 105.
In one embodiment of the present invention, the material in the isolation region 103 is SiO2Or undoped polysilicon.
In one embodiment of the present invention, the fill material within the TSV region 104 is copper.
In one embodiment of the present invention, a metal bump 107 is disposed on the second end surface of the TSV region 104.
In one embodiment of the present invention, the material of the metal bump 107 is copper.
In one embodiment of the present invention, the depth of the isolation region 103 and the TSV region 104 is 40-80 μm.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the through silicon via adapter plate provided by the invention, the ESD protection device diode is arranged on the through silicon via adapter plate, so that the antistatic capability of the stacked packaged chip is enhanced;
2. according to the invention, the diode is arranged on the through silicon via adapter plate, and the high heat dissipation capacity of the adapter plate is utilized, so that the high-current passing capacity of the device in the working process is improved;
3. the periphery of the diode of the through silicon via adapter plate provided by the invention utilizes the vertically through isolation region, so that the through silicon via adapter plate has smaller leakage current and parasitic capacitance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a through-silicon via interposer for system-in-package according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a through silicon via interposer for system in package according to an embodiment of the present invention;
fig. 3a to fig. 3h are flow charts of another method for manufacturing a through silicon via interposer for system-in-package according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a through silicon via interposer for system in package according to an embodiment of the present invention, including:
a Si substrate 101;
a plurality of lateral diodes 102 disposed within the Si substrate 101;
TSV regions 104 disposed at both sides of the device region and isolation region forming region;
an interconnection line 105 connecting the first end surface of the TSV region 104 and the lateral diode 102 in series;
the isolation region 103 and the TSV region 104 both penetrate the Si substrate 101 from top to bottom.
Specifically, a tungsten plug 106 is provided between the lateral diode 102 and the interconnect line 105.
Further, the material in the isolation region 103 is SiO2Or undoped polysilicon.
Preferably, the fill material within the TSV region 104 is copper.
Preferably, a metal bump 107 is disposed on the second end surface of the TSV region 104.
Preferably, the material of the metal bump 107 is copper.
Preferably, the depth of the isolation region 103 and the TSV region 104 is 40-80 μm.
Preferably, SiO is further included on the upper and lower surfaces of the Si substrate 1012An insulating layer.
According to the through silicon via adapter plate provided by the embodiment, the ESD protection device diode is arranged on the through silicon via adapter plate, so that the antistatic capability of the stacked packaged chip is enhanced; meanwhile, the through silicon via adapter plate provided by the embodiment is provided with the vertically-through isolation region around the diode, so that the through silicon via adapter plate has smaller leakage current and parasitic capacitance.
Example two
Referring to fig. 2 and fig. 2 are flowcharts illustrating a method for manufacturing a through silicon via interposer for system-in-package according to an embodiment of the present invention, and the embodiment of the present invention describes the method for manufacturing the through silicon via interposer in detail below based on the above embodiment. Specifically, the method comprises the following steps:
s101, selecting a substrate material;
s102, preparing a plurality of ESD protective devices on a substrate material;
s103, etching the substrate material to form isolation grooves on two sides of the ESD protection device;
s104, etching the substrate material to form TSV outside the isolation trench;
s105, filling the isolation groove and the TSV respectively to form an isolation region and a TSV region;
s106, preparing an interconnection line between the first end face of the TSV region and the ESD protection device on the upper surface of the substrate material;
and S107, preparing a metal bump on the second end face of the TSV region to complete the preparation of the through silicon via adapter plate.
Preferably, the substrate material is Si material, the crystal orientation is (100), (110) or (111), and the doping concentration is 1014～1017cm-3The thickness is 150 to 250 μm.
Preferably, the ESD protection device is a lateral structure diode.
Further, S102 may include:
s1021, flattening the upper surface of the substrate material by utilizing a Chemical Mechanical Polishing (CMP) process;
s1022, forming P by utilizing photoetching process+Active region pattern, P is performed by ion implantation with glue+Injecting and removing the photoresist to form the anode of the diode with the transverse structure;
s1023, forming N by utilizing photoetching process+Active region patterning by ion implantation with glue+Injecting and removing the photoresist to form a cathode of the diode with the transverse structure;
and S1024, performing high-temperature annealing to activate the impurities.
Preferably, S105 may include:
s1051, thermally oxidizing the TSV and the isolation trench to form an oxide layer on the inner walls of the TSV and the isolation trench;
s1052, etching the oxide layer by using a wet etching process to finish the planarization of the TSV and the inner wall of the isolation groove;
s1053, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1054, using chemical gas phaseA Deposition (Chemical Vapor Deposition, abbreviated as CVD) process, filling SiO in the isolation trench2Forming an isolation region;
s1055, forming a TSV filling pattern by utilizing a photoetching process;
s1056, manufacturing an adhesion layer and a seed layer by using a physical vapor deposition method;
and S1057, filling the TSV by an electrochemical deposition method to form a TSV region.
Preferably, S106 may include:
s1061, forming a liner layer and a barrier layer on the upper surface of the Si substrate by using a sputtering or CVD (chemical vapor deposition) process, and forming a tungsten plug on the anode and the cathode of the diode with the transverse structure by using the CVD process;
s1062, depositing an insulating layer, photoetching an interconnection pattern, depositing a copper material by using an electrochemical copper plating process, removing redundant copper material by using a chemical mechanical polishing process, and forming a copper interconnection line formed by connecting the first end of the TSV region and the diode with the transverse structure in series.
Specifically, S107 is preceded by:
x1, using the auxiliary wafer as a support of the upper surface of the Si substrate;
and x2, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process, and flattening the lower surface of the Si substrate by using a CMP process until the second end face of the TSV region is exposed.
Preferably, S107 may include:
s1071, depositing an insulating layer, photoetching a pattern of a metal bump on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;
s1072, removing the auxiliary wafer.
Preferably, the metal is copper.
The through-silicon-via adapter plate provided by the embodiment has the advantages that the ESD protection device diode is processed on the through-silicon-via adapter plate, the antistatic capacity of the stacked packaged chips is enhanced, and the problem that the antistatic capacity of the packaged whole system is influenced by the chips with weak antistatic capacity when the chips are stacked in three dimensions is solvedA problem with capacity; meanwhile, the periphery of the formed diode device is all SiO2The insulating layer surrounds the substrate, so that the parasitic capacitance between the active region and the substrate can be effectively reduced.
EXAMPLE III
In this embodiment, based on the above embodiments, specific parameters in the method for manufacturing a through silicon via interposer according to the present invention are described as follows. Specifically, referring to fig. 3a to 3h, fig. 3a to 3h are flow charts of another method for manufacturing a through silicon via interposer for system in package according to an embodiment of the present invention,
s301, as shown in FIG. 3a, selecting a Si substrate 201;
preferably, the doping concentration of the Si substrate is 1014～1017cm-3The thickness is 150 to 250 μm.
S302, as shown in FIG. 3b, an anode 202 and a cathode 203 of the diode are respectively formed on the Si substrate by means of ion implantation;
s3021, flattening the surface of the substrate by using a CMP process;
s3022, photoetching the P + active region, and performing P by adopting a mode of ion implantation with glue+Injecting and removing the photoresist to form the anode of the diode; the doping concentration of silicon is preferably 5X 1018cm-3The doping impurity is preferably boron;
s3023, photoetching the N + active region, and performing N in a mode of ion implantation with glue+And injecting and removing the photoresist to form the cathode of the diode. The doping concentration of silicon is preferably 5X 1018cm-3The doping impurity is preferably phosphorus;
s3024, annealing the substrate at 950-1100 ℃ for 15-120S, and activating impurities.
S303, as shown in figure 3 c; the etching process is used for preparing two TSVs 204 and four isolation trenches 205 on the Si substrate, and the method comprises the following steps:
s3031, depositing a layer of SiO with the thickness of 800nm to 1000nm on the upper surface of a Si substrate by utilizing a thermal oxidation process at the temperature of 950 ℃ to 1100 DEG C2A layer;
s3032, completing TSV and isolation trench etching graphs by steps of gluing, photoetching, developing and the like by utilizing a photoetching process;
s3033, Etching the Si substrate by using a Deep Reactive Ion Etching (DRIE) process to form 40-80 μm Deep TSV and an isolation trench;
s3034, removing SiO on the Si substrate by using CMP process2The substrate surface is planarized.
S304, as shown in FIG. 3 d; deposition of SiO on Si substrates by CVD process2Filling the isolation trench to form an isolation region, which may specifically include the following steps:
s3041, depositing SiO on the surface of the TSV and the isolation trench by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process2Forming an oxide layer with the thickness of 200 nm-300 nm on the inner walls of the TSV and the isolation trench;
s3042, etching the oxide layer on the inner wall of the TSV and the isolation trench by using a wet etching process to complete the planarization of the inner wall of the TSV and the isolation trench. So as to prevent the protrusion of the TSV and the sidewall of the isolation trench from forming an electric field concentration region.
S3043, by using a photoetching process, completing the filling pattern of the isolation trench by steps of gluing, photoetching, developing and the like;
s3044 depositing SiO by Low Pressure Chemical Vapor Deposition (LPCVD) at 690-710 deg.C2Filling the isolation groove to form an isolation region; wherein the SiO2The material is mainly used for isolation and may be replaced by other materials such as undoped polysilicon.
S3045, planarizing the surface of the substrate by using a CMP process.
S305, as shown in FIG. 3 e; the method comprises the following steps of depositing a copper material on a Si substrate by using a copper electroplating process to fill the TSV to form a TSV region, wherein the copper material comprises the following specific steps:
s3051, manufacturing an adhesion layer and a seed layer by using a physical vapor deposition method, wherein the adhesion layer is made of titanium or tantalum, and the seed layer is made of copper.
S3052, filling the TSV with a copper material through an electrochemical deposition method.
S3053, removing the redundant metal layer on the surface of the substrate by utilizing a CMP process.
S306, as shown in FIG. 3 f; the formation of the copper interconnection line 206 on the upper surface of the Si substrate by using the electroplating process may specifically include the following steps:
s3061, depositing SiO on the surface of the substrate by PECVD process2A layer;
s3062, completing contact hole patterns on the anode and the cathode of the diode through steps of gluing, photoetching, developing and the like by utilizing a photoetching process;
s3063, depositing a Ti film by using a CVD (chemical vapor deposition) process to form a liner layer, depositing a TiN film by using a CVD process to form a barrier layer, and depositing tungsten on the anode and the cathode of the diode by using a CVD process to form a tungsten plug 207;
s3064, planarizing the surface of the substrate by using a CMP process.
S3065, depositing SiO2The insulating layer is used for photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating method, removing redundant copper by using a chemical mechanical grinding method, and forming a first end of a TSV (through silicon via) region and a diode serial copper interconnection line;
s3066, planarizing the surface of the substrate by using a CMP process.
S307, as shown in FIG. 3 g; the method for thinning the Si substrate by using the chemical mechanical polishing process to leak the TSV region specifically comprises the following steps:
s3071 bonding the upper surface of the Si substrate with an auxiliary wafer by using a high polymer material as an intermediate layer, and finishing the thinning of the Si substrate through the support of the auxiliary wafer;
s3072, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process until the thickness is slightly larger than the depth of the TSV region, preferably larger than the depth of the TSV by 10 microns;
s3073, flattening the lower surface of the Si substrate by using a CMP (chemical mechanical polishing) process until the TSV region is exposed;
s308, as shown in FIG. 3 h; the forming of the copper bump 208 on the lower surface of the Si substrate by electroplating may specifically include the following steps:
s3081, depositionSiO2An insulating layer for photoetching copper convex point pattern at the second end of the TSV region, depositing copper by electrochemical copper plating process, removing excessive copper by chemical mechanical grinding process, and etching SiO2A layer, forming a copper bump at a second end of the TSV region;
s3082, removing the temporarily bonded auxiliary wafer by using a heating mechanical method.
The preparation method of the through silicon via adapter plate provided by the embodiment can be realized in the conventional TSV process platform, so that the compatibility is strong, and the application range is wide.
In the method for manufacturing the through silicon via interposer provided in this embodiment, the peripheral of the diode device is covered with SiO2The process surrounded by the insulating layer can effectively reduce the parasitic capacitance between the active region and the substrate. According to the invention, on the basis of considering process feasibility, the parasitic capacitance and resistance are reduced by optimally setting the TSV holes with a certain length and utilizing the doping concentration in a given range and considering the current passing capacity of the device, and the parasitic capacitance of the device is tuned to a certain degree by utilizing the inductance introduced by the TSV holes, so that the ESD resistance of the system-in-package is improved and the working range of the ESD protection circuit is expanded.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For example, the plurality of isolation regions mentioned in the present invention are only illustrated according to the cross-sectional view of the device structure provided in the present invention, wherein the plurality of isolation regions may also be a first portion and a second portion shown in a cross-sectional view of a ring body as a whole, and it should not be limited to these descriptions for a person skilled in the art to which the present invention pertains, and several simple deductions or replacements can be made without departing from the spirit of the present invention, and all of them should be considered as belonging to the protection scope of the present invention.
Claims (6)
1. A through-silicon-via interposer for system-in-package, comprising:
a Si substrate (101);
a plurality of lateral diodes (102) disposed within the Si substrate (101);
isolation regions (103) disposed on both sides of each of the lateral diodes (102) to form laterally enclosed device regions;
TSV regions (104) disposed at both sides of a region formed by the plurality of lateral diodes (102) and the isolation region (103);
an interconnect line (105) connecting in series a first end face of the TSV region (104) and the lateral diode (102);
SiO2insulating layers provided on the upper and lower surfaces of the Si substrate (101);
wherein the isolation region (103) and the TSV region (104) both penetrate the Si substrate (101) up and down; the depth of the isolation region (103) is equal to that of the TSV region (104), and the depth of the isolation region and the depth of the TSV region are both 80 mu m.
2. The through-silicon via interposer of claim 1, wherein a tungsten plug (106) is disposed between the lateral diode (102) and the interconnect line (105).
3. The through-silicon via interposer of claim 1, wherein the material in the isolation region (103) is SiO2Or undoped polysilicon.
4. The through silicon via interposer of claim 1, wherein the filler material within the TSV region (104) is copper.
5. The through silicon via interposer of claim 1, wherein a metal bump (107) is disposed on the second end surface of the TSV region (104).
6. The through silicon via interposer of claim 5, wherein the metal bump (107) is copper.
Priority Applications (1)
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