CN108321154A - TSV pinboards and preparation method thereof based on SCR pipes - Google Patents
TSV pinboards and preparation method thereof based on SCR pipes Download PDFInfo
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- CN108321154A CN108321154A CN201711349015.9A CN201711349015A CN108321154A CN 108321154 A CN108321154 A CN 108321154A CN 201711349015 A CN201711349015 A CN 201711349015A CN 108321154 A CN108321154 A CN 108321154A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000000463 material Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims description 49
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 37
- 229910052802 copper Inorganic materials 0.000 claims description 37
- 239000010949 copper Substances 0.000 claims description 37
- 238000001259 photo etching Methods 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 22
- 238000011049 filling Methods 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 6
- 238000004070 electrodeposition Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 33
- 238000005516 engineering process Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000003292 glue Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
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- 238000004100 electronic packaging Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of TSV pinboards and preparation method thereof based on SCR pipes, this method includes：Choose substrate material；SCR pipes are prepared in the substrate material；It etches the substrate material and forms isolated groove in SCR pipes both sides to form device region；It etches the substrate material and forms TSV in the device region both sides；It fills the isolated groove and the TSV forms isolated area and the areas TSV；Prepare the interconnection line of the first end face and the SCR pipes in the areas TSV；Second end face in the areas TSV prepares metal salient point.TSV pinboards provided by the invention enhance the antistatic effect of laminate packaging chip by processing ESD protection device SCR pipes on TSV pinboards.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a TSV adapter plate based on an SCR tube and a preparation method thereof.
Background
Along with the rapid development of intelligent power supply technology and high-power semiconductor devices, electronic products are increasingly miniaturized and portable, and the application field of power electronic devices is promoted to be continuously expanded. According to investigation, among various factors causing the functional failure of power electronic devices and Integrated Circuits (ICs), electrostatic discharge (ESD) is a main factor of the functional failure of the devices and the ICs, because the devices or products may generate static electricity during manufacturing, packaging, testing and using processes, and when people contact with each other under unknown conditions, a discharge path is formed, thereby causing the functional failure or permanent damage of the products. Therefore, the ESD protection problem is one of the important issues in the field of integrated circuit design. With the increasing scale of integrated circuits, the difficulty of ESD protection design is increasing.
Three-dimensional packaging techniques have come to light due to the ever-increasing demands on the size and power consumption of semiconductor chips, i.e., the need for smaller, thinner, lighter, highly reliable, multifunctional, low power, and low cost chips. In the case where the packing density of the two-dimensional packing technology has reached the limit, the advantages of the higher density three-dimensional (3D) packing technology are self-evident.
The Through-Silicon Via (TSV) technology is a new technical solution for realizing interconnection of stacked chips in a 3D integrated circuit. Due to the TSV technology, the stacking density of the chips in the three-dimensional direction can be maximized, the interconnection lines among the chips are shortest, and the overall dimension is minimized, so that the 3D chip stacking can be effectively realized, the manufactured chips with more complex structures, stronger performance and more cost efficiency are manufactured, and the TSV technology becomes the most attractive technology in the existing electronic packaging technology.
An interposer generally refers to the functional layer of interconnection and pin redistribution between a chip and a package substrate. The adapter plate can redistribute dense I/O leads, high-density interconnection of multiple chips is achieved, and the adapter plate becomes one of the most effective means for electrical signal connection between a nanoscale integrated circuit and a millimeter-scale macroscopic world. When the multifunctional chip integration is realized by using the adapter plate, the antistatic capability of different chips is different, and the antistatic capability of the whole system after packaging can be influenced by the chips with weak antistatic capability during three-dimensional stacking; therefore, how to improve the antistatic capability of the system-in-package of the 3D-IC based on the TSV process becomes an urgent problem to be solved in the semiconductor industry.
Disclosure of Invention
In order to improve the antistatic capability of a 3D integrated circuit based on a TSV process, the invention provides a TSV adapter plate based on a thyristor and also called a Silicon Controlled Rectifier (SCR) and a preparation method thereof; the technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a TSV adapter plate based on an SCR tube, which comprises the following steps:
s101, selecting a substrate material;
s102, preparing an SCR tube in a substrate material;
s103, etching the substrate material to form isolation grooves on two sides of the SCR tube so as to form a device area;
s104, etching the substrate material to form TSV on two sides of the device area;
s105, filling the isolation groove and the TSV to form an isolation region and a TSV region;
s106, preparing an interconnection line of the first end face of the TSV region and the SCR tube;
and S107, preparing a metal bump on the second end face of the TSV region.
In one embodiment of the present invention, S102 includes:
s1021, preparing an N well region and a P well region of the SCR tube in the substrate material;
s1022, preparing an N well contact region, a cathode, a P well contact region and an anode of the SCR tube in the N well region and the P well region.
In one embodiment of the present invention, S1021 includes:
s10211, preparing a masking layer by Chemical Vapor Deposition (CVD);
s10212, photoetching N well region pattern, and performing N by ion implantation+Injecting and removing the photoresist to form an N well region;
s10213, photoetching P well region pattern, and performing P by ion implantation+And injecting and removing the photoresist to form a P well region.
In one embodiment of the present invention, S1022 includes:
s10221, photoetching N-well contact region and cathode pattern, and performing N by adopting ion implantation process+Injecting and removing lightEtching glue to form an N-well contact region and a cathode;
s10222, photoetching P-well contact region and anode pattern, and performing P by ion implantation+And injecting and removing the photoresist to form a P well contact region and an anode.
In one embodiment of the present invention, S105 includes:
s1051, flattening the TSV and the inner wall of the isolation trench;
s1052, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1053, filling SiO in the isolation trench by CVD process2Forming an isolation region;
s1054, forming a TSV filling pattern by utilizing a photoetching process;
s1055, manufacturing an adhesion layer and a seed layer by using a physical vapor deposition method;
and S1056, filling the TSV by an electrochemical deposition method to form a TSV region.
In one embodiment of the present invention, S106 includes:
s1061, forming a liner layer and a barrier layer on the upper surface of the substrate material by using a CVD (chemical vapor deposition) process, and forming a tungsten plug on the SCR tube;
s1062, depositing an insulating layer, photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating process, removing redundant copper by using a chemical mechanical grinding process, and forming the first end face of the TSV region and an interconnection line of the SCR tube.
In an embodiment of the present invention, S107 further includes:
x1, using the auxiliary wafer as a support for the upper surface of the substrate material; thinning the lower surface of the substrate material;
and x2, planarizing the lower surface of the substrate material by using a Chemical Mechanical Polishing (CMP) process until the second end surface of the TSV region is exposed.
In one embodiment of the present invention, S107 includes:
s1071, depositing an insulating layer, photoetching a pattern of a metal bump on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;
s1072, removing the auxiliary wafer.
In one embodiment of the invention, the substrate material is a Si substrate, and the thickness is 150-250 mu; the depth of the TSV region and the isolation region is 80-120 mu m.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the TSV adapter plate, the ESD protection device SCR tube is processed on the TSV adapter plate, so that the antistatic capacity of a stacked packaging chip is enhanced;
2. according to the invention, the SCR tube is processed on the TSV adapter plate, and the high heat dissipation capacity of the adapter plate is utilized, so that the high-current passing capacity of the device in the working process is improved;
3. the TSV adapter plate provided by the invention has the advantages that the periphery of the SCR tube is provided with the vertically-through isolation grooves, so that the leakage current and the parasitic capacitance are smaller;
4. the preparation method of the TSV adapter plate based on the SCR tube can be realized in the existing TSV process platform, so that the compatibility is strong, and the application range is wide.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a TSV interposer based on an SCR tube according to an embodiment of the present invention;
fig. 2a to fig. 2i are flow charts of another TSV interposer manufacturing method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a TSV interposer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a TSV interposer based on an SCR tube according to an embodiment of the present invention, including:
s101, selecting a substrate material;
s102, preparing an SCR tube in a substrate material;
s103, etching the substrate material to form isolation grooves on two sides of the SCR tube so as to form a device area;
s104, etching the substrate material to form TSV on two sides of the device area;
s105, filling the isolation groove and the TSV to form an isolation region and a TSV region;
s106, preparing an interconnection line of the first end face of the TSV region and the SCR tube;
and S107, preparing a metal bump on the second end face of the TSV region.
Preferably, S102 may include:
s1021, preparing an N well region and a P well region of the SCR tube in the substrate material;
s1022, preparing an N well contact region, a cathode, a P well contact region and an anode of the SCR tube in the N well region and the P well region.
Further, S1021 may include:
s10211, preparing a masking layer by using a CVD (chemical vapor deposition) process;
s10212, photoetching N well region pattern, and performing N by ion implantation+Injecting and removing the photoresist to form an N well region;
s10213, photoetching P well region pattern, and performing P by ion implantation+And injecting and removing the photoresist to form a P well region.
Further, S1022 may include:
s10221, photoetching N-well contact region and cathode pattern, and performing N by adopting ion implantation process+Injecting and removing the photoresist to form an N-well contact region and a cathode;
s10222, photoetching P-well contact region and anode pattern, and performing P by ion implantation+And injecting and removing the photoresist to form a P well contact region and an anode.
Preferably, S105 may include:
s1051, flattening the TSV and the inner wall of the isolation trench;
s1052, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1053, filling SiO in the isolation trench by CVD process2Forming an isolation region;
s1054, forming a TSV filling pattern by utilizing a photoetching process;
s1055, manufacturing an adhesion layer and a seed layer by using a physical vapor deposition method;
and S1056, filling the TSV by an electrochemical deposition method to form a TSV region.
Preferably, S106 may include:
s1061, forming a liner layer and a barrier layer on the upper surface of the substrate material by using a CVD (chemical vapor deposition) process, and forming a tungsten plug on the SCR tube;
s1062, depositing an insulating layer, photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating process, removing redundant copper by using a chemical mechanical grinding process, and forming the first end face of the TSV region and an interconnection line of the SCR tube.
Specifically, S107 is preceded by:
x1, using the auxiliary wafer as a support for the upper surface of the substrate material; thinning the lower surface of the substrate material;
and x2, flattening the lower surface of the substrate material by using a CMP process until the second end face of the TSV region is exposed.
Further, S107 may include:
s1071, depositing an insulating layer, photoetching a pattern of a metal bump on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;
s1072, removing the auxiliary wafer.
Preferably, the substrate material is a Si substrate, and the thickness is 150-250 mu; the depth of the TSV region and the isolation region is 80-120 mu m.
According to the TSV adapter plate provided by the embodiment, the transverse SCR tube is processed on the TSV adapter plate, so that the antistatic capacity of stacked and packaged chips is enhanced, and the problem that the antistatic capacity of a packaged whole system is affected by chips with weak antistatic capacity during three-dimensional stacking is solved; meanwhile, the isolation regions which are communicated up and down are arranged around the SCR tube of the TSV adapter plate, so that the TSV adapter plate has smaller leakage current and parasitic capacitance.
Example two
In this embodiment, based on the above embodiments, specific parameters in the preparation method of the TSV interposer of the present invention are described as follows. Specifically, referring to fig. 2a to fig. 2i, fig. 2a to fig. 2i are flow charts of another TSV interposer manufacturing method according to an embodiment of the present invention,
s201, as shown in FIG. 2a, selecting a Si substrate 201;
preferably, the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 1014cm-3The thickness is 150 to 250 μm.
S202, as shown in FIG. 2 b; the preparation method of the N-well region 202 and the P-well region 203 of the SCR transistor by using the ion implantation process specifically includes the following steps:
s2021, forming SiO on the surface of the Si substrate by thermal oxidation process at 1050-1100 deg.C2A buffer layer;
s2022, depositing Si on the surface of the Si substrate by Low Pressure Chemical Vapor Deposition (LPCVD) process at the temperature of 700-800 DEG C3N4A layer;
s2023, photoetching the N well region, performing phosphorus injection by adopting an ion injection process with glue, removing the photoresist to form the N well region of the SCR tube, wherein the doping concentration is preferably 1 multiplied by 1017cm-3；
S2024, annealing the substrate at 950 ℃ for 2.5 hours, and advancing an N well;
s2025, removing Si on the surface of the substrate by using a wet etching process3N4A layer;
s2026, photoetching the P well region, performing boron injection by adopting an ion injection process with glue, removing the photoresist to form the P well region of the SCR tube, wherein the doping concentration is preferably 1 x 1018cm-3；
S2027, annealing the substrate at 950 ℃ for 2.5h, and advancing the P well.
S203, as shown in FIG. 2 c; the preparation of the N-well contact region 204, the cathode 205, the P-well contact region 206 and the anode 207 of the SCR tube may specifically include the following steps:
s2031, photoetching an N-well contact area and a cathode, and performing N by adopting an ion implantation process with glue+Injecting and removing the photoresist to form an N trap contact region and N of the SCR tube+And a cathode. The doping concentration is preferably 1.5X 1020cm-3The doping impurity is preferably phosphorus;
s2032, photoetching the P well contact area and the cathode, and performing P by adopting an ion implantation process with glue+Injecting and removing the photoresist to form a P well contact region and a P of the SCR tube+And an anode. The doping concentration is preferably 1.5X 1020cm-3The doping impurity is preferably boron;
s2033, annealing the substrate at 950-1100 ℃ for 15-120S, and activating impurities.
S204, as shown in fig. 2d, preparing the TSV208 and the isolation trench 209 on the Si substrate by using an etching process, may include the following steps:
s2041, growing a layer of SiO with the thickness of 800nm to 1000nm on the upper surface of a Si substrate by a thermal oxidation process at the temperature of 1050 ℃ to 1100 DEG C2A layer;
s2042, completing TSV and isolation trench etching patterns through processes of gluing, photoetching, developing and the like by utilizing a photoetching process;
s2043, Etching the Si substrate by using a Deep Reactive Ion Etching (DRIE) process to form TSV and an isolation trench with the depth of 80-120 mu m;
s2044, removing SiO on the Si substrate by using CMP process2The substrate surface is planarized.
Preferably, two isolation trenches are located between two TSVs.
S205, as shown in FIG. 2 e; deposition of SiO on Si substrates by CVD process2Filling the isolation trench to form an isolation region, which may specifically include the following steps:
s2051, thermally oxidizing the inner walls of the TSV and the isolation trench to form an oxide layer with the thickness of 200nm to 300nm at the temperature of 1050 ℃ to 1100 ℃;
and S2052, etching the oxide layers on the inner walls of the TSV and the isolation groove by using a wet etching process to finish the flattening of the inner walls of the TSV and the isolation groove. Preventing the TSV and the protrusion of the side wall of the isolation trench from forming an electric field concentration area;
s2053, completing the filling graph of the isolation groove by using a photoetching process through processes such as gluing, photoetching, developing and the like;
s2054, depositing SiO by LPCVD process at 690-710 deg.C2Filling the isolation groove to form an isolation region; as can be appreciated, the SiO2The material is mainly used for isolation and can be replaced by other materials such as undoped polysilicon and the like;
s2055, planarizing the surface of the substrate by using a CMP process.
S206, as shown in FIG. 2 f; the method comprises the following steps of depositing a copper material to fill the TSV by using a copper electroplating process to form a TSV region, and specifically comprises the following steps:
s2061, manufacturing an adhesion layer and a seed layer on the TSV by using a physical vapor deposition method, wherein the adhesion layer is made of titanium or tantalum, and the seed layer is made of copper;
s2062, filling the copper material in the TSV by an electrochemical deposition method;
s2063, removing the redundant metal layer on the surface of the substrate by utilizing the CMP process.
S207, as shown in FIG. 2 g; the formation of the copper interconnection line 210 on the upper surface of the Si substrate by using the electroplating process may specifically include the following steps:
s2071, depositing SiO on the surface of the substrate by PECVD process2A layer;
s2072, completing contact hole patterns on the anode and the cathode of the SCR tube by using a photoetching process through steps of gluing, photoetching, developing and the like;
s2073, depositing a Ti film, a TiN film and tungsten on the N well contact area 204, the cathode 205, the P well contact area 206 and the anode 207 of the SCR tube by using a CVD process to form a tungsten plug 207;
and S2074, flattening the surface of the substrate by using a CMP process.
S2075, depositing SiO2The insulating layer is used for photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating method, removing redundant copper by using a chemical mechanical grinding method, and forming a copper interconnection line which is connected with the first end of the TSV region and the SCR tube in series;
and S2076, flattening the surface of the substrate by using a CMP process.
Further, when the copper interconnection line is prepared, the metal interconnection line can be used to be wound in a spiral shape so as to have the characteristic of inductance for better electrostatic protection of the radio frequency integrated circuit.
S208, as shown in FIG. 2 h; the method for thinning the Si substrate by using the chemical mechanical polishing process to leak the TSV region specifically comprises the following steps:
s2081, bonding the upper surface of the Si substrate with an auxiliary wafer by using a high polymer material as an intermediate layer, and finishing the thinning of the Si substrate through the support of the auxiliary wafer;
s2082, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process until the thickness is slightly larger than the depth of the TSV region, preferably larger than the depth of the TSV by 10 microns;
s2083, flattening the lower surface of the Si substrate by using a CMP process until the TSV region is exposed;
s209, as shown in FIG. 2 i; the copper bump 211 is formed on the lower surface of the Si substrate by an electroplating copper method, which may specifically include the following steps:
s2091, depositing SiO2An insulating layer for photoetching copper convex point pattern at the second end of the TSV region, depositing copper by electrochemical copper plating process, removing excessive copper by chemical mechanical grinding process, and etching SiO2A layer, forming a copper bump at a second end of the TSV region;
s2092, removing the temporarily bonded auxiliary wafer by using a heating mechanical method.
In the method for manufacturing the esd protection device for system in package provided in this embodiment, the periphery of the SCR device is covered by SiO2The process surrounded by the insulating layer can effectively reduce the parasitic capacitance between the active region and the substrate. According to the invention, on the basis of considering process feasibility, the parasitic capacitance and resistance are reduced by optimally setting the TSV holes with a certain length and utilizing the doping concentration in a given range and considering the current passing capacity of the device, and the parasitic capacitance of the device is tuned to a certain degree by utilizing the inductance introduced by the TSV holes, so that the ESD resistance of the system-in-package is improved and the working range of the ESD protection circuit is expanded.
EXAMPLE III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a TSV interposer according to an embodiment of the present invention; in this embodiment, a structure of a TSV interposer is described in detail based on the above embodiments, wherein the TSV interposer is manufactured by the above manufacturing process shown in fig. 2a to fig. 2 i. Specifically, the TSV adapter plate includes:
si substrate 301, first TSV region 3021, second TSV region 3022, first isolation region 3031, second isolation region 3032, SCR tubes, first interconnect line 3101, second interconnect line 3102, and copper bump 311; wherein,
the SCR tube is located between the first isolation region 3031 and the second isolation region 3032; the region formed by the SCR tube, the first isolation region 3031 and the second isolation region 3032 is positioned between the first TSV region 3021 and the second TSV region 3022; first interconnect 3101 and second interconnect 3102 are located over a first end of first TSV region 3021, a first end of second TSV region 3022, and the SCR tube; copper bump 311 is located on the second end of first TSV region 3021 and the second end of second TSV region 3022.
Specifically, the SCR tube includes: n-well region 304, P-well region 305, N-well contact region 306 of the SCR tube, cathode 307, anode 308, and P-well contact region 309.
Further, a first interconnecting line 3101 is used to connect the first end face of the first TSV region 3021, the N-well contact region 306, and the anode 308; second interconnect lines 3102 are used to connect the first end of second TSV region 3022, cathode 307, and P-well contact region 309.
Specifically, the material filled in the TSV region 302 is copper; isolation region 303 filled material SiO2。
Specifically, a tungsten plug is provided between the first interconnect line 3101 and the N-well contact region 306 and the anode 308; a tungsten plug is disposed between the second interconnect line 3102 and the cathode 307 and the P-well contact region 309.
Further, the upper and lower surfaces of the Si substrate 301 are each provided with an insulating layer.
Preferably, the interconnect 309 is a copper interconnect.
The anti-static device provided by the embodiment has a simple structure, can bear very high ESD current by utilizing the low maintaining voltage of the SCR tube, has the characteristic of high ESD robustness naturally, and greatly improves the anti-static capability of the integrated circuit during system-in-package by arranging the SCR tube in the adapter plate.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For example, the plurality of isolation regions mentioned in the present invention are only illustrated according to the cross-sectional view of the device structure provided in the present invention, wherein the plurality of isolation regions may also be a first portion and a second portion shown in a cross-sectional view of a ring body as a whole, and it should not be limited to these descriptions for a person skilled in the art to which the present invention pertains, and several simple deductions or replacements can be made without departing from the spirit of the present invention, and all of them should be considered as belonging to the protection scope of the present invention.
Claims (10)
1. A preparation method of a TSV adapter plate based on an SCR tube is characterized by comprising the following steps:
s101, selecting a substrate material;
s102, preparing an SCR tube in the substrate material;
s103, etching the substrate material to form isolation grooves on two sides of the SCR tube so as to form a device area;
s104, etching the substrate material to form TSV on two sides of the device region;
s105, filling the isolation groove and the TSV to form an isolation region and a TSV region;
s106, preparing an interconnection line of the first end face of the TSV region and the SCR tube;
and S107, preparing a metal bump on the second end face of the TSV region.
2. The method according to claim 1, wherein S102 comprises:
s1021, preparing an N well region and a P well region of the SCR tube in the substrate material;
s1022, preparing an N well contact region, a cathode, a P well contact region and an anode of the SCR tube in the N well region and the P well region.
3. The method according to claim 2, wherein S1021 comprises:
s10211, preparing a masking layer by using a CVD (chemical vapor deposition) process;
s10212, photoetching the N well region pattern, and performing N by adopting an ion implantation process+Injecting and removing the photoresist to form the N well region;
s10213, photoetching the P well region pattern, and performing P by adopting an ion implantation process+And injecting and removing the photoresist to form the P well region.
4. The method according to claim 3, wherein S1022 comprises:
s10221, photoetching the N trap contact area and the cathode pattern, and performing N by adopting an ion implantation process+Injecting and removing the photoresist to form the N-well contact region and the cathode;
s10222, photoetching the P well contact region and the anode pattern, and performing P by adopting an ion implantation process+And injecting and removing the photoresist to form the P well contact region and the anode.
5. The method according to claim 1, wherein S105 comprises:
s1051, flattening the inner walls of the TSV and the isolation trench;
s1052, forming a filling pattern of the isolation trench by utilizing a photoetching process;
s1053, filling SiO in the isolation groove by using CVD process2Forming the isolation region;
s1054, forming a filling pattern of the TSV by utilizing a photoetching process;
s1055, manufacturing an adhesion layer and a seed layer by using a physical vapor deposition method;
and S1056, filling the TSV by an electrochemical deposition method to form the TSV region.
6. The method according to claim 1, wherein S106 comprises:
s1061, forming a liner layer and a barrier layer on the upper surface of a substrate material by using a CVD (chemical vapor deposition) process, and forming a tungsten plug on the SCR tube;
s1062, depositing an insulating layer, photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating process, removing redundant copper by using a chemical mechanical grinding process, and forming the first end face of the TSV region and the interconnection line of the SCR tube.
7. The method of claim 1, wherein S107 is preceded by:
x1, using an auxiliary wafer as a support for the upper surface of the substrate material; thinning the lower surface of the substrate material;
and x2, utilizing a CMP process to carry out planarization treatment on the lower surface of the substrate material until the second end face of the TSV region is exposed.
8. The method according to claim 7, wherein S107 comprises:
s1071, depositing an insulating layer, photoetching a pattern of the metal bump on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;
s1072, removing the auxiliary wafer.
9. The preparation method according to claim 1, wherein the substrate material is a Si substrate with a thickness of 150-250 μ; the depth of the TSV region and the isolation region is 80-120 mu m.
10. An SCR tube-based TSV adapter plate, characterized in that the TSV adapter plate is formed by the method of any one of claims 1-9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN101699625A (en) * | 2009-10-28 | 2010-04-28 | 苏州博创集成电路设计有限公司 | High trigger current SCR and ESD protective device |
| CN101764151A (en) * | 2009-11-09 | 2010-06-30 | 苏州博创集成电路设计有限公司 | SCR ESD protective structure with high maintaining voltage |
| CN101840918A (en) * | 2010-04-14 | 2010-09-22 | 电子科技大学 | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| CN105264660A (en) * | 2013-05-21 | 2016-01-20 | 吉林克斯公司 | Charge damage protection on an interposer for a stacked die assembly |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
| CN106783942A (en) * | 2016-11-30 | 2017-05-31 | 辽宁大学 | A kind of two-way SCR structure for ESD protections |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| CN206727069U (en) * | 2017-04-28 | 2017-12-08 | 江南大学 | A kind of ESD protection device with resistor capacitor diode auxiliary triggering SCR structure |
-
2017
- 2017-12-15 CN CN201711349015.9A patent/CN108321154A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN101699625A (en) * | 2009-10-28 | 2010-04-28 | 苏州博创集成电路设计有限公司 | High trigger current SCR and ESD protective device |
| CN101764151A (en) * | 2009-11-09 | 2010-06-30 | 苏州博创集成电路设计有限公司 | SCR ESD protective structure with high maintaining voltage |
| CN101840918A (en) * | 2010-04-14 | 2010-09-22 | 电子科技大学 | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| CN105264660A (en) * | 2013-05-21 | 2016-01-20 | 吉林克斯公司 | Charge damage protection on an interposer for a stacked die assembly |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
| CN106783942A (en) * | 2016-11-30 | 2017-05-31 | 辽宁大学 | A kind of two-way SCR structure for ESD protections |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| CN206727069U (en) * | 2017-04-28 | 2017-12-08 | 江南大学 | A kind of ESD protection device with resistor capacitor diode auxiliary triggering SCR structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
| CN113571513B (en) * | 2021-09-23 | 2022-01-04 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
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