CN108109990A - For the silicon hole pinboard of system in package - Google Patents
For the silicon hole pinboard of system in package Download PDFInfo
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- CN108109990A CN108109990A CN201711352508.8A CN201711352508A CN108109990A CN 108109990 A CN108109990 A CN 108109990A CN 201711352508 A CN201711352508 A CN 201711352508A CN 108109990 A CN108109990 A CN 108109990A
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- tsv
- silicon hole
- isolated area
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- diode
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000010949 copper Substances 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052681 coesite Inorganic materials 0.000 claims description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims description 13
- 229910052682 stishovite Inorganic materials 0.000 claims description 13
- 229910052905 tridymite Inorganic materials 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000012856 packing Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 47
- 230000000694 effects Effects 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 23
- 230000008569 process Effects 0.000 description 22
- 238000001259 photo etching Methods 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 12
- 238000002360 preparation method Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000969106 Megalaima haemacephala Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of silicon hole pinboard for system in package, including：Si substrates (101)；Multiple transverse diodes (102) are arranged in the Si substrates (101)；Isolated area (103) is arranged at the both sides of each transverse diode (102) to form device region between two neighboring isolated area；TSV areas (104) are arranged at the both sides by the device region and the isolated area forming region；Interconnection line (105) is connected in series the first end face and the transverse diode (102) of the TSV areas (104)；Wherein, Si substrates (101) described in the equal up/down perforation of the isolated area (103) and the TSV areas (104).Silicon hole pinboard provided by the invention is used as ESD protection device by processing diode on silicon hole pinboard, it solves the problems, such as that the IC system grade encapsulation antistatic effect based on TSV techniques is weak, enhances the antistatic effect of IC system grade encapsulation.
Description
Technical field
The invention belongs to semiconductor integrated circuit technology field, more particularly to a kind of silicon hole for system in package is transferred
Plate.
Background technology
With the continuous diminution of feature sizes of semiconductor devices, Moore's Law is more and more hard to carry on.Particularly in recent years,
With the proposition for surmounting Moore's Law, system in package becomes one of main flow direction of semiconductor industry future development.Based on silicon
The system in package of through hole (Through-Silicon Via, abbreviation TSV) technology because with high density of integration, low signal delay,
The advantages that low-power consumption, becomes the hot spot of academia and industrial quarters research.At present, generally acknowledge in the industry and three-dimensional heap is carried out to semiconductor element
The 3D technology difficult point folded and connected up is heavy, and the 2.5D encapsulation technologies of pinboard are introduced between semiconductor element and package substrate and are
Chip can be made to continue on one of important technology that the blueprint of Moore's Law advances.
On the other hand, inside semicon industry, raising and device feature size with integrated circuit integrated level
Reduce, potentiality caused by static discharge (Electro-Static Discharge, abbreviation ESD) is damaged in integrated circuit
Become more and more apparent.According to relevant report, the failure for having nearly 35% in the failure of integrated circuit fields is triggered by ESD,
Therefore chip internal is all designed with esd protection structure to improve the reliability of device.
Pinboard typically refers to the functional layer of the interconnection and pin redistribution between chip and package substrate.Pinboard can be with
Intensive I/O leads are redistributed, the high density interconnection of multi-chip is realized, it is grand with grade to become nanometer-grade IC
Electric signal connects one of most effective means between seeing the world.When realizing that multifunction chip is integrated using pinboard, not same core
The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether the anti-quiet of whole system after encapsulation when three-dimensional stacked
Electric energy power, therefore it is urgently to be resolved hurrily as semicon industry how to improve the antistatic effect of the system in package based on TSV techniques
The problem of.
The content of the invention
In order to improve the antistatic effect of the system in package of TSV techniques, the present invention provides one kind to be used for system-level envelope
The silicon hole pinboard of dress；The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of silicon hole pinboard for system in package, including：
Si substrates 101；
Multiple transverse diodes 102, are arranged in Si substrates 101；
Isolated area 103 is arranged at the both sides of each transverse diode 102 to form the device region of transverse seal；
TSV areas 104 are arranged at the both sides by device region and isolated area forming region；
Interconnection line 105, first end face and transverse diode 102 to TSV areas 104 are connected in series；
Wherein, 104 equal up/down perforation Si substrates 101 of isolated area 103 and TSV areas.
In one embodiment of the invention, tungsten plug 106 is provided between transverse diode 102 and interconnection line 105.
In one embodiment of the invention, the material in isolated area 103 is SiO2Or undoped polycrystalline silicon.
In one embodiment of the invention, the packing material in TSV areas 104 is copper.
In one embodiment of the invention, metal salient point 107 is set in the second end face in TSV areas 104.
In one embodiment of the invention, the material of metal salient point 107 is copper.
In one embodiment of the invention, isolated area 103 and the depth in TSV areas 104 are 40~80 μm.
Compared with prior art, the invention has the advantages that：
1st, silicon hole pinboard provided by the invention by silicon hole pinboard set ESD protection device diode,
Enhance the antistatic effect of laminate packaging chip；
2nd, the present invention, using the higher heat-sinking capability of pinboard, is improved by setting diode on silicon hole pinboard
High current handling capacity in device work；
3rd, the isolated area of up/down perforation is utilized around the diode of silicon hole pinboard provided by the invention, is had smaller
Leakage current and parasitic capacitance.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of silicon hole adapter plate structure schematic diagram for system in package provided in an embodiment of the present invention；
Fig. 2 is a kind of preparation method flow of silicon hole pinboard for system in package provided in an embodiment of the present invention
Figure；
Fig. 3 a- Fig. 3 h are the preparation of another silicon hole pinboard for system in package provided in an embodiment of the present invention
Method flow diagram.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of silicon hole adapter plate structure for system in package provided in an embodiment of the present invention
Schematic diagram, including：
Si substrates 101；
Multiple transverse diodes 102, are arranged in Si substrates 101；
Isolated area 103 is arranged at the both sides of each transverse diode 102 to form the device region of transverse seal；
TSV areas 104 are arranged at the both sides by device region and isolated area forming region；
Interconnection line 105, first end face and transverse diode 102 to TSV areas 104 are connected in series；
Wherein, 104 equal up/down perforation Si substrates 101 of isolated area 103 and TSV areas.
Specifically, tungsten plug 106 is provided between transverse diode 102 and interconnection line 105.
Further, the material in isolated area 103 is SiO2Or undoped polycrystalline silicon.
Preferably, the packing material in TSV areas 104 is copper.
Preferably, metal salient point 107 is set in the second end face in TSV areas 104.
Preferably, the material of metal salient point 107 is copper.
Preferably, isolated area 103 and the depth in TSV areas 104 are 40~80 μm.
Preferably, the SiO for being arranged at 101 upper and lower surface of Si substrates is further included2Insulating layer.
Silicon hole pinboard provided in this embodiment by silicon hole pinboard set ESD protection device diode,
Enhance the antistatic effect of laminate packaging chip；Meanwhile the present embodiment provides silicon hole pinboards to be set around diode
The isolated area of up/down perforation has smaller leakage current and parasitic capacitance.
Embodiment two
Fig. 2 is refer to, Fig. 2 is a kind of system of silicon hole pinboard for system in package provided in an embodiment of the present invention
Preparation Method flow chart, the present embodiment on the basis of above-described embodiment, to the present invention silicon hole pinboard preparation method into
Row is described in detail as follows.Specifically, include the following steps：
S101, substrate material is chosen；
S102, multiple ESD protection devices are prepared on substrate material；
S103, etched substrate material form isolated groove in ESD protection device both sides；
S104, etched substrate material form TSV on the outside of isolated groove；
S105, isolated groove and TSV formation isolated areas and TSV areas are filled respectively；
S106, the first end face that TSV areas are prepared in substrate material upper surface and the interconnection line of ESD protection device；
S107, the second end face in TSV areas prepare metal salient point to complete the preparation of silicon hole pinboard.
Preferably, substrate material be Si materials, crystal orientation be (100), (110) or (111), doping concentration 1014~
1017cm-3, thickness is 150~250 μm.
Preferably, ESD protection device is transversary diode.
Further, S102 can include：
S1021, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation CMP) technique, it is right
The upper surface of substrate material carries out smooth；
S1022, P is formed using photoetching process+Active area figure carries out P using band glue ion implantation technology+Injection, removal
Photoresist forms the anode of transversary diode；
S1023, N is formed using photoetching process+Active area figure carries out N using band glue ion implantation technology+Injection, removal
Photoresist forms the cathode of transversary diode；
S1024, high annealing, activator impurity are carried out.
Preferably, S105 can include：
S1051, thermal oxide TSV and isolated groove are in the inner wall of TSV and isolated groove formation oxide layer；
S1052, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；
S1053, the filling figure that isolated groove is formed using photoetching process；
S1054, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, isolating
Filling SiO in groove2Form isolated area；
S1055, the filling figure that TSV is formed using photoetching process；
S1056, adhesion layer and Seed Layer are made using physical vapor deposition methods；
S1057, TSV is filled by the method for electrochemical deposition to form TSV areas.
Preferably, S106 can include：
S1061, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works are utilized
Skill forms tungsten plug in the anode and cathode of transversary diode；
S1062, deposition insulating layer, photoetching interconnection graph deposit copper product using electrochemical plating process for copper, pass through chemical machine
Tool grinding technics removes extra copper product, forms the copper interconnecting line that the first end in TSV areas is concatenated with transversary diode.
Specifically, further included before S107：
X1, by the use of aiding in supporting item of the disk as Si substrate top surfaces；
X2, Si substrates lower surface is thinned using mechanical grinding reduction process, CMP process is recycled, to Si substrates
Lower surface carry out planarizing process, the second end face until exposing TSV areas.
Preferably, S107 can include：
S1071, deposition insulating layer in the figure of the second end face photolithographic salient point in TSV areas, utilize electrochemical plating coppersmith
Skill deposits metal, and extra metal is removed by chemical mechanical milling tech, and the second end face in TSV areas forms metal salient point；
S1072, auxiliary disk is removed.
Preferably, metal is copper.
Silicon hole pinboard provided in this embodiment by silicon hole pinboard process ESD protection device diode,
The antistatic effect of laminate packaging chip is enhanced, the weak chip of antistatic effect influences whether to encapsulate when solving three-dimensional stacked
Afterwards the problem of the antistatic effect of whole system；Meanwhile the diode component periphery formed is by SiO2Insulating layer surrounds, can
Effectively reduce the parasitic capacitance between active area and substrate.
Embodiment three
The present embodiment is on the basis of above-described embodiment, to specifically joining in the preparation method of the silicon hole pinboard of the present invention
Number citing is described as follows.Specifically, Fig. 3 a- Fig. 3 h, Fig. 3 a- Fig. 3 h are refer to be used for for another kind provided in an embodiment of the present invention
The preparation method flow chart of the silicon hole pinboard of system in package,
S301, as shown in Figure 3a chooses Si substrates 201；
Preferably, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μm.
S302, as shown in Figure 3b, the mode for being utilized respectively ion implanting on a si substrate forms 202 He of anode of diode
Cathode 203；
S3021, using CMP process, substrate surface is planarized；
S3022, photoetching P+ active areas, carry out P by the way of with glue ion implanting+Injection removes photoresist, forms two
The anode of pole pipe；Doping concentration preferably 5 × 1018cm-3, the preferred boron of impurity；
S3023, photoetching N+ active areas, carry out N by the way of with glue ion implanting+Injection removes photoresist, forms two
The cathode of pole pipe.Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity；
S3024, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S303, as shown in Figure 3c；Prepare two TSV204 and four isolated grooves on a si substrate using etching technics
205, it may include steps of：
S3031, at a temperature of 950 DEG C~1100 DEG C, utilize thermal oxidation technology one layer of surface deposition on a si substrate
The SiO of 800nm~1000nm2Layer；
S3032, using photoetching process, by gluing, photoetching, development and etc. complete TSV and isolated groove etched features；
S3033, using deep reaction ion etching method (Deep Reactive Ion Etching, abbreviation DRIE) technique,
Si substrates are etched, form the TSV and isolated groove of 40~80 μm of depths；
S3034, using CMP process, remove the SiO on Si substrates2, substrate surface is planarized.
S304, as shown in Figure 3d；Using CVD techniques, SiO is deposited on a si substrate2Isolated groove is filled to be formed
Isolated area specifically may include steps of：
S3041, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor are utilized
Deposition, PECVD) technique, in TSV and isolated groove surface deposition SiO2, the inner wall of TSV and isolated groove is made to form thickness
It spends for 200nm~300nm oxide layers；
S3042, using wet-etching technology, etch the oxide layer of inner wall of TSV and isolated groove to complete TSV and isolation
The planarizing of trench wall.To prevent the protrusion of TSV and isolated groove side wall from forming electric field concentrated area.
S3043, using photoetching process, by gluing, photoetching, development and etc. complete isolated groove and fill figure；
S3044, at a temperature of 690 DEG C~710 DEG C, utilize low-pressure chemical vapor deposition (Low Pressure
Chemical Vapor Deposition, LPCVD) technique, deposit SiO2Isolated groove is filled, forms isolated area；Its
In, the SiO2Material is mainly used for isolating, and can be substituted by other materials such as undoped polycrystalline silicons.
S3045, using CMP process, substrate surface is planarized.
S305, as shown in Figure 3 e；Using copper plating process, copper product is deposited on a si substrate, TSV is filled to be formed
TSV areas, specifically may include steps of：
S3051, one layer of adhesion layer and one layer of Seed Layer are made using physical vapor deposition methods, the material of adhesion layer is titanium
Or tantalum, the material of Seed Layer is copper.
S3052, copper product is filled in TSV by the method for electrochemical deposition.
S3053, CMP process, the extra metal layer of removal substrate surface are utilized.
S306, as illustrated in figure 3f；Using electroplating technology, surface forms copper interconnecting line 206 on a si substrate, can specifically wrap
Include following steps：
S3061, using pecvd process, deposit SiO in substrate surface2Layer；
S3062, anode and cathode in diode, using photoetching process, by gluing, photoetching, development and etc. completion
Contact hole graph；
S3063, laying is formed using CVD techniques deposit Ti films, barrier layer, profit is formed using CVD techniques deposit TiN film
Tungsten plug 207 is formed with anode and cathode deposition tungsten of the CVD techniques in diode；
S3064, substrate surface is planarized using CMP process.
S3065, deposit SiO2Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating
The method for learning mechanical lapping removes extra copper, and the first end for forming TSV areas concatenates copper interconnecting line with diode；
S3066, substrate surface is planarized using CMP process.
S307, as shown in figure 3g；Si substrates are thinned using CMP process, TSV areas is leaked out, specifically may be used
To include the following steps：
S3071, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Being thinned for Si substrates is completed in the support of disk；
S3072, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV areas until reducing to
The thickness of depth, preferably greater than 10 μm of TSV depth；
S3073, Si substrates lower surface is carried out using CMP process it is smooth, until exposing TSV areas；
S308, as illustrated in figure 3h；Copper bump 208 is formed using electric plating method in Si substrates lower surface, can specifically be wrapped
Include following steps：
S3081, deposit SiO2Insulating layer, the second end photoetching copper bump figure in TSV areas, utilizes electrochemical plating process for copper
Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in TSV areas form copper bump；
S3082, the auxiliary disk being bonded temporarily using the method dismounting of heated mechanical.
The preparation method of silicon hole pinboard provided in this embodiment can realize in existing TSV technique platforms, because
This compatibility is strong, applied widely.
The preparation method of silicon hole pinboard provided in this embodiment, using diode component periphery by SiO2Insulating layer bag
The technique enclosed can effectively reduce the parasitic capacitance between active area and substrate.The present invention is led on the basis of technological feasibility is considered
The TSV holes for crossing optimal design-aside certain length and the doping concentration using given range, and consider the electric current handling capacity of device,
Parasitic capacitance and resistance are reduced, and a degree of tuning is carried out to the parasitic capacitance of device using the inductance that TSV holes introduce,
The working range of esd protection circuit is expanded while raising system in package anti-ESD abilities.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For example, the multiple isolated areas referred in the present invention are only according to this hair
The device architecture sectional view of bright offer illustrates, wherein, multiple isolated areas can also be such as ring bodies in some entirety
The first portion that shows of sectional view and second portion, for those of ordinary skill in the art to which the present invention belongs, no
These explanations should be confined to, without departing from the inventive concept of the premise, several simple deduction or replace can also be made, all should
When being considered as belonging to protection scope of the present invention.
Claims (7)
1. a kind of silicon hole pinboard for system in package, which is characterized in that including：
Si substrates (101)；
Multiple transverse diodes (102) are arranged in the Si substrates (101)；
Isolated area (103) is arranged at the both sides of each transverse diode (102) to form the device region of transverse seal；
TSV areas (104) are arranged at the both sides by the device region and the isolated area (103) forming region；
Interconnection line (105) is connected in series the first end face and the transverse diode (102) of the TSV areas (104)；
Wherein, Si substrates (101) described in the equal up/down perforation of the isolated area (103) and the TSV areas (104).
2. silicon hole pinboard according to claim 1, which is characterized in that the transverse diode (102) and interconnection line
(105) tungsten plug (106) is provided between.
3. silicon hole pinboard according to claim 1, which is characterized in that the material in the isolated area (103) is SiO2
Or undoped polycrystalline silicon.
4. silicon hole pinboard according to claim 1, which is characterized in that the packing material in the TSV areas (104) is
Copper.
5. silicon hole pinboard according to claim 1, which is characterized in that set in the second end face of the TSV areas (104)
Put metal salient point (107).
6. silicon hole pinboard according to claim 5, which is characterized in that the material of the metal salient point (107) is copper.
7. silicon hole pinboard according to claim 1, which is characterized in that the isolated area (103) and the TSV areas
(104) depth is 40~80 μm.
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| CN106856201A (en) * | 2015-12-09 | 2017-06-16 | 三星电子株式会社 | Imageing sensor, its manufacture method and the system including the imageing sensor |
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| CN101320708A (en) * | 2007-06-06 | 2008-12-10 | 株式会社瑞萨科技 | Manufacturing method of semiconductor integrated circuit device |
| US20120007154A1 (en) * | 2010-07-12 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV Formation Processes Using TSV-Last Approach |
| CN106170853A (en) * | 2014-02-28 | 2016-11-30 | 勒丰德里有限公司 | Manufacture method and the semiconductor product of semiconductor device |
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