CN107894803A

CN107894803A - A kind of bias-voltage generating circuit in Internet of Things

Info

Publication number: CN107894803A
Application number: CN201711004357.7A
Authority: CN
Inventors: 陈磊
Original assignee: Danyang Constant Core Electronics Co Ltd
Current assignee: Danyang Constant Core Electronics Co Ltd
Priority date: 2017-10-25
Filing date: 2017-10-25
Publication date: 2018-04-10

Abstract

Patent of the present invention discloses the bias-voltage generating circuit in a kind of Internet of Things, including：One micro-current generation circuit, its core is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as little as na level, and power consumption is very small；One reference generating circuit, using cascade cascaded structure, the precision of caused bias voltage is also very high, be affected by temperature it is smaller, due in whole circuit do not use resistance, so the area of overall circuit is also very small.

Description

A kind of bias-voltage generating circuit in Internet of Things

Technical field

The present invention relates to the bias voltage in bias-voltage generating circuit field, more particularly to a kind of Internet of Things to produce electricity Road.

Background technology

In the application of Internet of Things and most of wireless telecommunications, associated receiver circuitry or radiating circuit etc. are all that needs are low Power consumption, therefore the bias-voltage generating circuit of low-power consumption is very crucial and very necessary for whole application.Biasing Pith of the potential circuit as analog circuit, the normal work within the scope of a wider temperature is generally required, therefore not Require nothing more than low in energy consumption, it is also necessary to stable performance, there is preferable temperature characterisitic.Traditional mode can be entered using band-gap reference circuit Row design, but its power consumption is all that microwatt level is other, is not belonging to low power dissipation design category.

The content of the invention

It is inclined in a kind of Internet of Things it is a primary object of the present invention to provide to overcome the above-mentioned problems of the prior art Voltage generation circuit is put, the advantages that it possesses low-power consumption and less silicon area.

In view of the above and other objects, the present invention provides the bias-voltage generating circuit in a kind of Internet of Things, it is at least wrapped Include：

One micro-current generation circuit, its core is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is as little as na level Electric current, power consumption is very small；One reference generating circuit, using cascode structure, the precision of caused bias voltage is also very Height, due to not using resistance in whole circuit, so the area of overall circuit is also very small.

The present invention proposes the bias-voltage generating circuit in a kind of Internet of Things, including：One micro-current generation circuit, its core The heart is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as little as na level, and power consumption is very small；One benchmark Generation circuit, using cascode structure, the precision of caused bias voltage is also very high, due to not adopted in whole circuit With resistance, so the area of overall circuit is also very small；It is characterized in that：The micro-current generation circuit is by the first PMOS PM1, the second PMOS PM2, the 7th PMOS PM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed, PM1 pipes and PM2 pipes Source electrode be all connected with supply voltage VDD, PM2 grid is connected with PM1 grid, PM1 drain, NM8 drain； PM2 drain is connected with the drain electrode of NM8 grid, PM7 grid, PM7 source electrode, PM7；NM8 source electrode and NM9 grid Pole, NM9 drain are connected；The Substrate ground of PM7 pipes, wherein PM7 pipes use as diode；NM9 source ground；It is described Reference generating circuit is by the 3rd PMOS PM3, the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, and first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 are formed；The source electrode of PM3 pipes, the source electrode of PM4 pipes, the source electrode of PM5 pipes, PM6 pipes source electrode all with power supply Voltage VDD is connected；The grid of PM3 pipes, the grid of PM4 pipes, the grid of PM5 pipes, PM6 grid are connected with the grid of PM2 pipes Together；PM3 drain is connected with NM6 drain, NM6 grid, NM7 grid；NM6 source electrode and NM7 drain, NM5 source electrode is connected；NM7 source ground；PM4 drain is connected with NM4 drain, NM4 grid, NM5 grid； NM4 source electrode is connected with NM5 drain, NM3 source electrode；PM5 drain and NM2 grid, NM2 drain, NM3 grid It is connected；NM2 source electrode is connected with NM3 drain, NM1 source electrode；PM6 drain and the drain phase of NM1 grid, NM1 Connection, output end of its node as bias voltage VREF；NM1 pipes, NM2 pipes, NM3 pipes, NM4 pipes, NM5 pipes, NM6 pipes, NM7 The Substrate ground of pipe, NM8 pipes and NM9 pipes；PM1 pipes, PM2 pipes, PM3 pipes, PM4 pipes, PM5 are managed and the substrate of PM6 pipes meets VDD.

Brief description of the drawings

The accompanying drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention Apply example and its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：

Fig. 1 is the bias-voltage generating circuit figure in a kind of Internet of Things of the present invention；

Fig. 2 is PMOS PM7 structural representations of the present invention.

Embodiment

With reference to shown in Fig. 1, in the following embodiments, the bias-voltage generating circuit, it is comprised at least：One micro-current Generation circuit, its core are that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as little as na level, power consumption It is very small；One reference generating circuit, using cascode structure, the precision of caused bias voltage is also very high, due to whole Resistance is not used in circuit, so the area of overall circuit is also very small.

Described micro-current generation circuit is made up of PMOS PM1, PM2, PM7, NMOS tube NM8, NM9, and PM7 is as one Positive diode, its voltage is a threshold voltage, equivalent to the gate source voltage sum of NM8 pipes and NM9 pipes, then just force NM8 pipes enter sub-threshold region, therefore caused electric current Ib is the low current of nA ranks.

Fig. 2 is the structural representation of PM7 pipes, and P-substrate is P type substrate, and n-WEll is the n traps of PMOS, Cathode is the negative pole of diode, and Anode is the positive pole of diode.PM7 grid, source electrode, drain electrode are connected as diode just Pole, substrate avoid using temperature change caused by big resistance as diode cathode, it also avoid using parasitic pnp, PM7 Voltage between grid source of the voltage of positive pole-negative pole equal to NM8 and NM9 and, therefore NM8 pipes enter sub-threshold region.

The reference generating circuit by PMOS PM3, PM4, PM5, PM6, NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7 are formed；NM1, NM2, NM3, NM4, NM5, NM6, NM7 are cascaded in a manner of automatic biasing, NM6 and NM7, NM4 and NM5, NM2 and NM3 are biased in subthreshold region all in identical p-well, and they all produce positive temperature coefficient electricity Pressure；Transistor PM2, PM3, PM4 and PM5 are equal sized, and PM6 size is three times of PM2 pipes, and the electric current for flowing through PM6 is also stream Cross PM2 tube currents three times.

Output end of the drain of PM6 pipes as bias voltage VREF, electric current flow through NM1 pipes, the two of weak inversion regime work Pole pipe connection transistor NM1 is used as negative temperature coefficient voltage, finally VREF go out to produce one of Positive and Negative Coefficient Temperature counteracting it is inclined Put magnitude of voltage.

The present invention proposes a kind of bias-voltage generating circuit of the low-power consumption of no resistance, compared with other circuits, circuit In do not utilize BJT, structure is simpler, and transistor is operated in subthreshold region in circuit, significantly reduces supply voltage and power consumption. The circuit is only had 20nA circuit, is belonged to low-power consumption bias voltage using 0.18 μm of CMOS technology design of smic, whole circuit Circuit, circuit can be worked under as little as 1V supply voltage, and 750mV output electricity is provided in the range of -25 DEG C to 125 DEG C Pressure, the voltage difference between maximum and minimum value is only 1.8mV.

Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention In the case of, easily carry out various modifications or embodiment can be combined, these also should be regarded as protection scope of the present invention.

Claims

1. the bias-voltage generating circuit in a kind of Internet of Things, including：

2. as described in the appended claim 1：The micro-current generation circuit is by the first PMOS PM1, the second PMOS PM2, the 7th PMOS PM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed, the source electrode of PM1 pipes and PM2 pipes all with supply voltage VDD It is connected, PM2 grid is connected with PM1 grid, PM1 drain, NM8 drain；PM2 drain and NM8 grid, The drain electrode of PM7 grid, PM7 source electrode, PM7 is connected；NM8 source electrode is connected with NM9 grid, NM9 drain；PM7 The Substrate ground of pipe, wherein PM7 pipes use as diode；NM9 source ground；The reference generating circuit is by the 3rd PMOS Pipe PM3, the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the first NMOS tube NM1, the second NMOS tube NM2, 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 are formed；PM3 The source electrode of pipe, the source electrode of PM4 pipes, the source electrode of PM5 pipes, the source electrode of PM6 pipes are all connected with supply voltage VDD；The grid of PM3 pipes Pole, the grid of PM4 pipes, the grid of PM5 pipes, the PM6 grid of grid and PM2 pipes link together；PM3 drain and NM6's Drain, NM6 grid, NM7 grid are connected；NM6 source electrode is connected with NM7 drain, NM5 source electrode；NM7 source electrode Ground connection；PM4 drain is connected with NM4 drain, NM4 grid, NM5 grid；NM4 source electrode and NM5 drain, NM3 Source electrode be connected；PM5 drain is connected with NM2 grid, NM2 drain, NM3 grid；NM2 source electrode and NM3's Drain, NM1 source electrode are connected；PM6 drain is connected with NM1 grid, NM1 drain, and its node is as bias voltage VREF output end.