CN103926967B - Low-voltage and low-power-consumption reference voltage source and low reference voltage generating circuit - Google Patents
Low-voltage and low-power-consumption reference voltage source and low reference voltage generating circuit Download PDFInfo
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- CN103926967B CN103926967B CN201410154983.4A CN201410154983A CN103926967B CN 103926967 B CN103926967 B CN 103926967B CN 201410154983 A CN201410154983 A CN 201410154983A CN 103926967 B CN103926967 B CN 103926967B
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Abstract
The invention provides a low-voltage and low-power-consumption reference voltage source comprises a starting circuit, a low reference voltage generating circuit and a stabilizing circuit and is characterized in that the starting circuit detects a voltage signal at the first output end of the low reference voltage generating circuit so as to judge whether the low reference voltage generating circuit works normally; when the low reference voltage generating circuit is not started, an output current source is generated by the starting circuit forcibly to charge the low reference voltage generating circuit, after the charging is completed, the low reference voltage generating circuit is started and works normally, the voltage signal at the first output end of the low reference voltage generating circuit changes in a jump mode, and the starting circuit automatically switches off the output current source according to the detected voltage signal; the voltage signal is generated at the first output end of the low reference voltage generating circuit to be output to the starting circuit; when the low reference voltage generating circuit works normally, a reference voltage is generated at the second output end of the low reference voltage generating circuit to be output, and meanwhile, the third output end of the low reference voltage generating circuit outputs a reference voltage sampling signal to obtain the stabilizing circuit.
Description
Technical field
The present invention relates in simulation and Digital Analog Hybrid Circuits the reference voltage source and the circuit that need to produce low-voltage and low-power dissipation, particularly relate to the low-voltage and low-power dissipation reference voltage source based on CMOS technology and low reference voltage generating circuit.
Background technology
High precision and stable reference voltage source, in simulation and mixed signal, are applied widely.In some communication devices, as RFID, hand-held mobile terminal, demand is proposed to the reference voltage source of small size, low pressure, low-power consumption, low temperature sensitivity.
Traditional reference voltage source circuit adopts the band gap properties of diode or BJT triode to realize usually, owing to being about 0.6V under the forward voltage normal temperature of diode and BJT pipe, under subzero temperature, even can be high to 0.8V, in such a circuit, supply voltage just can not drop to lower value, also can not provide hundreds of mV reference voltage.
Adopt the metal-oxide-semiconductor being operated in sub-threshold region can realize the reference voltage source of low pressure, low-power consumption, low temperature sensitivity, but implement and can there is certain difficulty.
Summary of the invention
One of technical matters to be solved by this invention is to provide low-voltage and low-power dissipation reference voltage source.
Two of technical matters to be solved by this invention is the low reference voltage generating circuit providing output reference voltage lower than 1V.
The present invention, in order to solve the problems of the technologies described above, adopts following technical scheme:
Low-voltage and low-power dissipation reference voltage source, comprises start-up circuit, low reference voltage generating circuit and stabilizing circuit; Be characterized in:
Start-up circuit detects the voltage signal of low reference voltage generating circuit first output terminal, to judge whether in normal mode of operation; When low reference voltage generating circuit is not activated, start-up circuit forces generation output current source to charge to low reference voltage generating circuit, to be charged complete after, low reference voltage generating circuit is activated, enter normal mode of operation, the voltage signal generation saltus step of low reference voltage generating circuit first output terminal simultaneously, start-up circuit according to the voltage signal detected, cuts out output current source more automatically; Start-up circuit is used for guaranteeing that low reference voltage generating circuit enters normal operating conditions;
Described low reference voltage generating circuit first output terminal produces voltage signal and outputs to start-up circuit; When normal mode of operation, the second output terminal produces reference voltage and exports, and meanwhile, this low reference voltage generating circuit the 3rd output terminal output reference voltage sampled signal is to stabilizing circuit;
Described stabilizing circuit and low reference voltage generating circuit form feedback loop, and when reference voltage rises, stabilizing circuit produces the signal suppressing reference voltage to rise, and reference voltage is stablized; To compensate low reference voltage generating circuit internal positive feedback loop to the impact of circuit stability, and feedback loop gain is greater than low reference voltage generating circuit internal positive feedback loop gain; To ensure that circuit enters steady state (SS), prevent low reference voltage generating circuit from entering vibration district.
By start-up circuit, the present invention guarantees that low reference voltage generating circuit enters normal operating conditions, and start-up circuit cuts out automatically after low reference voltage generating circuit enters normal operating conditions, low reference voltage generating circuit internal positive feedback loop is compensated on the impact of circuit stability by stabilizing circuit, ensure that circuit enters steady state (SS), produce low reference voltage by low reference voltage generating circuit; Structure of the present invention is simple, and circuit stability is reliable, has the advantages such as low-power consumption, low-work voltage, low output reference voltage.
According to a kind of preferred version of described low-voltage and low-power dissipation reference voltage source, described low reference voltage generating circuit comprises first, second equivalent PMOS, first, second PMOS, first, second, 3rd NMOS tube and current-limiting resistance, first, second, the substrate and first of the 3rd NMOS tube, the source electrode of the second NMOS tube all connects with ground, first, second, the grid of the 3rd NMOS tube connects with the drain electrode of the second NMOS tube simultaneously, also the drain electrode of PMOS equivalent with first connects, the source electrode of the 3rd NMOS tube is by current-limiting resistance ground connection, the drain electrode of the 3rd NMOS tube connects with the drain electrode of the second equivalent PMOS, the source electrode of first, second equivalent PMOS all connects with the drain electrode of the second PMOS, and the grid of first, second equivalent PMOS all connects with ground, the substrate of first, second equivalent PMOS connects, the grid of first, second PMOS connects with the drain electrode of the first PMOS and the drain electrode of the first NMOS tube simultaneously, and the source electrode of first, second PMOS is all connected with power supply.
The present invention adopts the NMOS tube being operated in sub-threshold region to produce zero warm output reference voltage, has feature low in energy consumption; The VGS voltage of NMOS tube subzero temperature characteristic and the positive temperature characteristics voltage at equivalent PMOS two ends are cancelled out each other, and form the output voltage of zero temperature characteristics, and circuit structure is simple, has the feature of low-work voltage, low output reference voltage.
According to a kind of preferred version of described low-voltage and low-power dissipation reference voltage source, each equivalent PMOS is formed by many PMOS serial connections, namely the grid of these many PMOS links together simultaneously, as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
According to a kind of preferred version of described low-voltage and low-power dissipation reference voltage source, described start-up circuit comprises the 15,16 PMOS and the 5th to the 8th NMOS tube; Wherein, the 15, the substrate of 16 PMOS and source electrode connect power supply, the substrate of the 5th to the 8th NMOS tube and the source ground of the 5th NMOS tube; Grid and the drain electrode of the 5th NMOS tube are connected together, and connect with the source electrode of the 6th NMOS tube, and the grid of the 6th NMOS tube is connected together with drain electrode and is connected with the drain electrode of the 15 PMOS; The grid of the 15 PMOS connects the first output terminal of low reference voltage generating circuit; 16 PMOS and the 7th NMOS tube form phase inverter, their grid is connected together, and connect with the drain electrode of the 15 PMOS, the drain electrode of the 16 PMOS and the 7th NMOS tube is connected together and connects with the grid of the 8th NMOS tube, the drain electrode of the 8th NMOS tube connects with power supply, and the source output of the 8th MN8 pipe is to low reference voltage generating circuit.
Start-up circuit design of the present invention is ingenious, by detecting certain node voltage of low reference voltage generating circuit, accurately judge whether low reference voltage generating circuit starts, when low reference voltage generating circuit is not activated, start-up circuit forces generation output current source to charge to low reference voltage generating circuit, to be charged complete after, start-up circuit according to the voltage signal that detects, cuts out output current source more automatically.
A kind of low reference voltage generating circuit, be characterized in: described low reference voltage generating circuit comprises first, second equivalent PMOS, first, second PMOS, first, second, 3rd NMOS tube and current-limiting resistance, first, second, the substrate and first of the 3rd NMOS tube, the source electrode of the second NMOS tube all connects with ground, first, second, the grid of the 3rd NMOS tube connects with the drain electrode of the second NMOS tube simultaneously, also the drain electrode of PMOS equivalent with first connects, the source electrode of the 3rd NMOS tube is by current-limiting resistance ground connection, the drain electrode of the 3rd NMOS tube connects with the drain electrode of the second equivalent PMOS, the source electrode of first, second equivalent PMOS all connects with the drain electrode of the second PMOS, and the grid of first, second equivalent PMOS all connects with ground, the substrate of first, second equivalent PMOS connects, the grid of first, second PMOS connects with the drain electrode of the first PMOS and the drain electrode of the first NMOS tube simultaneously, and the source electrode of first, second PMOS is all connected with power supply.
According to a kind of preferred version of described low reference voltage generating circuit, each equivalent PMOS is formed by many PMOS serial connections, namely the grid of these many PMOS links together simultaneously, as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
The beneficial effect of low-voltage and low-power dissipation reference voltage source of the present invention and low reference voltage generating circuit is: by start-up circuit, the present invention guarantees that low reference voltage generating circuit enters normal operating conditions, and start-up circuit cuts out automatically after low reference voltage generating circuit enters normal operating conditions, low reference voltage generating circuit internal positive feedback loop is compensated on the impact of circuit stability by stabilizing circuit, ensure that circuit enters steady state (SS), produce low reference voltage by low reference voltage generating circuit; Structure of the present invention is simple, and circuit stability is reliable, has low-power consumption, low-work voltage, low output reference voltage, high-precision advantage; In RFID, hand-held communication system, there is larger advantage.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of low-voltage and low-power dissipation reference voltage source of the present invention.
Fig. 2 is in start-up course, the waveform change transient curve of main bias node.
Fig. 3 is the reference voltage temperature variation curve of low reference voltage generating circuit 2.
Fig. 4 is the total current temperature variation curve of low reference voltage generating circuit 2.
Embodiment
See Fig. 1, low-voltage and low-power dissipation reference voltage source, be made up of start-up circuit 1, low reference voltage generating circuit 2 and stabilizing circuit 3, wherein, the input end of start-up circuit 1 connects with first output terminal of low reference voltage generating circuit 2, the output terminal of start-up circuit 1 connects with the input end of low reference voltage generating circuit 2, second output terminal of low reference voltage generating circuit 2 exports as reference voltage source, and connect with the output terminal of stabilizing circuit 3, the 3rd output terminal of low reference voltage generating circuit 2 connects with the input end of steady dot circuit 3.
Start-up circuit 1 detects the voltage signal of low reference voltage generating circuit 2 first output terminal, to judge that 2 whether in normal mode of operation; When low reference voltage generating circuit 2 is not activated, start-up circuit 1 forces generation output current source to charge to low reference voltage generating circuit 2, to be charged complete after, low reference voltage generating circuit 2 is activated, enter normal mode of operation, the voltage signal generation saltus step of low reference voltage generating circuit 2 first output terminal simultaneously, start-up circuit 2 according to the voltage signal detected, cuts out output current source more automatically;
Described low reference voltage generating circuit 2 first output terminal produces voltage signal and outputs to start-up circuit 1; When normal mode of operation, the second output terminal produces reference voltage and exports, and meanwhile, this low reference voltage generating circuit 2 the 3rd output terminal output reference voltage sampled signal is to stabilizing circuit 3;
Described stabilizing circuit 3 forms feedback loop with low reference voltage generating circuit 2, and when reference voltage rises, stabilizing circuit 3 produces the signal suppressing reference voltage to rise, and reference voltage is stablized; And feedback loop gain is greater than low reference voltage generating circuit 2 internal positive feedback loop gain; To ensure that circuit enters steady state (SS).
Described low reference voltage generating circuit 2 is by first, second equivalent PMOS MPS1, MPS2, first, second PMOS MP1, MP2, first, second, 3rd NMOS tube MN1, MN2, MN3, electric capacity C2, C3 and current-limiting resistance R2 is formed, first, second, 3rd NMOS tube MN1, MN2, the substrate of MN3 and first, second NMOS tube MN1, the source electrode of MN2 all connects with ground VSS, first, second, 3rd NMOS tube MN1, MN2, the grid of MN3 connects with the drain electrode of the second NMOS tube MN2 simultaneously, also the drain electrode of PMOS MPS1 equivalent with first connects, and connected with ground VSS by electric capacity C3, the source electrode of the 3rd NMOS tube MN3 is connected with the drain electrode of the second equivalent PMOS MPS2 by the drain electrode of current-limiting resistance R2 ground connection VSS, the 3rd NMOS tube MN3, and provides voltage to described stabilizing circuit 3, the source electrode of first, second equivalent PMOS MPS1, MPS2 all connects with the drain electrode of the second PMOS MP2, as the output terminal of reference voltage, the grid of first, second equivalent PMOS MPS1, MPS2 all connects with ground VSS, the substrate of first, second equivalent PMOS MPS1, MPS2 connects, the grid of first, second PMOS MP1, MP2 connects with the drain electrode of the first PMOS MP1 and the drain electrode of the first NMOS tube MN1 simultaneously, and is connected with power supply VCC by electric capacity C2, the source electrode of first, second PMOS MP1, MP2 is all connected with power supply VCC.
Described low reference voltage generating circuit utilizes the subzero temperature characteristic of NMOS tube MN2, the MN3 and NMOS tube MN2VGS voltage being operated in sub-threshold region to realize zero warm output voltage.Be operated in sub-threshold region and proportional NMOS tube MN2, the MN3 of breadth length ratio can produce the voltage difference of positive temperature coefficient at resistance R2 two ends, this voltage difference is added in the two ends of resistance R2, produce the electric current of positive temperature coefficient, the electric current of positive temperature coefficient flows through the NMOS tube MN2 of subzero temperature characteristic and is operated in the equivalent PMOS MPS1 of linear zone, the subzero temperature characteristic VGS voltage of NMOS tube MN2 and the positive temperature characteristics voltage at equivalent PMOS MPS1 two ends are cancelled out each other, form the output voltage of zero temperature characteristics, be reference voltage.
Each equivalent PMOS is formed by many PMOS serial connections, and namely the grid of these many PMOS links together simultaneously, and as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
In a particular embodiment, first equivalent PMOS MPS1 is connected in series by six PMOS MP3 ~ MP8 and forms, second equivalent PMOS MPS2 is also connected in series by six PMOS MP9 ~ MP14 and forms, and the quantity forming the PMOS of equivalent PMOS is determined by the output pressure of reference voltage source.The substrate of PMOS MP3 ~ MP14 connects with the source electrode of PMOS MP8.
Described start-up circuit 2 comprises the 15,16 PMOS MP15, MP16 and the 5th to the 8th NMOS tube MN5, MN6, MN7, MN8; Wherein, the 15, the substrate of 16 PMOS MP15, MP16 and source electrode meet power supply VCC, the substrate of the 5th to the 8th NMOS tube MN5, MN6, MN7, MN8 and the source ground of the 5th NMOS tube MN5; Grid and the drain electrode of the 5th NMOS tube MN5 are connected together, and connect with the source electrode of the 6th NMOS tube MN6, and the grid of the 6th NMOS tube MN6 is connected together with drain electrode and is connected with the drain electrode of the 15 PMOS MP15; The grid of the 15 PMOS MP15 connects the first output terminal of low reference voltage generating circuit 2; 16 PMOS MP16 and the 7th NMOS tube MN7 forms phase inverter, their grid is connected together, and connect with the drain electrode of the 15 PMOS MP15, the drain electrode of the 16 PMOS MP16 and the 7th NMOS tube MN7 is connected together and connects with the grid of the 8th NMOS tube MN8, the drain electrode of the 8th NMOS tube MN8 connects with power supply VCC, and the source output of the 8th MN8 pipe is to low reference voltage generating circuit 2.
See Fig. 1, a kind of low reference voltage generating circuit, by first, second equivalent PMOS MPS1, MPS2, first, second PMOS MP1, MP2, first, second, 3rd NMOS tube MN1, MN2, MN3, electric capacity C2, C3 and resistance R2 is formed, first, second, 3rd NMOS tube MN1, MN2, the substrate of MN3 and first, second NMOS tube MN1, the source electrode of MN2 all connects with ground VSS, first, second, 3rd NMOS tube MN1, MN2, the grid of MN3 connects with the drain electrode of the second NMOS tube MN2 simultaneously, also the drain electrode of PMOS MPS1 equivalent with first connects, and connected with ground VSS by electric capacity C3, the source electrode of the 3rd NMOS tube MN3 is connected with the drain electrode of the second equivalent PMOS MPS2 by the drain electrode of resistance R2 ground connection VSS, the 3rd NMOS tube MN3, and provides voltage to described stabilizing circuit 3, the source electrode of first, second equivalent PMOS MPS1, MPS2 all connects with the drain electrode of the second PMOS MP2, as the output terminal of reference voltage, the grid of first, second equivalent PMOS MPS1, MPS2 all connects with ground VSS, the substrate of first, second equivalent PMOS MPS1, MPS2 connects, the grid of first, second PMOS MP1, MP2 connects with the drain electrode of the first PMOS MP1 and the drain electrode of the first NMOS tube MN1 simultaneously, and is connected with power supply VCC by electric capacity C2, the source electrode of first, second PMOS MP1, MP2 is all connected with power supply VCC.
Above-mentioned equivalent PMOS is formed by many PMOS serial connections, and namely the grid of these many PMOS links together simultaneously, and as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
In a particular embodiment, first equivalent PMOS MPS1 is connected in series by six PMOS MP3 ~ MP8 and forms, second equivalent PMOS MPS2 is also connected in series by six PMOS MP9 ~ MP14 and forms, and the quantity forming the PMOS of equivalent PMOS is determined by the output pressure of reference voltage source.The substrate of PMOS MP3 ~ MP14 connects with the source electrode of PMOS MP8.
Stabilizing circuit as shown in Figure 1, is made up of NMOS tube MN4, electric capacity C1 and resistance R1.The RC feedback of stabilizing circuit inside, is used for guaranteeing that low-voltage and low-power dissipation bias-voltage generating circuit is operated in steady state (SS), prevents low reference voltage generating circuit 2 from entering vibration district.
The principle of work of start-up circuit 1 of the present invention is: when low reference voltage generating circuit 2 not yet starts, node VBP voltage is high level, and PMOS MP15 is operated in cut-off region, and node VBN is low level, and NMOS tube MN1 and MN2 is operated in cut-off region.Because node VBP level is high level, the drain electrode no current of MP15 flows through, and the grid leak of NMOS tube MN6 must be extremely low level, namely VBN6 is low level, after the phase inverter that the low level of VBN6 is consisted of MP16 and MN7, the output level of phase inverter can become high level, and namely VBN8 level is high level.Now, the grid VBN8 of NMOS tube is high level, source electrode VBN is low level, drain electrode is supply voltage VCC, substrate is ground VSS, the conducting of MN8 pipe, power supply VCC is charged to node VBN by the drain-source end of MN8 pipe, and VBN node voltage can raise gradually, after this node voltage is elevated to certain value, MN1 pipe and the conducting of MN2 pipe, the conducting of MN1 pipe, the drain voltage of MN1 pipe can be made to be dragged down, and namely VBP node voltage can be dragged down, when VBP node voltage is pulled down to certain value, MP1 pipe and the conducting of MP2 pipe.Simultaneously MP15 pipe also can conducting, in MP15 turn on process, gate node VBP voltage changes from high to low, this can make MP15 pipe drain node VBN6 voltage be raised to height by low, and after node VBN6 voltage is elevated to certain value, the output VBN8 that MP16 and MN7 forms phase inverter can become low level from high level, MN8 pipe turns off, MN8 pipe stops charging to MN1 and MN2 tube grid, and start-up circuit cuts out, and low-voltage and low-power dissipation bias-voltage generating circuit completes startup.See Fig. 2, power supply electrifying is in stabilization process, and from the transient response curve of node VBN, node VREF, node VBP, start-up circuit serves the function to circuit start.
The principle of low reference voltage generating circuit 2 of the present invention is: after MN2 tube grid signal is amplified by MN1 pipe, be connected to the grid of MP2 pipe, MP2 pipe amplifies further to this signal, then by equivalent PMOS MPS1, feeds back to MN2, and this loop forms positive feedback.The signal voltage of the real-time detection node VB of stabilizing circuit 3, when the signal voltage of node VB rises, the reverse amplification of MN4, the signal voltage of reduction can be produced on VREF, this signal voltage feeds back to VB by equivalent PMOS MPS2, suppress the rising of VB signal voltage, play the function of stable output reference voltage.As shown in Figure 3, curve shows feedback loop stable linearity curve, and stabilizing circuit serves good stablizing effect to the present invention.
Voltage difference between MN3 grid source adds the voltage V between the voltage difference at resistance R2 two ends and MN2 grid source
gS2equal.And MN2 and MN3 is all operated in sub-threshold region, flow through the electric current I of resistance R2
ptatfor positive temperature electric current, its slope can be changed by the ratio of the breadth length ratio setting MN2 pipe and MN3 pipe.
Because the source electrode of MPS1 and MPS2 and source electrode, grid and grid are connected together respectively, and MPS1 and MPS2 drain voltage difference is very little, flows through the electric current approximately equal of MPS1 and MPS2 like this.And MPS1 drain electrode connects with the drain electrode of MN2, the drain electrode of MPS2 connects with the drain electrode of MN3, so flow through the electric current also approximately equal of MN2 and MN3.
Equivalence PMOS MPS1 is serially connected by MP3, MP4, MP5, MP6, MP7, MP8, can be similar to and be interpreted as a constant temperature resistance Rmos1.The reference voltage V that low reference voltage generating circuit 2 produces
rEFobtained by following equation:
V
REF=V
GS2+I
ptat×R
mos1
V
gS2negative temperature characteristic and I
ptat× R
mos1positive temperature characteristics cancel out each other, by reasonably designing V
gS2, I
ptat, R
mos1value, can obtain zero temperature export reference voltage V
rEF.
When the present invention can ensure that supply voltage is lower, still can normally work.Fig. 3 is under different electrical power voltage, reference output voltage variation with temperature family curve, and when supply voltage is low to moderate 0.8V, a kind of low-voltage and low-power dissipation reference voltage source circuit of the present invention still can normally work, and namely has the feature of operating on low voltage.
The present invention is operated in MN2 pipe and the MN3 pipe electric current that only needs consumption is very low of sub-threshold region, just can guarantee that low-voltage and low-power dissipation voltage reference produces circuit and normally works.When the present invention utilizes MN2 pipe and MN3 pipe to be operated in sub-threshold region, the feature that drain current is very little, realizes low power consumption characteristic.Fig. 4 is supply voltage when being 1.2V, and the temperature variant curve of total current of a kind of low-voltage and low-power dissipation reference voltage source circuit of the present invention, can draw from curve: maximum operating currenbt is less than 1.5uA.Illustrate that a kind of low-voltage and low-power dissipation reference voltage source circuit of the present invention has the feature of low-power consumption.
Result of implementation above shows: a kind of low-voltage and low-power dissipation reference voltage source circuit of the present invention has the features such as low working power voltage, low output reference voltage, low-power consumption.The technology of the present invention can be applied in RFID label chip and other low-power consumption IC chip.
Claims (5)
1. low-voltage and low-power dissipation reference voltage source, comprises start-up circuit (1), low reference voltage generating circuit (2) and stabilizing circuit (3); It is characterized in that:
Start-up circuit (1) detects the voltage signal of low reference voltage generating circuit (2) first output terminal, to judge that whether (2) are in normal mode of operation; When low reference voltage generating circuit (2) is not activated, start-up circuit (1) forces generation output current source to charge to low reference voltage generating circuit (2), to be charged complete after, low reference voltage generating circuit (2) is activated, enter normal mode of operation, the voltage signal generation saltus step of low reference voltage generating circuit (2) first output terminal simultaneously, start-up circuit (2) according to the voltage signal detected, cuts out output current source more automatically;
Described low reference voltage generating circuit (2) first output terminal produces voltage signal and outputs to start-up circuit (1); When normal mode of operation, the second output terminal produces reference voltage and exports, and meanwhile, this low reference voltage generating circuit (2) the 3rd output terminal output reference voltage sampled signal is to stabilizing circuit (3);
Described stabilizing circuit (3) and low reference voltage generating circuit (2) form feedback loop, and when reference voltage rises, stabilizing circuit (3) produces the signal suppressing reference voltage to rise, and reference voltage is stablized;
Described low reference voltage generating circuit (2) comprises first, second equivalent PMOS (MPS1, MPS2), first, second PMOS (MP1, MP2), first, second, 3rd NMOS tube (MN1, MN2, and resistance (R2) MN3), first, second, 3rd NMOS tube (MN1, MN2, MN3) substrate and first, second NMOS tube (MN1, MN2) source electrode all connects with ground (VSS), first, second, 3rd NMOS tube (MN1, MN2, MN3) grid connects with the drain electrode of the second NMOS tube (MN2) simultaneously, also the drain electrode of PMOS (MPS1) equivalent with first connects, the source electrode of the 3rd NMOS tube (MN3) is by resistance (R2) ground connection (VSS), the drain electrode of the 3rd NMOS tube (MN3) connects with the drain electrode of the second equivalent PMOS (MPS2), the source electrode of first, second equivalent PMOS (MPS1, MPS2) all connects with the drain electrode of the second PMOS (MP2), and the grid of first, second equivalent PMOS (MPS1, MPS2) all connects with ground (VSS), the substrate of first, second equivalent PMOS (MPS1, MPS2) connects, the grid of first, second PMOS (MP1, MP2) connects with the drain electrode of the first PMOS (MP1) and the drain electrode of the first NMOS tube (MN1) simultaneously, and the source electrode of first, second PMOS (MP1, MP2) is all connected with power supply (VCC).
2. low-voltage and low-power dissipation reference voltage source according to claim 1, it is characterized in that: each equivalent PMOS is formed by many PMOS serial connections, namely the grid of these many PMOS links together simultaneously, as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
3. low-voltage and low-power dissipation reference voltage source according to claim 1 and 2, is characterized in that: described start-up circuit (2) comprises the 15,16 PMOS (MP15, MP16) and the 5th to the 8th NMOS tube (MN5, MN6, MN7, MN8); Wherein, 15, the substrate of 16 PMOS (MP15, MP16) and source electrode connect power supply (VCC), the substrate of the 5th to the 8th NMOS tube (MN5, MN6, MN7, MN8) and the source ground of the 5th NMOS tube (MN5); Grid and the drain electrode of the 5th NMOS tube (MN5) are connected together, and connect with the source electrode of the 6th NMOS tube (MN6), the grid of the 6th NMOS tube (MN6) is connected together with drain electrode and is connected with the drain electrode of the 15 PMOS (MP15); The grid of the 15 PMOS (MP15) connects the first output terminal of low reference voltage generating circuit (2); 16 PMOS (MP16) and the 7th NMOS tube (MN7) form phase inverter, their grid is connected together, and connect with the drain electrode of the 15 PMOS (MP15), the drain electrode of the 16 PMOS (MP16) and the 7th NMOS tube (MN7) is connected together and connects with the grid of the 8th NMOS tube (MN8), the drain electrode of the 8th NMOS tube (MN8) connects with power supply (VCC), and the source output of the 8th MN8 pipe is to low reference voltage generating circuit (2).
4. a low reference voltage generating circuit, it is characterized in that: described low reference voltage generating circuit comprises first, second equivalent PMOS (MPS1, MPS2), first, second PMOS (MP1, MP2), first, second, 3rd NMOS tube (MN1, MN2, and current-limiting resistance (R2) MN3), first, second, 3rd NMOS tube (MN1, MN2, MN3) substrate and first, second NMOS tube (MN1, MN2) source electrode all connects with ground (VSS), first, second, 3rd NMOS tube (MN1, MN2, MN3) grid connects with the drain electrode of the second NMOS tube (MN2) simultaneously, also the drain electrode of PMOS (MPS1) equivalent with first connects, the source electrode of the 3rd NMOS tube (MN3) is by current-limiting resistance (R2) ground connection (VSS), the drain electrode of the 3rd NMOS tube (MN3) connects with the drain electrode of the second equivalent PMOS (MPS2), the source electrode of first, second equivalent PMOS (MPS1, MPS2) all connects with the drain electrode of the second PMOS (MP2), and the grid of first, second equivalent PMOS (MPS1, MPS2) all connects with ground (VSS), the substrate of first, second equivalent PMOS (MPS1, MPS2) connects, the grid of first, second PMOS (MP1, MP2) connects with the drain electrode of the first PMOS (MP1) and the drain electrode of the first NMOS tube (MN1) simultaneously, and the source electrode of first, second PMOS (MP1, MP2) is all connected with power supply (VCC).
5. low reference voltage generating circuit according to claim 4, it is characterized in that: each equivalent PMOS is formed by many PMOS serial connections, namely the grid of these many PMOS links together simultaneously, as the grid of equivalent PMOS, the substrate of these many PMOS also links together simultaneously, as the substrate of equivalent PMOS; The drain electrode of first PMOS in these many PMOS is as the drain electrode of equivalent PMOS, the source electrode of first PMOS in these many PMOS connects the drain electrode of second PMOS in these many PMOS, the source electrode of second PMOS in these many PMOS connects the drain electrode of the 3rd PMOS in these many PMOS, the like, the source electrode of last PMOS in these many PMOS is as the source electrode of equivalent PMOS.
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| CN105867499B (en) * | 2016-04-22 | 2017-10-10 | 福州福大海矽微电子有限公司 | A kind of circuit and method for realizing reference voltage source low-voltage high-precision |
| CN109491447A (en) * | 2018-12-26 | 2019-03-19 | 湘潭芯力特电子科技有限公司 | A kind of start-up circuit applied to band-gap reference circuit |
| CN117233458B (en) * | 2023-11-10 | 2024-03-19 | 成都明夷电子科技股份有限公司 | Power detection circuit and power detection system |
| CN118131853B (en) * | 2024-05-10 | 2024-07-02 | 上海芯炽科技集团有限公司 | Low-voltage detection protection circuit for band-gap reference state judgment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545977A (en) * | 1992-06-10 | 1996-08-13 | Matsushita Electric Industrial Co., Ltd. | Reference potential generating circuit and semiconductor integrated circuit arrangement using the same |
| CN1264067A (en) * | 1999-01-29 | 2000-08-23 | 三星电子株式会社 | Low-power reference voltage circuit |
| JP2004355523A (en) * | 2003-05-30 | 2004-12-16 | Oki Electric Ind Co Ltd | Constant voltage circuit |
| CN102147632A (en) * | 2011-05-11 | 2011-08-10 | 电子科技大学 | Resistance-free bandgap voltage reference source |
| CN102385407A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Bandgap reference voltage source |
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| FR2834805B1 (en) * | 2002-01-17 | 2004-07-16 | St Microelectronics Sa | CURRENT OR VOLTAGE GENERATOR HAVING A TEMPERATURE STABLE OPERATING POINT |
| TWI365282B (en) * | 2008-01-22 | 2012-06-01 | Feature Integration Technology Inc | Current control apparatus applied to transistor |
-
2014
- 2014-04-17 CN CN201410154983.4A patent/CN103926967B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545977A (en) * | 1992-06-10 | 1996-08-13 | Matsushita Electric Industrial Co., Ltd. | Reference potential generating circuit and semiconductor integrated circuit arrangement using the same |
| CN1264067A (en) * | 1999-01-29 | 2000-08-23 | 三星电子株式会社 | Low-power reference voltage circuit |
| JP2004355523A (en) * | 2003-05-30 | 2004-12-16 | Oki Electric Ind Co Ltd | Constant voltage circuit |
| CN102147632A (en) * | 2011-05-11 | 2011-08-10 | 电子科技大学 | Resistance-free bandgap voltage reference source |
| CN102385407A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Bandgap reference voltage source |
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