CN104166423B - A kind of reference source with compensation in full temperature range characteristic - Google Patents

Abstract

The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind of reference source with compensation in full temperature range characteristic.Reference source of the present invention, comprises electric current source generating circuit, low temperature compensation circuit, high temperature compensation circuit and single order reference source circuit; Wherein, the bias voltage that electric current source generating circuit produces is connected respectively to the first input end of low temperature compensation circuit and the first input end of single order reference source circuit; Second input termination subzero temperature voltage of low temperature compensation circuit, it exports the second input end of termination single order reference source circuit; The positive temperature voltage of input termination of high temperature compensation circuit, it exports the 3rd input end of termination single order reference source circuit; The output terminal output reference voltage of single order reference source circuit.Beneficial effect of the present invention is, has the reference voltage of less temperature coefficient; Because integrated circuit does not use BJT to manage and resistance, chip area is reduced greatly, the overall power of reference source reduces simultaneously.The present invention is particularly useful for reference source.

Description

Reference source with full temperature range compensation characteristic

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a reference source with full-temperature-range compensation characteristics.

Background

Reference sources have become an indispensable part of electronic systems, playing an important role in many applications, especially in high-precision, temperature-independent circuits. Meanwhile, with the continuous development of the functions and the process technology of electronic products, the performance requirements of the electronic products on the reference source are higher and higher. In many electronic systems, the characteristics of the benchmark greatly affect the performance of the overall system. Therefore, a high-performance reference source has an extremely important value, and research on the high-performance reference source is always a hot spot in the field of integrated circuits.

In order to reduce the voltage drift of the reference source in a wide temperature range, various compensation techniques have been proposed, and a compensation method for a non-resistance non-bandgap reference source is not uncommon. For a non-bandgap reference source without resistance, the main factor limiting the temperature characteristic of the reference source is focused on the non-linear temperature characteristic of the mobility. Therefore, it is necessary to eliminate the influence of the nonlinear temperature characteristic of mobility on the reference source to obtain an excellent temperature coefficient.

Disclosure of Invention

The invention aims to provide a full-temperature-range compensation method and a reference source integrating the technology, and the method can realize a smaller temperature coefficient in a wide temperature range.

The invention has the technical scheme that the reference source with the full-temperature-range compensation characteristic comprises a current source generating circuit, a low-temperature compensation circuit, a high-temperature compensation circuit and a first-order reference source circuit; the bias voltage generated by the current source generating circuit is respectively connected to the first input end of the low-temperature compensation circuit and the first input end of the first-order reference source circuit; the second input end of the low-temperature compensation circuit is connected with the negative-temperature voltage, and the output end of the low-temperature compensation circuit is connected with the second input end of the first-order reference source circuit; the input end of the high-temperature compensation circuit is connected with the positive temperature voltage, and the output end of the high-temperature compensation circuit is connected with the third input end of the first-order reference source circuit; the output end of the first-order reference source circuit outputs a reference voltage.

Specifically, the first-order reference source circuit is composed of PMOS transistors M1, M2, M5 and M6, and NMOS transistors M3 and M4; wherein: the grid of the M5 is connected with the grid of the M6 by a bias voltage; the source electrode of the M5 is connected with a power supply voltage; the source of M6 is connected with the power voltage, and the drain is connected with the source of M1 and the source of M2; m4 has its gate and drain interconnected, its drain connected to the drain of M5 and the gate of M1, its source grounded; drain ground potential of M1; m3 has its gate connected to the gate of M4, its drain connected to the interconnection point of the gate and the drain of M2 as the output end of the first-order reference source circuit, and its source connected to the ground potential; the second input end and the third input end of the first-order reference circuit are the same input end; the source connection points of the PMOS tubes M1 and M2 are used as the second and third input ends of the first-order reference circuit;

the high-temperature compensation circuit consists of PMOS tubes M8 and M9 and an NMOS tube M7; wherein, the source of M8 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M7; the gate of M7 is connected with the positive temperature voltage, and the source thereof is connected with the ground potential; the source of M9 is connected with the power voltage, the grid is connected with the grid of M8, and the drain is used as the output end of the high-temperature compensation circuit;

the low-temperature compensation circuit is composed of PMOS tubes M10, M11, M12, M15 and M16, NMOS tubes M17, M18, M19, M20 and M21; wherein, the source of M10 is connected with the power voltage, and the grid is connected with the bias voltage; m17 has its gate and drain interconnected, its drain connected to the drain of M10, and its source at ground potential; m18 with its gate connected to the gate of M17 and its source at ground potential; the source of M11 is connected with the power voltage, and the drain is connected with the drain of M18; the source of M12 is connected with the power supply voltage, the grid is connected with the drain, and the grid is connected with the grid of M11; the grid of M19 is connected with negative temperature voltage, the drain is connected with the drain of M12, and the source is grounded; the grid electrode of M20 is interconnected with the drain electrode, the drain electrode thereof is connected with the interconnection point of the drain electrode of M11 and the drain electrode of M18, and the source electrode thereof is grounded; m21 with its gate connected to the gate of M20 and its source at ground potential; the source of M15 is connected with the power supply voltage, the grid is connected with the drain, and the drain is connected with the drain of M21; the source of M16 is connected to the power supply voltage, its gate is connected to the gate of M15, and its drain is used as the output end of the low temperature compensation circuit.

The method has the advantages that the output of the reference source is compensated at high temperature and low temperature respectively, so that the influence of the nonlinear temperature characteristic of the mobility on the reference source is reduced, and the reference voltage with a smaller temperature coefficient is obtained; the whole circuit does not use BJT (bipolar junction transistor) transistors and resistors, so that the area of a chip is greatly reduced, and most MOS (metal oxide semiconductor) transistors in the circuit work in a sub-threshold region, so that the whole power consumption of the reference source is reduced.

Drawings

FIG. 1 is a schematic diagram of a logic structure of a reference source with full temperature range compensation feature according to the present invention;

FIG. 2 is a schematic diagram of a first-order reference source circuit according to the present invention;

FIG. 3 is a schematic diagram of a high temperature compensation circuit according to the present invention;

FIG. 4 is a schematic diagram of a low temperature compensation circuit according to the present invention;

FIG. 5 is a simplified schematic diagram of a current source generating circuit according to the present invention;

FIG. 6 is a schematic diagram of the high temperature compensation current generation principle of the present invention;

FIG. 7 is a schematic diagram of the low temperature compensation current generation principle of the present invention;

FIG. 8 is a schematic diagram of a full temperature range compensated reference source according to the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples

The full-temperature range compensation method and the reference source architecture integrating the technology are shown in figure 1 and comprise a current source generating circuit, a low-temperature compensation circuit, a high-temperature compensation circuit and a first-order reference source circuit. Bias voltage V generated by current source generating circuit_BThe first input end of the low-temperature compensation circuit and the first input end of the first-order reference source circuit are respectively connected; the second input end of the low-temperature compensation circuit is connected with the negative-temperature voltage V_CTATThe output end of the first-order reference source circuit is connected with the second input end V of the first-order reference source circuit_A(ii) a The input end of the high-temperature compensation circuit is connected with a positive temperature voltage V_PTATThe output end of the first-order reference source circuit is connected with the third input end V of the first-order reference source circuit_A(ii) a The output end of the first-order reference source circuit outputs a reference voltage V_REF。

The first-order reference source circuit is shown in fig. 2, and is composed of 4 PMOS transistors: m1, M2, M5, M6, 2 NMOS transistors: m3 and M4. The specific connection relationship is as follows: the gate of M5 is connected with the gate of M6 by an external bias voltage V_BThe source electrode of the transistor is connected with a power supply voltage VDD; the source of M6 is connected with the power voltage VDD, and the drain is connected with the source of M1 and the source of M2; m4 has its gate and drain interconnected, its drain connected to the drain of M5 and the gate of M1, its source grounded to VSS; drain ground potential VSS of M1; m3 with its gate connected to the gate of M4 and its drain connected to the interconnection point of the gate and drain of M2 as the output V of the first-order reference source circuit_REFThe source thereof is at ground potential VSS.

The high temperature compensation circuit is shown in fig. 3, and is composed of 2 PMOS transistors: m8, M9, 1 NMOS transistor: m7. The specific connection relationship is as follows: the source of M8 is connected with the power supply voltage VDD, the grid is interconnected with the drain, and the drain is connected with the drain of M7; the grid of M7 is connected with an external positive temperature voltage V_PTATThe source thereof is grounded potential VSS; m9 has its source connected to power supply voltage VDD, its gate connected to M8, and its drain as output V of the circuit_A。

The low temperature compensation circuit is composed of 5 PMOS transistors M10, M11, M12, M15, M16, and 5 NMOS transistors M17, M18, M19, M20, and M21, as shown in fig. 4. The specific connection relationship is as follows: m10 has its source connected to power supply voltage VDD and its gate connected to external bias voltage V_B(ii) a M17 has its gate and drain interconnected, its drain connected to the drain of M10, and its source at ground potential VSS; m18 with its gate connected to the gate of M17 and its source at ground potential VSS; the source of M11 is connected with the power voltage VDD, and the drain is connected with the drain of M18; the source of M12 is connected with the power supply voltage VDD, the grid is interconnected with the drain, and the grid is connected with the grid of M11; the grid of M19 is connected with negative temperature voltage V_CTATThe drain of the transistor is connected with the drain of M12, and the source of the transistor is grounded at VSS; m20 has its gate and drain interconnected, its drain connected to the interconnection point of M11 drain and M18 drain, and its source connected to the ground potential VSS; m21 with its gate connected to the gate of M20 and its source at ground potential VSS; the source of M15 is connected with the power supply voltage VDD, the grid is interconnected with the drain, and the drain is connected with the drain of M21; m16 has its source connected to power supply voltage VDD, its gate connected to M15, and its drain as output end of low temperature compensation circuit_REF。

A simple schematic diagram of a current source generating circuit is shown in fig. 5, which generates a positive temperature current I ═ a μ_nT²Wherein A is a constant, mu_nIs the electron mobility, T is the absolute temperature, and then mirrored to the first-order reference source circuit and the low temperature compensation circuit through the M22 transistor. Since the number of methods for realizing the temperature-correcting characteristic current is large, the present invention will not be described in detail herein. Due to the fact that_n＝μ_n0(T/T₀)^-mIn which μ_n0Is T₀The electron mobility at temperature, m (typically 1.5) is the temperature power of the electron mobility, and a typical temperature coefficient for the isothermal current is given by:

$\frac{\∂I}{\∂T}=\frac{1}{2}A\frac{1}{\sqrt{T}}---\left(1\right)$

as shown in fig. 2, the first-order reference source circuit simultaneously generates a positive temperature voltage, a negative temperature voltage, and a positive and negative temperature voltage. In the circuit, M1 and M2 work in a saturation region, and the rest MOS tubes work in a subthreshold region. M1, M2, M3 and M4 form a core circuit of a reference source, and M5 and M6 are used for providing tail current. The subthreshold and saturation region current equations are written as follows:

$I_4={\mathrm{\μ}}_n{C}_{OX}{S}_4{V}_T^2\exp \left(\frac{V_{GS4}-V_{THN}}{{\mathrm{nV}}_T}\right)---\left(2\right)$

$I_i=\frac{1}{2}{\mathrm{\μ}}_p{C}_{OX}{S}_i{(V_{GSi}-V_{THP})}^2---\left(3\right)$

wherein, I_iDenotes a MOS transistor M_iDrain current of (d), mu_nIs the electron mobility, mu_pIs the hole mobility, C_OXIs the capacitance per unit area of the gate oxide, S_iDenotes a MOS transistor M_iN is the subthreshold slope.

According to the connection relationship in FIG. 2, the drain current of the M4 transistor is obtained as

$I_4=I_5=\frac{S_5}{S_{22}}I=A\frac{S_5}{S_{22}}{\mathrm{\μ}}_n{T}^2---\left(4\right)$

The gate-source voltage of the M4 transistor obtained from the formula (2) is as follows

$V_{GS4}=V_{THN}+{\mathrm{nV}}_{T}ln\frac{I_4}{{\mathrm{\μ}}_n{C}_{OX}{V}_T^2{S}_4}---\left(5\right)$

Combining the formulae (4) and (5) gives:

V_GS4＝V_THN+nV_TlnB(6)

wherein,k is the boltzmann constant and q is the electronic charge.

Due to V_TH＝V_TH0-α_VTH(T-T₀) In which V is_TH0Is T₀Threshold voltage at temperature, α_VTHIs a V_THThe temperature coefficient of (a). Gate source voltage V of available M4 tube_GS4The temperature coefficients of (a) and (b) are as follows:

$\frac{\∂V_{GS4}}{\∂T}=-{\mathrm{\α}}_{VTH}+\frac{nk}{q}\ln B---\left(7\right)$

the difference between the gate-source voltages of the M1 tube and the M2 tube is obtained according to the formula (3):

$V_{GS2}-V_{GS1}=\sqrt{\frac{2I_1}{{\mathrm{\μ}}_p{C}_{ox}{S}_1}}-\sqrt{\frac{2I_2}{{\mathrm{\μ}}_p{C}_{ox}{S}_2}}=\sqrt{\frac{2I_1}{{\mathrm{\μ}}_p{C}_{ox}{S}_1}}(1-\sqrt{\frac{I_2{S}_1}{I_1{S}_2}})---\left(8\right)$

let I₁＝aI₂Where a is a constant, then $I_1=\frac{a}{1+a}{I}_6=\frac{a}{1+a}\frac{S_6}{S_{22}}I=A\frac{a}{1+a}\frac{S_6}{S_{22}}{\mathrm{\μ}}_n{T}^2,$ Substituting equation (8) can obtain:

$V_{GS2}-V_{GS1}=C\sqrt{\frac{{\mathrm{\μ}}_n}{{\mathrm{\μ}}_p}}T---\left(9\right)$

wherein,due to the fact that_p＝μ_p0(T/T₀)^-m1Wherein, mu_p0Is T₀Hole mobility at temperature; m1 (typically 1.4) is the temperature power of hole mobility. The temperature coefficient of the difference between the gate-source voltages of M2 and M1 can be obtained as follows:

$\frac{\∂(V_{GS2}-V_{GS1})}{\∂T}=\frac{\∂\left(C\sqrt{\frac{T^{-1.5}}{T^{-1.4}}}T\right)}{\∂T}=\frac{\∂\left(C\sqrt{T^{-0.1}}T\right)}{\∂T}=0.95C\frac{1}{\sqrt[20]{T}}---\left(10\right)$

from the above formula, the temperature coefficient of the difference between the gate and source voltages is positive and decreases with increasing temperature.

According to the connection relationship in FIG. 2, the output voltage V of the first-order reference source can be obtained_REFComprises the following steps:

$V_{REF}=V_{GS4}+V_{GS2}-V_{GS1}=V_{THN}+{\mathrm{nV}}_T\ln B+C\sqrt{\frac{{\mathrm{\μ}}_n}{{\mathrm{\μ}}_p}}T---\left(11\right)$

the temperature coefficient of the reference voltage is as follows:

$\frac{\∂V_{REF}}{\∂T}=-{\mathrm{\α}}_{VTH}+\frac{nk}{q}\ln B+0.95C\frac{1}{\sqrt[20]{T}}---\left(12\right)$

from the above-mentioned reference voltage V_REFAs can be seen from the formula, theoretically, by controlling the temperature coefficient of the positive temperature current I and the width-to-length ratios of M1, M4, M5, M6, and M22, a reference source with a temperature coefficient of "zero" can be obtained. However, since the mobilities of holes and electrons are not completely the same temperature characteristics, the final reference source output voltage can achieve a true zero-temperature characteristic only at a certain temperature point as shown in equation (12). In practice, the waveform of the reference output voltage is as shown by the solid line in fig. 7 as the image before compensation. In order to further reduce the temperature drift of the reference output, the invention provides a full-temperature-range compensation method which is used for reducing the temperature coefficient of the reference voltage.

The high temperature compensation circuit is shown in FIG. 3, in which the gate of the M7 transistor is controlled by PTAT voltage when V is_PTATAs the temperature increases, at a high temperature compensation point T_HA, V_PTAT>V_THNWhen the M7 tube is opened, the current is increased, as shown in FIG. 6, and then passes through the electricity consisting of M8 and M9A flow mirror for mirroring the leakage current of M7 and filling the leakage current into the V of the first-order reference source_ANode to change the magnitude of tail current to make temperature higher than T_HAt times, the difference V between the gate-source voltages of M2 and M1_GS2-V_GS1The temperature coefficient of the reference source increases along with the temperature rise, and the output voltage of the reference source is at T_HThe latter high temperature section is shown in figure 8 with a compensated dotted line.

The low temperature compensation circuit is shown in fig. 4, wherein M17 and M18, M11 and M12, M20 and M21, and M15 and M16 respectively form a current mirror. The grid of M10 is controlled by external bias voltage, the positive temperature current I provided by the current source generating circuit is mirrored, and the positive temperature circuit is obtainedThe grid of M19 is subjected to negative temperature voltage V_CTATControl to obtain a negative temperature current I_CTATBy mirroringNegative temperature current I₁₁With a positive temperature current I₁₈Subtracting, flowing into M20, mirroring via two-stage current mirror, and injecting V of first-order reference source_AAnd the node is used for changing the magnitude of the reference source tail current. As the temperature increases, the leakage current of M16 decreases, at the low temperature compensation point T_LThe leakage current is zero, as shown in fig. 7. Temperature less than T_LAt times, the difference V between the gate-source voltages of M2 and M1_GS2-V_GS1The temperature coefficient of the reference source is reduced along with the temperature rise, and the output voltage of the reference source is at T_LThe effect of the low temperature compensation in the front positive temperature section is shown by the compensated dotted line in fig. 8. In summary, the invention implements a smaller temperature coefficient within a wide temperature range by performing high and low temperature compensation on the first-order resistance-free reference source, the whole circuit does not use BJT and resistor, the chip area is greatly reduced, and most MOS transistors work in a sub-threshold region, so that the overall power consumption of the reference source is reduced.

Claims (1)

1. A reference source with full temperature range compensation characteristic comprises a current source generating circuit, a low temperature compensation circuit, a high temperature compensation circuit and a first-order reference source circuit; the bias voltage generated by the current source generating circuit is respectively connected to the first input end of the low-temperature compensation circuit and the first input end of the first-order reference source circuit; the second input end of the low-temperature compensation circuit is connected with the negative-temperature voltage, and the output end of the low-temperature compensation circuit is connected with the second input end of the first-order reference source circuit; the input end of the high-temperature compensation circuit is connected with the positive temperature voltage, and the output end of the high-temperature compensation circuit is connected with the third input end of the first-order reference source circuit; the output end of the first-order reference source circuit outputs a reference voltage;

the first-order reference source circuit is composed of PMOS tubes M1, M2, M5 and M6, and NMOS tubes M3 and M4; wherein: the grid of the M5 is connected with the grid of the M6 by a bias voltage; the source electrode of the M5 is connected with a power supply voltage; the source of M6 is connected with the power voltage, and the drain is connected with the source of M1 and the source of M2; m4 has its gate and drain interconnected, its drain connected to the drain of M5 and the gate of M1, its source grounded; drain ground potential of M1; m3 has its gate connected to the gate of M4, its drain connected to the interconnection point of the gate and the drain of M2 as the output end of the first-order reference source circuit, and its source connected to the ground potential; the second input end and the third input end of the first-order reference source circuit are the same input end; the source connection points of the PMOS tubes M1 and M2 are used as the second input end and the third input end of the first-order reference source circuit;

the high-temperature compensation circuit consists of PMOS tubes M8 and M9 and an NMOS tube M7; wherein, the source of M8 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M7; the gate of M7 is connected with the positive temperature voltage, and the source thereof is connected with the ground potential; the source of M9 is connected with the power voltage, the grid is connected with the grid of M8, and the drain is used as the output end of the high-temperature compensation circuit;

the low-temperature compensation circuit is composed of PMOS tubes M10, M11, M12, M15 and M16, NMOS tubes M17, M18, M19, M20 and M21; wherein, the source of M10 is connected with the power voltage, and the grid is connected with the bias voltage; m17 has its gate and drain interconnected, its drain connected to the drain of M10, and its source at ground potential; m18 with its gate connected to the gate of M17 and its source at ground potential; the source of M11 is connected with the power voltage, and the drain is connected with the drain of M18; the source of M12 is connected with the power supply voltage, the grid is connected with the drain, and the grid is connected with the grid of M11; the grid of M19 is connected with negative temperature voltage, the drain is connected with the drain of M12, and the source is grounded; the grid electrode of M20 is interconnected with the drain electrode, the drain electrode thereof is connected with the interconnection point of the drain electrode of M11 and the drain electrode of M18, and the source electrode thereof is grounded; m21 with its gate connected to the gate of M20 and its source at ground potential; the source of M15 is connected with the power supply voltage, the grid is connected with the drain, and the drain is connected with the drain of M21; the source of M16 is connected to the power supply voltage, its gate is connected to the gate of M15, and its drain is used as the output end of the low temperature compensation circuit.