CN107436521A - The preparation method of array base palte and its pixel, liquid crystal panel - Google Patents
The preparation method of array base palte and its pixel, liquid crystal panel Download PDFInfo
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- CN107436521A CN107436521A CN201710909023.8A CN201710909023A CN107436521A CN 107436521 A CN107436521 A CN 107436521A CN 201710909023 A CN201710909023 A CN 201710909023A CN 107436521 A CN107436521 A CN 107436521A
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- public electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
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Abstract
The invention provides a kind of array base palte, and it includes：Data wire, gate line and public electrode wire, the data wire and the public electrode wire extend along column direction, the gate line extends along line direction, the data wire and the gate line are arranged in a crossed manner, the public electrode wire and the data wire be arranged in parallel, and the public electrode wire and the gate line not juxtaposition.Present invention also offers a kind of preparation method of pixel of the array base palte and with the array base palte liquid crystal panel.By the present invention in that public electrode wire and gate line not juxtaposition, so as to produce parasitic capacitance between, and then reduce the logic power consumption of display panel.
Description
Technical field
The invention belongs to technical field of liquid crystal display, specifically, is related to the making side of a kind of array base palte and its pixel
Method, liquid crystal panel.
Background technology
With the evolution of photoelectricity and semiconductor technology, the fluffy of flat-panel monitor (Flat Panel Display) has also been driven
The exhibition of breaking out, and in many flat-panel monitors, liquid crystal display (Liquid Crystal Display, abbreviation LCD) is because having
Many advantageous characteristics such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, production life has been applied to it
Various aspects living.
Liquid crystal display generally includes the liquid crystal panel being oppositely arranged and backlight module, wherein because liquid crystal panel can not be sent out
Light, it is therefore desirable to which backlight module provides uniform display light to liquid crystal panel, so that liquid crystal panel shows image.And liquid crystal surface
Plate generally includes array base palte (i.e. Array substrates) and color membrane substrates (i.e. CF substrates).In current array base palte, to pixel
Public electrode provide between the public electrode wire and gate line of common electric voltage can juxtaposition, their cross-lapping department point it
Between the parasitic capacitance that is formed it is larger, so as to which the logic power consumption of display panel can be increased.
The content of the invention
In order to solve the above-mentioned problems of the prior art, it is an object of the invention to provide one kind can eliminate parasitic electricity
The array base palte of appearance and its preparation method of pixel.
According to an aspect of the present invention, there is provided a kind of array base palte, it includes：Data wire, gate line and public electrode
Line, the data wire and the public electrode wire extend along column direction, and the gate line extends along line direction, the data wire with
The gate line is arranged in a crossed manner, and the public electrode wire and the data wire be arranged in parallel, and the public electrode wire with it is described
Gate line not juxtaposition.
Further, the array base palte also includes：Multiple block of pixels, the multiple block of pixels array arrangement, each picture
Plain block includes two pixels arranged along line direction, and the data wire is arranged between the block of pixels, and the gate line is set
Between the block of pixels, the pixel connects with the corresponding data wire and the corresponding gate line, each block of pixels
Two pixels between the public electrode wire is set.
Further, setting a data line between every two adjacent row block of pixels, a data line are adjacent thereto
Two row pixels in each pixel connection.
Further, one of two gate lines, two gate lines and its are set between every two adjacent row block of pixels
The pixel positioned at odd column in adjacent one-row pixels block connects, another a line picture adjacent thereto of two gate lines
The pixel positioned at even column in plain block connects；Or two gate lines are set between every two adjacent row block of pixels, described two
In one of bar gate line one-row pixels block adjacent thereto positioned at even column pixel connect, two gate lines it is another
The pixel positioned at odd column in one-row pixels block adjacent thereto connects.
Further, the pixel includes：Thin film transistor (TFT), pixel electrode, public electrode and liquid crystal, the film crystal
The grid of pipe is connected to corresponding gate line, and the source electrode of the thin film transistor (TFT) or drain electrode are connected to corresponding data wire, described
The drain electrode of thin film transistor (TFT) or source electrode are connected to the pixel electrode, and the pixel electrode is spaced with the public electrode,
The liquid crystal is arranged between the pixel electrode and the public electrode, and the public electrode connects with corresponding public electrode wire
Connect.
According to another aspect of the present invention, a kind of preparation method of the pixel of array base palte described above is additionally provided, its
Including step：Thin film transistor (TFT) and the public electrode wire with the thin film transistor (TFT) interval are formed on substrate；It is brilliant in the film
Pixel electrode is formed in the source electrode of body pipe or drain electrode；Formed and cover thin film transistor (TFT), the public electrode wire and the picture
The insulation material layer of plain electrode；The via of the exposure public electrode wire is formed in the insulation material layer；In the insulation
Public electrode is formed in material layer, the public electrode fills the via to be connected with the public electrode wire.
Further, forming the method for the thin film transistor (TFT) and the public electrode wire includes step：In the substrate
Upper formation grid；Gate insulator is formed on the substrate and the grid；It is formed simultaneously with the gate insulator
Active layer, on the active layer and the source electrode being spaced and drain electrode and the public electrode wire with the active layer interval.
Further, forming the method for the insulation material layer includes step：Formed and cover the thin film transistor (TFT), described
The silicon nitride layer of public electrode wire and the pixel electrode；Form the organic insulation layer for covering the silicon nitride layer.
According to another aspect of the invention, a kind of liquid crystal panel is provided again, and it includes above-mentioned array base palte.
Beneficial effects of the present invention：By the present invention in that public electrode wire and gate line not juxtaposition, so as at the two
Between will not produce parasitic capacitance, and then reduce the logic power consumption of display panel.
Brief description of the drawings
The following description carried out in conjunction with the accompanying drawings, above and other aspect, feature and the advantage of embodiments of the invention
It will become clearer, in accompanying drawing：
Fig. 1 is the structural representation of array base palte according to an embodiment of the invention；
Fig. 2 is the structure top view of the pixel of block of pixels according to an embodiment of the invention；
Fig. 3 is the structural side view of pixel according to an embodiment of the invention；
Fig. 4 is the flow chart of the preparation method of pixel according to an embodiment of the invention.
Embodiment
Hereinafter, with reference to the accompanying drawings to embodiments of the invention are described in detail.However, it is possible to come in many different forms real
Apply the present invention, and the specific embodiment of the invention that should not be construed as limited to illustrate here.Conversely, there is provided these implementations
Example is in order to explain the principle and its practical application of the present invention, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
In the accompanying drawings, in order to understand device, layer and the thickness in region are exaggerated.Identical label is in the accompanying drawings and the description
All the time identical element is represented.
Fig. 1 is the structural representation of array base palte according to an embodiment of the invention.
Reference picture 1, array base palte according to an embodiment of the invention include：Multiple block of pixels 100, a plurality of data lines 200,
A plurality of gate line 300 and a plurality of public electrode wire 400.
Multiple array arrangements of block of pixels 100.Here, each block of pixels 100 includes two pixel PX, the two pixels PX edges
Line direction arranges, but the present invention is not restricted to this.
Data wire 200 and public electrode wire 400 extend along column direction, and gate line 300 extends along line direction.It should manage
Solution, after being rotated by 90 °, data wire 200 and public electrode wire 400 extend along line direction, and gate line 300 is along row side
To extension.
Per setting a data line 200 between two adjacent row block of pixels 100, per two adjacent row block of pixels 100 it
Between set two gate lines 300, and between two pixel PX in each block of pixels 100 set a public electrode wire 400.
So, data wire 200 and public electrode wire 400 be arranged in parallel, and data wire 200 and gate line 300 are arranged in a crossed manner.In addition, by
Between two pixel PX that public electrode wire 400 is provided only in each block of pixels 100, i.e., public electrode wire 400 is arranged at
Within block of pixels 100, and gate line 300 is provided between block of pixels 100, therefore public electrode wire 400 and gate line 300 are not
Juxtaposition, so as to which parasitic capacitance will not be produced between.
In the present embodiment, pixel takes the mode for replacing connection with the connected mode of data wire 200 and gate line 300,
Specifically：Per each pixel PX connections in the two row pixels adjacent thereto of data line 200.That is, per data line
200 are connected with each pixel PX in its left adjacent row pixel, and a row picture adjacent with its right side per data line 200
Each pixel PX connections in element.
For array is per two gate lines 300 between two adjacent row block of pixels 100, wherein a gate line 300 with
The pixel PX connections positioned at odd column in its adjacent one-row pixels block 100, wherein another tuned grid polar curve 300 is adjacent thereto
The pixel PX connections positioned at even column in another row block of pixels 100.That is, gate line 300 above and its phase
The pixel PX connections positioned at odd column in adjacent one-row pixels block 100 above, and underlying gate line 300 and
The pixel PX connections positioned at even column in its adjacent underlying one-row pixels block 100.
Fig. 2 is the structure top view of the pixel of block of pixels according to an embodiment of the invention.
Reference picture 2, each pixel PX include：Thin film transistor (TFT) 110, pixel electrode 120, public electrode 130 and liquid crystal are (not
Show), the grid of thin film transistor (TFT) 110 is connected to corresponding gate line 300, the source electrode of thin film transistor (TFT) 110 or drain electrode connection
To corresponding data wire 200, the drain electrode of thin film transistor (TFT) 110 or source electrode are connected to pixel electrode 120, pixel electrode 120 and public affairs
Common electrode 130 is spaced, and the liquid crystal is arranged between pixel electrode 120 and public electrode 130, public electrode 130 with it is right
The public electrode wire 400 answered connects.
It should be noted that, although public electrode 130 and pixel electrode 120 have been drawn in into same plane in fig. 2, this is
For the ease of showing the two, but pixel electrode 120 is located at the lower section of public electrode 130 in practice, and the two is to each other
Every and insulate, this is described below.
Fig. 3 is the structural side view of pixel according to an embodiment of the invention.Fig. 4 is picture according to an embodiment of the invention
The flow chart of the preparation method of element.
Reference picture 3 and Fig. 4, in step S410, on substrate 1000 formed thin film transistor (TFT) 110 and with the film crystal
The public electrode wire 400 that pipe 110 is spaced.
Specifically, forming thin film transistor (TFT) 110 and the method for public electrode wire 400 includes：
First, grid G is formed on substrate 1000.For example, appropriate thickness is pressed on substrate 1000Gate metal layer (Cr, Mo, Al, Cu etc.) is coated with, the gate metal layer being coated with is patterned
Handle to form grid G.Here, while gate line 300 is also formed, but gate line 300 is not shown in Fig. 3.Gate line 300 with
Grid G connects.
Secondly, gate insulator GI is formed on substrate 1000 and grid G.For example, deposit to form one layer absolutely by PECVD
VelumTo be used as gate insulator GI.
Finally, active layer AL is formed simultaneously with gate insulator GI, on active layer AL and the source S that is spaced
Public electrode wire 400 with drain D and with active layer AL intervals.For example, according to appropriate thicknessIt is logical
PECVD is crossed to deposit to form one layer of active material (a-Si:H), then according to certain thicknessIt is coated with source
Drain metal layer (Cr, Mo, Al, Cu etc.), then using Half Tone Mask to source-drain electrode metal level and active material
Layer carries out patterned process, to be formed simultaneously with active layer AL, source S, drain D and public electrode wire 400.Here, at the same also shape
Data wire 200 is not shown into data wire 200, but in Fig. 3.Data wire 200 is connected with source S or drain D.
After having carried out step S410, step S420 is then carried out.In the step s 420, in the leakage of thin film transistor (TFT) 110
Pixel electrode 120 is formed on the D of pole.It should be noted that pixel electrode can also be formed in the source S of thin film transistor (TFT) 110
120.For example, by appropriate thicknessTransparent electrode material layer (ITO or IZO) is coated with, then to transparent
Electrode material layer carries out patterned process, to form pixel electrode 120.
After having carried out step S420, step S430 is then carried out.In step S430, cover film transistor is formed
110th, the insulation material layer of public electrode wire 400 and pixel electrode 120.
Specifically, forming the method for insulation material layer includes：
First, the silicon nitride layer I1 of cover film transistor 110, public electrode wire 400 and pixel electrode 120 is formed.Example
Such as, deposit to form layer of sin by PECVDxInsulating film layerTo be used as silicon nitride layer I1.
Then, covering silicon nitride layer I1 organic insulation layer I2 is formed.For example, deposit to form one layer by PECVD
Thickness isOrganic insulating film, to be used as organic insulation layer I2.
After having carried out step S430, step S440 is then carried out.In step S440, the shape in the insulation material layer
Into the via GH of exposure public electrode wire 400.For example, the method for dry etching can be used to form via in the insulation material layer
GH。
After having carried out step S440, step S450 is then carried out.In step S450, shape over which layer of insulating material
Into public electrode 130, public electrode 130 fills via GH to be connected with public electrode wire 400.For example, by appropriate thicknessTransparent electrode material layer (ITO or IZO) is coated with, then transparent electrode material layer is carried out at patterning
Reason, to form public electrode 130.
In summary, according to an embodiment of the invention, public electrode wire and gate line not juxtaposition, so as at the two it
Between will not produce parasitic capacitance, and then the logic power consumption of display panel can be reduced.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (9)
- A kind of 1. array base palte, it is characterised in that including：Data wire, gate line and public electrode wire, the data wire and described Public electrode wire extends along column direction, and the gate line extends along line direction, and the data wire and the gate line are arranged in a crossed manner, The public electrode wire and the data wire be arranged in parallel, and the public electrode wire and the gate line not juxtaposition.
- 2. array base palte according to claim 1, it is characterised in that the array base palte also includes：Multiple block of pixels, institute Multiple block of pixels array arrangements are stated, each block of pixels includes two pixels arranged along line direction, and the data wire is arranged at institute Between stating block of pixels, the gate line is arranged between the block of pixels, the pixel and the corresponding data wire and corresponding Gate line connection, the public electrode wire is set between two pixels of each block of pixels.
- 3. array base palte according to claim 2, it is characterised in that a data is set between per two adjacent row block of pixels Line, each pixel connection in a data line two row pixels adjacent thereto.
- 4. the array base palte according to Claims 2 or 3, it is characterised in that two are set between per two adjacent row block of pixels The pixel positioned at odd column in one of gate line, two gate lines one-row pixels block adjacent thereto connects, and described two The pixel positioned at even column in another one-row pixels block adjacent thereto of bar gate line connects；Or one of two gate lines, two gate lines a line adjacent thereto is set between every two adjacent row block of pixels The pixel positioned at even column in block of pixels connects, the position in another one-row pixels block adjacent thereto of two gate lines Connected in the pixel of odd column.
- 5. array base palte according to claim 2, it is characterised in that the pixel includes：Thin film transistor (TFT), pixel electricity Pole, public electrode and liquid crystal, the grid of the thin film transistor (TFT) are connected to corresponding gate line, the source electrode of the thin film transistor (TFT) Or drain electrode is connected to corresponding data wire, the drain electrode of the thin film transistor (TFT) or source electrode are connected to the pixel electrode, the picture Plain electrode is spaced with the public electrode, and the liquid crystal is arranged between the pixel electrode and the public electrode, institute Public electrode is stated to connect with corresponding public electrode wire.
- 6. a kind of preparation method of the pixel of array base palte as claimed in claim 5, it is characterised in that including step：Thin film transistor (TFT) and the public electrode wire with the thin film transistor (TFT) interval are formed on substrate；Pixel electrode is formed on the source electrode of the thin film transistor (TFT) or drain electrode；Form the insulation material layer for covering the thin film transistor (TFT), the public electrode wire and the pixel electrode；The via of the exposure public electrode wire is formed in the insulation material layer；Form public electrode over which layer of insulating material, the public electrode fill the via with the public electrode wire Connection.
- 7. preparation method according to claim 6, it is characterised in that form the thin film transistor (TFT) and the public electrode The method of line includes step：Grid is formed on the substrate；Gate insulator is formed on the substrate and the grid；Active layer is formed simultaneously with the gate insulator, on the active layer and the source electrode that is spaced and drain electrode with And the public electrode wire with the active layer interval.
- 8. preparation method according to claim 6, it is characterised in that forming the method for the insulation material layer includes step Suddenly：Form the silicon nitride layer for covering the thin film transistor (TFT), the public electrode wire and the pixel electrode；Form the organic insulation layer for covering the silicon nitride layer.
- 9. a kind of liquid crystal panel, it is characterised in that including the array base palte described in any one of claim 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710909023.8A CN107436521A (en) | 2017-09-29 | 2017-09-29 | The preparation method of array base palte and its pixel, liquid crystal panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710909023.8A CN107436521A (en) | 2017-09-29 | 2017-09-29 | The preparation method of array base palte and its pixel, liquid crystal panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110596976A (en) * | 2019-08-22 | 2019-12-20 | 武汉华星光电技术有限公司 | Display panel and display device thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237355A (en) * | 2010-04-30 | 2011-11-09 | 瀚宇彩晶股份有限公司 | TFT array substrate and LCD panel |
| CN102346342A (en) * | 2010-08-03 | 2012-02-08 | 乐金显示有限公司 | Liquid crystal display device |
| CN104880873A (en) * | 2015-06-29 | 2015-09-02 | 合肥鑫晟光电科技有限公司 | Pixel structure, display panel and manufacturing method of pixel structure |
| CN105159001A (en) * | 2015-10-20 | 2015-12-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| WO2017133095A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Double-grid array substrate and display device |
-
2017
- 2017-09-29 CN CN201710909023.8A patent/CN107436521A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237355A (en) * | 2010-04-30 | 2011-11-09 | 瀚宇彩晶股份有限公司 | TFT array substrate and LCD panel |
| CN102346342A (en) * | 2010-08-03 | 2012-02-08 | 乐金显示有限公司 | Liquid crystal display device |
| CN104880873A (en) * | 2015-06-29 | 2015-09-02 | 合肥鑫晟光电科技有限公司 | Pixel structure, display panel and manufacturing method of pixel structure |
| CN105159001A (en) * | 2015-10-20 | 2015-12-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| WO2017133095A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Double-grid array substrate and display device |
Non-Patent Citations (2)
| Title |
|---|
| 成都市教育局: "《物理 第3册》", 30 November 1979, 四川人民出版社 * |
| 马群刚: "《TFT-LCD原理与设计》", 31 December 2011, 电子工业出版社 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110596976A (en) * | 2019-08-22 | 2019-12-20 | 武汉华星光电技术有限公司 | Display panel and display device thereof |
| WO2021031372A1 (en) * | 2019-08-22 | 2021-02-25 | 武汉华星光电技术有限公司 | Display panel and display device comprising same |
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Application publication date: 20171205 |