CN103278986A - Array substrate, display device and manufacturing method of array substrate - Google Patents
Array substrate, display device and manufacturing method of array substrate Download PDFInfo
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- CN103278986A CN103278986A CN2013101103335A CN201310110333A CN103278986A CN 103278986 A CN103278986 A CN 103278986A CN 2013101103335 A CN2013101103335 A CN 2013101103335A CN 201310110333 A CN201310110333 A CN 201310110333A CN 103278986 A CN103278986 A CN 103278986A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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Abstract
The invention relates to the display technical field, and discloses an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises an underlayer substrate and a plurality of thin film transistors arranged in an array and further comprises public electrode wires, public electrodes and an insulating layer, wherein the public electrode wires are positioned on the underlayer substrate, the public electrodes are positioned on the underlayer substrate and connected with the public electrode wires, and the insulating layer covers the public electrode wires, the public electrodes and the underlayer substrate. The thin film transistors are positioned on the insulating layer, and scanning lines connected with grids of the thin film transistors in each row are positioned above the public electrode wires. By adoption of the technical scheme, due to the fact that the public electrode wires are positioned below the scanning lines, and the insulating layer is adopted for carrying out insulating between the scanning lines and the public electrode wires, the line width of a black matrix of a color film substrate can be reduced correspondingly, and then an aperture opening ratio and transmittance of a panel are improved.
Description
Technical field
The present invention relates to the display technique field, particularly relate to the manufacture method of a kind of array base palte, display device and array base palte.
Background technology
In panel display apparatus, Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, be called for short TFT-LCD) have that volume is little, low in energy consumption, manufacturing cost is relatively low and characteristics such as radiationless, occupied leading position in current flat panel display market.
At present, the display mode of TFT-LCD mainly contains TN(Twisted Nematic, twisted-nematic) pattern, VA(Vertical Alignment, vertical orientated) pattern, IPS(In-Plane-Switching, the in-plane conversion) pattern and AD-SDS(ADvanced Super Dimension Switch, a senior super dimension switch technology is called for short ADS) pattern etc.
Wherein, the electric field that the electric field that produces by gap electrode edge in the same plane based on the display of ADS pattern and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal work efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, no water of compaction ripple advantages such as (push Mura).
As shown in Figure 1, the TFT-LCD array base-plate structure synoptic diagram of the ADS pattern of prior art, Fig. 1 is vertical view; Fig. 2 is the section structure synoptic diagram of the A-A face of Fig. 1, can see the array base palte inner structure better, as depicted in figs. 1 and 2, its structure comprises: underlay substrate 1, the public electrode 3(that is formed on the underlay substrate 1 is plate electrode), public electrode wire 2 and sweep trace 12(comprise grid 4), wherein, public electrode wire 2 is electrically connected with public electrode 3, also comprise gate insulator 5, active layer 7, data line 11(comprises source electrode 8, drain electrode 9), passivation layer 6, a plurality of pixel electrode 10(are gap electrode).Each array base palte comprises many parallel scanning beams 12 and the data line 11 parallel with vertical many of sweep trace 12, the rectangle region that is intersected to form by data line 11 and sweep trace 12 is called pixel region, a thin film transistor (TFT) is arranged in each pixel region, and delegation's thin film transistor (TFT) is provided with a sweep trace that is connected with the grid of the thin film transistor (TFT) of this row.
As shown in Figure 3, the structural representation of the TFT-LCD liquid crystal cell of prior art ADS pattern, be that color membrane substrates and array base palte are to the structural representation of box, chromatic filter layer 21 in the color membrane substrates is covered in pixel region with chromatic photoresist as filter membranous layer, each chromatic filter layer can see through wherein a kind of light of primary colors of red green blue tricolor, and black matrix 22 need cover on thin film transistor (TFT), sweep trace 12, data line 11 and the public electrode wire 2 in case light leak between each pixel, and can increase trichromatic contrast.
The defective that prior art exists is, because the existence of public electrode wire on the array base palte, black matrix will cover the public electrode wire top on the color membrane substrates, cause the aperture opening ratio of panel and transmitance lower.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of array base palte, display device and array base palte, in order to aperture opening ratio and the transmitance that improves panel, and then the brightness that improves panel.
Array base palte of the present invention comprises also comprising a plurality of thin film transistor (TFT)s of underlay substrate and array arrangement:
Be positioned at the public electrode wire on the described underlay substrate;
Be positioned at the public electrode that is electrically connected with described public electrode wire on the described underlay substrate;
Cover the insulation course of described public electrode wire, public electrode and underlay substrate;
Described a plurality of thin film transistor (TFT) is positioned on the described insulation course, and the sweep trace that is connected with the grid of the described thin film transistor (TFT) of each row is positioned at the top of described public electrode wire.
Preferably, described public electrode is positioned at the both sides of described public electrode wire and is electrically connected with described public electrode wire.
Preferably, the material of described insulation course is silicon nitride.
Preferably, described array base palte also comprises:
Cover the passivation layer of described thin film transistor (TFT);
Be positioned at a plurality of pixel electrodes on the described passivation layer, described pixel electrode is positioned at the top of described public electrode.
Preferably, described pixel electrode is consistent with the material of described public electrode.
Preferably, the material of described public electrode is tin indium oxide.
The invention still further relates to a kind of display device, comprise above-mentioned any described array base palte.
The invention still further relates to a kind of manufacture method of array base palte, comprising:
Formation is positioned at the common electrode layer on the underlay substrate, and forms public electrode by mask composition technology;
Form the public electrode wire that is positioned on the described underlay substrate in the scan line position of setting;
Form the insulation course that covers described public electrode, public electrode wire and underlay substrate;
Form thin film transistor (TFT) at described insulation course.
Preferably, the manufacture method of described array base palte after described insulation course forms thin film transistor (TFT), also comprises:
Formation is positioned at the passivation layer on the described thin film transistor (TFT);
Formation is positioned on the described passivation layer, is positioned at a plurality of pixel electrodes of described public electrode top.
Preferably, in the manufacture method of described array base palte, the material of described insulation course is silicon nitride.
In array base palte of the present invention, because described public electrode wire is positioned at the below of sweep trace, and adopt insulation course to insulate between sweep trace and public electrode wire, therefore, the black matrix of color membrane substrates only covers to the sweep trace top and gets final product, the live width of therefore black matrix can correspondingly reduce, and then has improved panel aperture opening ratio and transmitance.In addition, because the public electrode top has increased by a layer insulating, therefore, can effectively reduce memory capacitance, thereby reduce the duration of charging of pixel, also be beneficial to the product of making high image resolution.
Description of drawings
Fig. 1 is the TFT-LCD array base-plate structure synoptic diagram of prior art ADS pattern;
Fig. 2 is the section structure synoptic diagram of the A-A face of Fig. 1;
Fig. 3 is the structural representation of the TFT-LCD liquid crystal cell of prior art ADS pattern;
Fig. 4 is array base palte one example structure synoptic diagram of the present invention;
Fig. 5 is the section structure synoptic diagram of the B-B face of Fig. 4;
Fig. 6 is the structural representation of liquid crystal cell of the present invention;
Fig. 7 is another example structure synoptic diagram of array base palte of the present invention;
Fig. 8 is the manufacture method schematic flow sheet of array base palte of the present invention.
Reference numeral:
1-underlay substrate 2-public electrode wire 3-public electrode 4-grid 5-gate insulator
6-passivation layer 7-active layer 8-source electrode 9-drain electrode 10-pixel electrode 11-data line
12-sweep trace 13-insulation course 21-chromatic filter layer 22-deceives matrix
Embodiment
In order to improve the panel aperture opening ratio, the invention provides the manufacture method of a kind of array base palte, display device and array base palte.In this technical scheme, because public electrode wire is positioned at the below of sweep trace, therefore, the live width of the black matrix on the color membrane substrates can correspondingly reduce, and then panel aperture opening ratio and transmitance have been improved, and between sweep trace and public electrode wire, adopt insulation course to isolate, effectively reduce memory capacitance, and then shortened the duration of charging of pixel.For making the purpose, technical solutions and advantages of the present invention clearer, below lift specific embodiment the present invention is described in further detail.
As shown in Figure 4, array base palte one example structure synoptic diagram of the present invention, Fig. 5 is the section structure synoptic diagram of the B-B face of Fig. 4, in conjunction with Fig. 4 and shown in Figure 5, array base palte of the present invention comprises also comprising a plurality of thin film transistor (TFT)s of underlay substrate 1 and array arrangement:
Be positioned at the public electrode wire 2 on the underlay substrate 1;
Be positioned at least one public electrode 3 that is electrically connected with public electrode wire 2 on the underlay substrate 1;
Cover the insulation course 13 of public electrode wire 2, public electrode 3 and underlay substrate 1;
Described a plurality of thin film transistor (TFT) is positioned on the insulation course 13, and the sweep trace 12 that is connected with the grid 4 of each row thin film transistor (TFT) is positioned at the top of public electrode wire 2.
In embodiments of the present invention, because public electrode wire 2 is positioned at the below of sweep trace 12, therefore, as shown in Figure 6, liquid crystal cell structure synoptic diagram of the present invention, 22 need of black matrix of corresponding color membrane substrates cover the top of sweep trace 12, and in the prior art, as shown in Figure 1, sweep trace 12 and public electrode wire 2 are arranged in parallel, black matrix 22 need cover the top of sweep trace 12 and public electrode wire 2, therefore, adopts technical scheme of the present invention, (dotted portion among Fig. 6 is the width of the black matrix of prior art in the live width of scan-line direction can to effectively reduce black matrix, as seen the corresponding minimizing of the live width of black matrix of the present invention), improve panel aperture opening ratio and transmitance, and then improved the brightness of panel.In addition, increased by a layer insulating 13 on the public electrode 3, therefore, can effectively reduce memory capacitance, and then reduced the duration of charging of pixel, be beneficial to the manufacturing of high image resolution panel.
Preferably, as shown in Figure 7, the structural representation of another embodiment of array base palte of the present invention, public electrode 3 are positioned at the both sides of public electrode wire 2 and are electrically connected with public electrode wire 2.
In embodiments of the present invention, each bar public electrode wire 2 can be electrically connected with the public electrode 3 of its both sides, can improve the utilization factor of public electrode wire 2, and can reduce the making number of public electrode wire 2.
Preferably, as shown in Figure 5, the material of insulation course 13 is silicon nitride.
In embodiments of the present invention, the material of insulation course 13 can have multiple choices, as long as prevent public electrode wire 2 and sweep trace insulation, so can select multiple insulating material for use, preferred silicon nitride specifically can adopt the method for chemical vapor deposition to form insulation course as insulation course 13.
Preferably, as shown in Figure 5, the array base palte of the embodiment of the invention also comprises:
The transistorized passivation layer 6 of cover film;
Be positioned at a plurality of pixel electrodes 10 on the passivation layer 6, pixel electrode 10 is positioned at the top of public electrode 3.
In embodiments of the present invention, pixel electrode 10 and public electrode 3 are as two pole plates of memory capacitance, and insulation course 13 between the two, gate insulator 5 and passivation layer 6 form memory capacitance as insulating medium.The part of grid 4(sweep trace), gate insulator 5, active layer 7 etc. as shown in Figure 5, described array base palte comprises underlay substrate 1, on the insulation course 13 on the underlay substrate 1, can further comprise:.Described thin film transistor (TFT) can be top gate type, also can be bottom gate type, the array base palte that bottom gate thin film transistor as shown in Figure 5 forms, its structure is specially: sweep trace layer (sweep trace of sweep trace layer comprises grid 4 in each pixel region) is formed on the insulation course 13, gate insulator 5 is formed on the sweep trace layer, active layer 7 is formed on the gate insulator 5, data line layer is formed on the active layer 7, passivation layer 6 covers whole base plate, pixel electrode is formed on the passivation layer 6, be positioned at the top of public electrode 3, and form memory capacitance with public electrode 3.
Preferably, as shown in Figure 6, pixel electrode 10 is consistent with the material of public electrode 3.
In embodiments of the present invention, pixel electrode 10 and public electrode 3 are as the pole plate of memory capacitance, can select for use the material of identical material to make, be preferably nesa coating, because the pixel electrode 10 respective pixel districts of public electrode 3 and top thereof, need higher light transmission rate, therefore can select for use transparent conducting film as its material.
Preferably, the material of public electrode 3 is tin indium oxide.
In embodiments of the present invention, the material of pixel electrode 10 and public electrode 3 can be selected transparent conductive material for use, preferred tin indium oxide, because tin indium oxide has good transmitance and electric conductivity,
The embodiment of the invention also provides a kind of display device, it comprises above-mentioned any one array base palte, described display device can for: liquid crystal panel, Electronic Paper, oled panel, LCD TV, LCD, digital album (digital photo frame), mobile phone, panel computer etc. have product or the parts of any Presentation Function.Display device of the present invention can be TN pattern, VA pattern, IPS pattern or ADS pattern etc.The display device that array base palte of the present invention forms is particularly useful for IPS pattern and ADS pattern.
As shown in Figure 8, the invention still further relates to a kind of manufacture method of array base palte, comprising:
In embodiments of the present invention, at first form public electrode at array base palte, and at the position of the sweep trace of setting formation public electrode wire, public electrode is electrically connected with public electrode wire, public electrode wire can offer common electric voltage of public electrode, above public electrode wire, form sweep trace, so just make sweep trace and public electrode wire be in parallel state up and down, the black matrix of color membrane substrates should be corresponding the width of public electrode wire can reduce, therefore, can improve aperture opening ratio and the transmitance of panel, and then improve the brightness of panel.In addition, need between public electrode wire and the sweep trace to adopt insulation course that both are insulated, therefore, the thickness of the insulating medium between public electrode and pixel electrode increases, reduce memory capacitance, and then shortened the duration of charging of pixel, be conducive to design and the making of high image resolution product.
Preferably, the manufacture method of described array base palte after described insulation course forms thin film transistor (TFT), also comprises:
Formation is positioned at the passivation layer on the described thin film transistor (TFT);
Formation is positioned on the described passivation layer, is positioned at a plurality of pixel electrodes of described public electrode top.
In embodiments of the present invention, the method for making of thin film transistor (TFT) is consistent with prior art, thin film transistor (TFT) can be bottom gate type, also can be for top gate type, if with the public electrode wire design below sweep trace, a plurality of pixel electrodes formation memory capacitance of public electrode and top thereof, because the thickness of the insulating medium of memory capacitance increases, therefore, memory capacitance effectively reduces, and then has reduced the duration of charging of pixel; The material of passivation layer can be elected transparent resin material as, is used for further improving transmitance.
Preferably, in the manufacture method of described array base palte, the material of described insulation course is silicon nitride.
The array base palte of embodiment shown in Fig. 5, its main manufacture craft flow process is as follows:
Form one deck common electrode layer at underlay substrate, can preferably adopt the method for sputtering sedimentation to form, the preferred material of common electrode layer is tin indium oxide, underlay substrate is elected glass substrate as, be specially by sputtering sedimentation and deposit one deck common electrode layer at glass substrate, and by the mask composition technology first time (mask composition technology generally includes cleaning, film forming, coating, exposure, development, does and carve or operations such as wet quarter, photoresist lift off) formation public electrode;
The position of the sweep trace of setting at underlay substrate forms public electrode wire, is specially by sputtering sedimentation one deck public electrode wire layer, and forms the public electrode wire array grid by mask composition technology for the second time in the position of sweep trace correspondence;
Form the insulation course that covers public electrode, public electrode wire and underlay substrate, the material of preferred insulation course is silicon nitride (SiNx), is specially by chemical vapor deposition, exposure, etching, stripping technology, forms one deck silicon nitride dielectric layer;
By traditional handicraft, form sweep trace (comprising grid) at insulation course, thereby and form the gate insulation layer, active layer, source-drain electrode layer, passivation layer and the pixel electrode that cover sweep trace successively by traditional handicraft and finish subsequent technique and finish whole array base palte and make, wherein, the material of pixel electrode can be preferably tin indium oxide, and the material of passivation layer can be preferably silicon nitride.
As seen, sweep trace and public electrode wire are arranged in parallel up and down, make the live width of black matrix reduce, aperture opening ratio and the transmitance of panel have been improved, and owing to made a layer insulating, therefore increased the thickness of the insulating medium between public electrode and pixel electrode, effectively reduced memory capacitance, and then shortened the duration of charging of pixel.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. array base palte comprises it is characterized in that a plurality of thin film transistor (TFT)s of underlay substrate and array arrangement, also comprises:
Be positioned at the public electrode wire on the described underlay substrate;
Be positioned at the public electrode that is electrically connected with described public electrode wire on the described underlay substrate;
Cover the insulation course of described public electrode wire, public electrode and underlay substrate;
Described a plurality of thin film transistor (TFT) is positioned on the described insulation course, and the sweep trace that is connected with the grid of the described thin film transistor (TFT) of each row is positioned at the top of described public electrode wire.
2. array base palte as claimed in claim 1 is characterized in that, described public electrode is positioned at the both sides of described public electrode wire and is electrically connected with described public electrode wire.
3. array base palte as claimed in claim 1 is characterized in that, the material of described insulation course is silicon nitride.
4. array base palte as claimed in claim 1 is characterized in that, also comprises:
Cover the passivation layer of described thin film transistor (TFT);
Be positioned at a plurality of pixel electrodes on the described passivation layer, described pixel electrode is positioned at the top of described public electrode.
5. array base palte as claimed in claim 4 is characterized in that, described pixel electrode is consistent with the material of described public electrode.
6. array base palte as claimed in claim 5 is characterized in that, the material of described public electrode is tin indium oxide.
7. a display device is characterized in that, comprises as each described array base palte in the claim 1～6.
8. the manufacture method of an array base palte is characterized in that, comprising:
Formation is positioned at the common electrode layer on the underlay substrate, and forms public electrode by mask composition technology;
Form the public electrode wire that is positioned on the described underlay substrate in the scan line position of setting;
Form the insulation course that covers described public electrode, public electrode wire and underlay substrate;
Form thin film transistor (TFT) at described insulation course.
9. the manufacture method of array base palte as claimed in claim 8 is characterized in that, after described insulation course forms thin film transistor (TFT), also comprises:
Formation is positioned at the passivation layer on the described thin film transistor (TFT);
Formation is positioned on the described passivation layer, is positioned at a plurality of pixel electrodes of described public electrode top.
10. the manufacture method of array base palte as claimed in claim 8 is characterized in that, the material of described insulation course is silicon nitride.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310110333.5A CN103278986B (en) | 2013-04-01 | 2013-04-01 | The manufacture method of a kind of array base palte, display device and array base palte |
| PCT/CN2013/081835 WO2014161258A1 (en) | 2013-04-01 | 2013-08-20 | Array substrate, display apparatus, and manufacturing method for array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310110333.5A CN103278986B (en) | 2013-04-01 | 2013-04-01 | The manufacture method of a kind of array base palte, display device and array base palte |
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| Publication Number | Publication Date |
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| CN103278986A true CN103278986A (en) | 2013-09-04 |
| CN103278986B CN103278986B (en) | 2015-11-25 |
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Also Published As
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| CN103278986B (en) | 2015-11-25 |
| WO2014161258A1 (en) | 2014-10-09 |
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