CN106849913A - High-performance low-overhead double-node flip online self-recovery latch - Google Patents
High-performance low-overhead double-node flip online self-recovery latch Download PDFInfo
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- 238000005516 engineering process Methods 0.000 abstract description 7
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/00338—In field effect transistor circuits
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Abstract
The invention discloses a high-performance low-overhead double-node overturning online self-recovery latch, which constructs a high-reliability data storage feedback loop through eight groups of mutually-fed C units, can completely tolerate double-node overturning, can realize online self-recovery of double-node overturning, and has high-reliability characteristic. The invention respectively uses less transistor number, clock gating technology and high-speed path technology, reduces area overhead and power consumption overhead, improves circuit performance and has the characteristics of high performance and low overhead. The invention is suitable for integrated circuits and systems with high reliability, and can be widely applied to the fields of space flight and aviation and the like which have high requirements on the cost and reliability of the latch.
Description
Technical field
A kind of binode the present invention relates to high-performance low overhead overturns restoration-online latch, belongs to integrated circuit and resists
Fault-tolerant design field is reinforced in binode upset.
Background technology
With the fast development of ic manufacturing technology, circuit feature size and operating voltage present and constantly decline
Gesture, the logic state of circuit node overturn required for the quantity of electric charge（Critical charge）Also decrease, circuit is easy all the more
Influenceed by particles such as the heavy ion in radiation environment, α particles, neutron and protons and produced soft error.Soft error is a kind of
The instantaneity mistake caused by integrated circuit transient fault under radiation environment.In strong radiation environment, under charge sharing mechanism,
The binode upset that particle shock circuit node is induced is a kind of typical soft error.It is double for single-particle inversion
The failure probability that node upset is caused to integrated circuit is bigger.
Latch is a kind of basic sequential element, is widely used in large-scale integrated circuit and system.There is statistics
As shown by data, under nanometer technology, especially in strong radiation environment, binode upset has become influence latch circuit reliability
Property design subject matter.When latch circuit works long hours in high energy particle and a large amount of intense radiation rings for existing of cosmic ray
In border, it is not sufficient enough only to carry out single-particle inversion Design of Reinforcement, it is necessary to binode upset Design of Reinforcement is carried out to it.Lock
The binode upset Design of Reinforcement of storage, the reliability for improving integrated circuit has great importance.
Anti- binode upset Design of Reinforcement currently for latch is primarily present problems with：One is the presence of fragile section
Point is right, and when each node of the node centering overturns, latch outputs will stay in that the logical value of mistake, it is impossible to real
Now to the tolerance completely of binode upset；Although two is that can realize the tolerance completely to binode upset, exist fragile
Node pair, when each node of the node centering overturns, be will stay in that inside latch mistake logical value and
Do not influence output end, that is, it cannot be guaranteed that all nodes being capable of restoration-online, it is impossible to suitable for the electricity of high reliability demand
Road system；Three is that the expenses such as area, delay, power consumption are larger.
The content of the invention
The purpose of the present invention is to overcome the shortcomings of that existing anti-binode upset is reinforced latch structure and existed, and meets high-performance
Low overhead and highly reliable demand scene, there is provided a kind of binode upset restoration-online latch of high-performance low overhead, pass through
Eight groups of C cells of phase mutual feedback build the restoration-online that high reliability data storage feedback loop realizes binode upset, use
High speed channel, clock gating techniques and fewer number of transistor reduction latch expense, can be widely applied to performance, expense
The every field higher with reliability requirement.
To achieve these goals, the present invention is adopted the following technical scheme that：
Including four transmission gates, eight C cells；Four described transmission gates are followed successively by the first transmission gate（TG1）, the second transmission gate
（TG2）, the 3rd transmission gate（TG3）, the 4th transmission gate（TG4）；Eight described C cells are followed successively by the first C cell（CE1）,
Two clock C cells（CE2-CG）, the 3rd C cell（CE3）, the 4th clock C cell（CE4-CG）, the 5th C cell（CE5）, the 6th
Clock C cell（CE6-CG）, the 7th C cell（CE7）, the 8th clock C cell（CE8-CG）；Contain in each C cell circuit
First signal input part, secondary signal input and signal output part；It is defeated containing the first signal in each clock C cell circuit
Enter end, secondary signal input, clock signal input terminal, inverting clock signal input and signal output part；Wherein, first pass
Defeated door（TG1）Signal input part be this latch data input pin, the first transmission gate（TG1）Signal output part respectively with
First C cell（CE1）Secondary signal input, the 4th clock C cell（CE4-CG）Output end, the 5th C cell（CE5）'s
First signal input part is connected；Second transmission gate（TG2）Signal input part be this latch data input pin, second pass
Defeated door（TG2）Signal output part respectively with the 3rd C cell（CE3）Secondary signal input, the 6th clock C cell（CE6-
CG）Signal output part, the 7th C cell（CE7）The first signal input part be connected；3rd transmission gate（TG3）Signal it is defeated
It is the data input pin of this latch, the 3rd transmission gate to enter end（TG3）Signal output part respectively with the 5th C cell（CE5）'s
Secondary signal input, the 8th clock C cell（CE8-CG）Signal output part, the first C cell（CE1）The first signal input
End is connected；4th transmission gate（TG4）Signal input part be this latch data input pin, the 4th transmission gate（TG4）'s
Signal output part respectively with the 7th C cell（CE7）Secondary signal input, the second clock C cell（CE2-CG）Signal it is defeated
Go out end, the 3rd C cell（CE3）The first signal input part be connected；First C cell（CE1）Signal output part respectively with
Two clock C cells（CE2-CG）Secondary signal input, the 6th clock C cell（CE6-CG）The first signal input part be connected
Connect；Second clock C cell（CE2-CG）Signal output part respectively with the 3rd C cell（CE3）The first signal input part, the 7th
C cell（CE7）Secondary signal input be connected；3rd C cell（CE3）Signal output part it is mono- with the 4th clock C respectively
Unit（CE4-CG）Secondary signal input, the 8th clock C cell（CE8-CG）The first signal input part be connected；4th clock
Control C cell（CE4-CG）Signal output part respectively with the 5th C cell（CE5）The first signal input part, the first C cell
（CE1）Secondary signal input be connected；5th C cell（CE5）Signal output part respectively with the 6th clock C cell
（CE6-CG）Secondary signal input, the second clock C cell（CE2-CG）The first signal input part be connected；6th clock
C cell（CE6-CG）Signal output part respectively with the 7th C cell（CE7）The first signal input part, the 3rd C cell（CE3）
Secondary signal input be connected；7th C cell（CE7）Signal output part respectively with the 8th clock C cell（CE8-CG）
Secondary signal input, the 4th clock C cell（CE4-CG）The first signal input part be connected；8th clock C cell
（CE8-CG）Signal output part respectively with the first C cell（CE1）The first signal input part, the 5th C cell（CE5）Second
Signal input part is connected；8th clock C cell（CE8-CG）Signal output part be this latch data output end；It is described
The first transmission gate（TG1）, the second transmission gate（TG2）, the 3rd transmission gate（TG3）, the 4th transmission gate（TG4）During with identical
Clock.The second described clock C cell（CE2-CG）, the 4th clock C cell（CE4-CG）, the 6th clock C cell（CE6-CG）,
Eight clock C cells（CE8-CG）With identical clock.
The structure situation of C cell is as follows：
The C cell circuit is by the first PMOS MP1, the second PMOS MP2, the first NMOS tube MN1 and the second NMOS tube MN2 groups
Into；Wherein, the grid of the first PMOS MP1 is connected with the grid of the first NMOS tube MN1, and tie point is the of C cell circuit
One signal input part（I1）；The grid of the second PMOS MP2 is connected with the grid of the second NMOS tube MN2, and tie point is C cell
The secondary signal input of circuit（I2）；The drain electrode of the second PMOS MP2 is connected with the drain electrode of the first NMOS tube MN1, connection
Point is the signal output part of C cell circuit（Out）；The drain electrode of the first PMOS MP1 is connected with the source electrode of the second PMOS MP2
Connect；The source electrode of the first NMOS tube MN1 is connected with the drain electrode of the second NMOS tube MN2；Source electrode, first of the first PMOS MP1
The substrate of PMOS MP1, the substrate of the second PMOS MP2 are all connected with power supply（VDD）；Substrate, second of the first NMOS tube MN1
The source grounding of the substrate of NMOS tube MN2, the second NMOS tube MN2.
The structure situation of clock C cell is as follows：
The clock C cell circuit is by the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube
MN1, the second NMOS tube MN2 and the 3rd NMOS tube MN3 are constituted；Wherein, the grid of the first PMOS MP1 and the second NMOS tube MN2
Grid be connected, tie point for clock C cell circuit the first signal input part（I1）；The grid of the second PMOS MP2 with
The grid of the 3rd NMOS tube MN3 is connected, and tie point is the secondary signal input of clock C cell circuit（I2）；3rd PMOS
The drain electrode of pipe MP2 is connected with the drain electrode of the first NMOS tube MN1, and tie point is the signal output part of clock C cell circuit
（Out）；The drain electrode of the first PMOS MP1 is connected with the source electrode of the second PMOS MP2；The drain electrode of the second PMOS MP2 and the
The source electrode of three PMOS MP3 is connected；The source electrode of the first NMOS tube MN1 is connected with the drain electrode of the second NMOS tube MN2；Second
The source electrode of NMOS tube MN2 is connected with the drain electrode of the 3rd NMOS tube MN3；The source electrode of the first PMOS MP1, the first PMOS MP1
Substrate, the substrate of the second PMOS MP2, the substrate of the 3rd PMOS MP3 be all connected with power supply（VDD）；First NMOS tube MN1's
Substrate, the substrate of the second NMOS tube MN2, the substrate of the 3rd NMOS tube MN3, the source grounding of the 3rd NMOS tube MN3.
The invention has the advantages that：
1）High reliability data is built by eight groups of C cells of phase mutual feedback and store feedback loop, be not only able to overturn binode
Tolerated completely, and the restoration-online to binode upset can be realized.
2）Delay, power consumption and area overhead are relatively low.Postponed by high speed channel reduction, improve circuit performance；Use clock
Gating technology reduces electric current competition, reduces power dissipation overhead；Built using fewer number of transistor, reduced area overhead.
Brief description of the drawings
In order to preferably illustrate specific embodiment of the invention and restoration-online principle, below in conjunction with the accompanying drawings to this hair
It is bright to be described further.
Fig. 1 is the binode upset restoration-online latch circuit schematic diagram of high-performance low overhead of the present invention.
Fig. 2 is the circuit theory diagrams of C cell.
Fig. 3 is the symbolic notation of C cell.
Fig. 4 is the truth table of C cell.
Fig. 5 is the circuit theory diagrams of clock C cell.
Fig. 6 is the symbolic notation of clock C cell.
Fig. 7 is the truth table of clock C cell.
Specific embodiment
In order that the purpose of the present invention, technical scheme and beneficial effect are of greater clarity, below in conjunction with the accompanying drawings to this hair
It is bright to be described in detail.It should be appreciated that specific embodiment discussed below is only used for explaining the present invention, it is not used to limit this
Invention.
Binode upset restoration-online latch under high-performance bottom surface product overhead requirements scene provided by the present invention
Circuit theory diagrams are as shown in figure 1, it includes four transmission gates, eight C cells；Four described transmission gates are followed successively by the first transmission
Door（TG1）, the second transmission gate（TG2）, the 3rd transmission gate（TG3）, the 4th transmission gate（TG4）；Eight described C cells are followed successively by
First C cell（CE1）, the second clock C cell（CE2-CG）, the 3rd C cell（CE3）, the 4th clock C cell（CE4-CG）,
Five C cells（CE5）, the 6th clock C cell（CE6-CG）, the 7th C cell（CE7）, the 8th clock C cell（CE8-CG）；Each C
Contain the first signal input part, secondary signal input and signal output part in element circuit；In each clock C cell circuit
It is defeated containing the first signal input part, secondary signal input, clock signal input terminal, inverting clock signal input and signal
Go out end；Wherein, the first transmission gate（TG1）Signal input part be this latch data input pin, the first transmission gate（TG1）'s
Signal output part respectively with the first C cell（CE1）Secondary signal input, the 4th clock C cell（CE4-CG）Output end,
5th C cell（CE5）The first signal input part be connected；Second transmission gate（TG2）Signal input part be this latch
Data input pin, the second transmission gate（TG2）Signal output part respectively with the 3rd C cell（CE3）Secondary signal input,
Six clock C cells（CE6-CG）Signal output part, the 7th C cell（CE7）The first signal input part be connected；3rd transmission
Door（TG3）Signal input part be this latch data input pin, the 3rd transmission gate（TG3）Signal output part respectively with
Five C cells（CE5）Secondary signal input, the 8th clock C cell（CE8-CG）Signal output part, the first C cell（CE1）
The first signal input part be connected；4th transmission gate（TG4）Signal input part be this latch data input pin, the 4th
Transmission gate（TG4）Signal output part respectively with the 7th C cell（CE7）Secondary signal input, the second clock C cell
（CE2-CG）Signal output part, the 3rd C cell（CE3）The first signal input part be connected；First C cell（CE1）Letter
Number output end respectively with the second clock C cell（CE2-CG）Secondary signal input, the 6th clock C cell（CE6-CG）
One signal input part is connected；Second clock C cell（CE2-CG）Signal output part respectively with the 3rd C cell（CE3）
One signal input part, the 7th C cell（CE7）Secondary signal input be connected；3rd C cell（CE3）Signal output part
Respectively with the 4th clock C cell（CE4-CG）Secondary signal input, the 8th clock C cell（CE8-CG）The first signal it is defeated
Enter end to be connected；4th clock C cell（CE4-CG）Signal output part respectively with the 5th C cell（CE5）The first signal it is defeated
Enter end, the first C cell（CE1）Secondary signal input be connected；5th C cell（CE5）Signal output part respectively with
Six clock C cells（CE6-CG）Secondary signal input, the second clock C cell（CE2-CG）The first signal input part be connected
Connect；6th clock C cell（CE6-CG）Signal output part respectively with the 7th C cell（CE7）The first signal input part, the 3rd
C cell（CE3）Secondary signal input be connected；7th C cell（CE7）Signal output part it is mono- with the 8th clock C respectively
Unit（CE8-CG）Secondary signal input, the 4th clock C cell（CE4-CG）The first signal input part be connected；8th clock
Control C cell（CE8-CG）Signal output part respectively with the first C cell（CE1）The first signal input part, the 5th C cell
（CE5）Secondary signal input be connected；8th clock C cell（CE8-CG）Signal output part be this latch data
Output end；The first described transmission gate（TG1）, the second transmission gate（TG2）, the 3rd transmission gate（TG3）, the 4th transmission gate（TG4）
With identical clock.The second described clock C cell（CE2-CG）, the 4th clock C cell（CE4-CG）, the 6th clock C it is mono-
Unit（CE6-CG）, the 8th clock C cell（CE8-CG）With identical clock.
Fig. 2 show the circuit theory diagrams of C cell.The C cell circuit is by the first PMOS MP1, the second PMOS
MP2, the first NMOS tube MN1 and the second NMOS tube MN2 are constituted；Wherein, the grid of the first PMOS MP1 and the first NMOS tube MN1
Grid be connected, tie point for C cell circuit the first signal input part（I1）；The grid and second of the second PMOS MP2
The grid of NMOS tube MN2 is connected, and tie point is the secondary signal input of C cell circuit（I2）；The leakage of the second PMOS MP2
Pole is connected with the drain electrode of the first NMOS tube MN1, and tie point is the signal output part of C cell circuit（Out）；First PMOS
The drain electrode of MP1 is connected with the source electrode of the second PMOS MP2；The drain electrode of the source electrode of the first NMOS tube MN1 and the second NMOS tube MN2
It is connected；The source electrode of the first PMOS MP1, the substrate of the first PMOS MP1, the substrate of the second PMOS MP2 are all connected with power supply
（VDD）；The substrate of the first NMOS tube MN1, the substrate of the second NMOS tube MN2, the source grounding of the second NMOS tube MN2.
Fig. 3 show the symbolic notation of C cell.Fig. 4 show the truth table of C cell.From the table, when the first letter
When number input I1 is identical with secondary signal input I2 logical values, signal output part Out will export the logic opposite with input
Value, now C cell shows as phase inverter；When the first signal input part I1 is different with secondary signal input I2 logical values, letter
Number output end Out enters hold mode, the logical value under output original state.As can be seen here, C cell can be used to masked nodes
Logical value upset, it is to avoid input I1 or I2 logical value upset and propagate to output end Out.
Fig. 5 show the circuit theory diagrams of clock C cell.The clock C cell circuit is by the first PMOS MP1, second
PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2 and the 3rd NMOS tube MN3 composition；Wherein,
The grid of the first PMOS MP1 is connected with the grid of the second NMOS tube MN2, and tie point is the first letter of clock C cell circuit
Number input（I1）；The grid of the second PMOS MP2 is connected with the grid of the 3rd NMOS tube MN3, and tie point is clock C cell
The secondary signal input of circuit（I2）；The drain electrode of the 3rd PMOS MP2 is connected with the drain electrode of the first NMOS tube MN1, connection
Point is the signal output part of clock C cell circuit（Out）；The drain electrode of the first PMOS MP1 and the source electrode phase of the second PMOS MP2
Connection；The drain electrode of the second PMOS MP2 is connected with the source electrode of the 3rd PMOS MP3；The source electrode and second of the first NMOS tube MN1
The drain electrode of NMOS tube MN2 is connected；The source electrode of the second NMOS tube MN2 is connected with the drain electrode of the 3rd NMOS tube MN3；First PMOS
The source electrode of pipe MP1, the substrate of the first PMOS MP1, the substrate of the second PMOS MP2, the substrate of the 3rd PMOS MP3 are all connected with
Power supply（VDD）；The substrate of the first NMOS tube MN1, the substrate of the second NMOS tube MN2, substrate, the 3rd of the 3rd NMOS tube MN3
The source grounding of NMOS tube MN3.
Fig. 6 show the symbolic notation of clock C cell.Fig. 7 show the truth table of clock C cell.From the table,
When latch is in transparent mode, that is, work as clock signal（CLK）It is high level, inverting clock signal（NCK）During for low level, letter
Number output end Out is uncorrelated to the logical value of the first signal input part I1 and secondary signal input I2.When latch is in lock
Pattern is deposited, that is, works as clock signal（CLK）It is low level, inverting clock signal（NCK）During for high level, the table is true with C cell
Value table is of equal value.
The operation principle to latch proposed by the invention is illustrated below, and specific operation principle is as follows：
When CLK be high level, NCK be low level when, the latch be in transparent mode.Now, the first transmission gate TG1, second
Transmission gate TG2 conductings, the 3rd transmission gate TG3 conductings, the 4th transmission gate TG4 conductings.The data input pin D ports input of latch
Data secondary signal input, the 4th clock C cell CE4- of the first C cell CE1 are arrived separately at by the first transmission gate TG1
First signal input part of the signal output part of CG, the 5th C cell CE5；The data of the data input pin D ports input of latch
The letter of the secondary signal input of the 3rd C cell CE3, the 6th clock C cell CE6-CG is arrived separately at by the second transmission gate TG2
Number output end, first signal input part of the 7th C cell CE7.The data of the data input pin D ports input of latch are by the
Three transmission gate TG3 arrive separately at the secondary signal input of the 5th C cell CE5, the signal output of the 8th clock C cell CE8-CG
End（The port that is, the signal output part Q ports of latch）, the first C cell CE1 the first signal input part；The number of latch
According to input D ports be input into data by the 4th transmission gate TG4 arrive separately at the 7th C cell CE7 secondary signal input,
Signal output part, first signal input part of the 3rd C cell CE3 of the second clock C cell CE2-CG.Now, the first C cell
CE1, the 3rd C cell CE3, the 5th C cell CE5, the input signal of the 7th C cell CE7 and output signal all understand.Connect down
Come, the signal output part of the first C cell CE1 arrives separately at secondary signal input, the 6th clock of the second clock C cell CE2-CG
First signal input part of control C cell CE6-CG；The signal output part of the 3rd C cell CE3 arrives separately at the 4th clock C cell
First signal input part of the secondary signal input of CE4-CG, the 8th clock C cell CE8-CG；The signal of the 5th C cell CE5
Output end arrives separately at first letter of the secondary signal input of the 6th clock C cell CE6-CG, the second clock C cell CE2-CG
Number input；The signal output part of the 7th C cell CE7 arrive separately at the 8th clock C cell CE8-CG secondary signal input,
First signal input part of the 4th clock C cell CE4-CG.Now, the input signal and output signal of all C cells all may be used
Know, and the data of the data input pin D ports input of latch directly pass through the signal that the 4th transmission gate TG4 reaches latch
Output end Q ports, reduce propagation delay, improve circuit performance.
When CLK be low level when, NCK be high level when, the latch be in latch mode.Now, the first transmission gate
TG1, the second transmission gate TG2 shut-off, the 3rd transmission gate TG3 shut-offs, the 4th transmission gate TG4 shut-offs；The signal of the first transmission gate TG1
Output end is served as by the signal output part of the 4th clock C cell CE4-CG；The signal output part of the second transmission gate TG2 is by the 6th clock
The signal output part of control C cell CE6-CG serves as；The signal output part of the 3rd transmission gate TG3 is by the 8th clock C cell CE8-CG
Signal output part serve as；The signal output part of the 4th transmission gate TG4 is filled by the signal output part of the second clock C cell CE2-CG
When.Now, the rule that such a is fed back mutually is reached between all of C cell：In the C cell sequence of order cycle arrangement
In { CE1, CE2-CG, CE3, CE4-CG, CE5, CE6-CG, CE7, CE8-CG }, the signal output part of each C cell is anti-
It is fed to the signal input part of next C cell and the 3rd signal input part of C cell of backtracking, and all C cells
First signal input part and secondary signal input are only fed back once.Thus constitute interlocking structure and realize data latch function,
And the data of the 8th clock C cell CE8-CG signal output parts output are the data of latch outputs Q ports output.Separately
On the one hand, due to having used clock gating techniques, signal output part, the 4th clock C of the second clock C cell CE2-CG are reduced
The signal output part of unit CE4-CG, the signal output part of the 6th clock C cell CE6-CG, the 8th clock C cell CE8-CG
The electric current competition of signal output part, power dissipation overhead is relatively low.Further, since the transistor size for using is less, area overhead is relatively low.
The binode upset restoration-online principle to latch proposed by the invention is illustrated below, specific as follows
It is described：
Binode upset occurs under the latch mode of latch, due to the output end of any two C cell under latch mode
The data mode of mouth is all it may happen that upset（Output end only need to be considered because output end all correspondingly to be fed back to other C mono-
The input of unit）, therefore the key node sequence of the latch is { N1, N2, N3, N4, N5, N6, N7, Q }, so as to there is generation double
The situation of node upset amounts to C8 2=28 kinds.As it was earlier mentioned, reaching what such a was fed back mutually between all of C cell
Rule：In the C cell sequence { CE1, CE2-CG, CE3, CE4-CG, CE5, CE6-CG, CE7, CE8-CG } of order cycle arrangement
In, the signal output part of each C cell is fed back to the signal input part of next C cell and the 3rd C of backtracking
The signal input part of unit, and all C cells the first signal input part and secondary signal input only fed back once, plus
Fig. 1 shown in understand, there is symmetry between each C cell in latch.If by between the output end of two neighboring C cell
Distance is denoted as λ, then the distance between output end of any two C cell is only possible to be λ, 2 λ, 3 λ, 4 λ in latch, thus may be used
Choose 4 kinds of exemplary binodes upset nodes to sequence< N1、Q>、< N2、Q>、< N3、Q>、< N4、Q>}.Obviously, sequence
In the distance between the output end of corresponding two C cells be respectively λ, 2 λ, 3 λ, 4 λ, and every other node pair in latch
All with a kind of above-mentioned the of 4 kinds of node centerings it is respectively of equal value.
Below to above-mentioned exemplary binode upset node to sequence< N1、Q>、< N2、Q>、< N3、Q>、< N4、Q>}
In the fault-tolerant principle of each binode upset situation discuss respectively analysis：
Under the influence of by radiated particle strikes, when the signal output part and the 8th clock C cell CE8- of the first C cell CE1
The logic state of the signal output part of CG overturns simultaneously, that is, the secondary signal input of the second clock C cell CE2-CG,
First signal input part of the 6th clock C cell CE6-CG, first signal input part and the 5th C cell of the first C cell CE1
The logic state of the secondary signal input of CE5 overturns.From the truth table of C cell, when certain signal of C cell is defeated
The logic state for entering end overturns, and the logic state of the signal output part of C cell will keep constant, although that is, the second clock
The logic state of certain signal input part of C cell CE2-CG, the 5th C cell CE5 and the 6th clock C cell CE6-CG is turned over
Turn, the logic state of three signal output parts of C cell is still correct.By C cell under previously described latch mode it
Between mutual Feedback Rule understand, the data of the signal output part of the 3rd C cell CE3 and the signal output part of the 7th C cell CE7
Fed back to the signal input part of the 8th clock C cell CE8-CG respectively, that is, the 8th clock C cell CE8-CG signal input
The data at end are correct, it is clear that the logic state of the signal output part of the 8th clock C cell CE8-CG can be believed by it
The correct input signal restoration-online of number input is correct logical value.Again because the signal of the 4th clock C cell is defeated
The logic state for going out end is correct, and now the data of the signal input part of the first C cell CE1 are correct, it is clear that a C
The logic state of the signal output part of unit CE1 can be by the correct input signal restoration-online of its signal input part
Correct logical value.In a word, when the signal output part and the signal output part of the 8th clock C cell CE8-CG of the first C cell CE1
Logic state simultaneously overturn, the latch be capable of will overturn logic state restoration-online be correct logic shape
State.
Under the influence of by radiated particle strikes, when the signal output part and the 8th clock of the second clock C cell CE2-CG
The logic state of the signal output part of control C cell CE8-CG overturns simultaneously, that is, first signal of the 3rd C cell CE3 is defeated
Enter end, first signal input part and the 5th C cell CE5 of the secondary signal input of the 7th C cell CE7, the first C cell CE1
The logic state of secondary signal input overturn.From the truth table of C cell, when certain signal input of C cell
The logic state at end overturns, and the logic state of the signal output part of C cell will keep constant, although that is, the first C cell
CE1, the 3rd C cell CE3, the logic state of certain signal input part of the 5th C cell CE5 and the 7th C cell CE7 are turned over
Turn, the logic state of four signal output parts of C cell is still correct.By C cell under previously described latch mode it
Between mutual Feedback Rule understand, the data of the signal output part of the 3rd C cell CE3 and the signal output part of the 7th C cell CE7
Fed back to the signal input part of the 8th clock C cell CE8-CG respectively, that is, the 8th clock C cell CE8-CG signal input
The data at end are correct, it is clear that the logic state of the signal output part of the 8th clock C cell CE8-CG can be believed by it
The correct input signal restoration-online of number input is correct logical value.Due to now the first C cell CE1 and the 5th C
The logic state of the signal output part of unit CE5 is correct, it is clear that the signal output part of the second clock C cell CE2-CG is patrolled
The state of collecting can be correct logical value by the correct input signal restoration-online of its signal input part.In a word, when
The logic state of the signal output part of two clock C cell CE2-CG and the signal output part of the 8th clock C cell CE8-CG is simultaneously
Overturn, the logic state restoration-online that the latch will can overturn is correct logic state.
Similarly, when the signal output part and the signal output part of the 8th clock C cell CE8-CG of the 3rd C cell CE3
Logic state overturns simultaneously, or when the signal output part and the 8th clock C cell CE8- of the 4th clock C cell CE4-CG
The logic state of the signal output part of CG overturns simultaneously, and it is online from extensive that the latch is equally capable of the logic state that will be overturn
It is again correct logic state.
In sum, the invention provides the binode upset that radiated particle strikes latch circuit in radiation environment triggers
Restoration-online solution, which thereby enhance the reliability of latch circuit.At the same time, due to respectively using fewer
Purpose transistor, clock gating techniques and high speed channel technology, reduce area overhead, power dissipation overhead, improve circuit performance.
The invention is applied to the integrated circuit and system of high reliability, can be widely applied to space flight and aviation etc. to latch expense and reliability
Property require demand field higher.
Claims (3)
1. the binode of high-performance low overhead overturns restoration-online latch, it is characterised in that：Including four transmission gates, eight
C cell；Four described transmission gates are followed successively by the first transmission gate（TG1）, the second transmission gate（TG2）, the 3rd transmission gate（TG3）、
4th transmission gate（TG4）；Eight described C cells are followed successively by the first C cell（CE1）, the second clock C cell（CE2-CG）,
Three C cells（CE3）, the 4th clock C cell（CE4-CG）, the 5th C cell（CE5）, the 6th clock C cell（CE6-CG）, the 7th C
Unit（CE7）, the 8th clock C cell（CE8-CG）；Contain the first signal input part, secondary signal in each C cell circuit
Input and signal output part；In each clock C cell circuit containing the first signal input part, secondary signal input, when
Clock signal input part, inverting clock signal input and signal output part；Wherein, the first transmission gate（TG1）Signal input part
It is the data input pin of this latch, the first transmission gate（TG1）Signal output part respectively with the first C cell（CE1）Second
Signal input part, the 4th clock C cell（CE4-CG）Output end, the 5th C cell（CE5）The first signal input part be connected
Connect；Second transmission gate（TG2）Signal input part be this latch data input pin, the second transmission gate（TG2）Signal it is defeated
Go out end respectively with the 3rd C cell（CE3）Secondary signal input, the 6th clock C cell（CE6-CG）Signal output part,
Seven C cells（CE7）The first signal input part be connected；3rd transmission gate（TG3）Signal input part be this latch number
According to input, the 3rd transmission gate（TG3）Signal output part respectively with the 5th C cell（CE5）Secondary signal input, the 8th
Clock C cell（CE8-CG）Signal output part, the first C cell（CE1）The first signal input part be connected；4th transmission gate
（TG4）Signal input part be this latch data input pin, the 4th transmission gate（TG4）Signal output part respectively with the 7th
C cell（CE7）Secondary signal input, the second clock C cell（CE2-CG）Signal output part, the 3rd C cell（CE3）'s
First signal input part is connected；First C cell（CE1）Signal output part respectively with the second clock C cell（CE2-CG）'s
Secondary signal input, the 6th clock C cell（CE6-CG）The first signal input part be connected；Second clock C cell（CE2-
CG）Signal output part respectively with the 3rd C cell（CE3）The first signal input part, the 7th C cell（CE7）Secondary signal
Input is connected；3rd C cell（CE3）Signal output part respectively with the 4th clock C cell（CE4-CG）Secondary signal
Input, the 8th clock C cell（CE8-CG）The first signal input part be connected；4th clock C cell（CE4-CG）Letter
Number output end respectively with the 5th C cell（CE5）The first signal input part, the first C cell（CE1）Secondary signal input phase
Connection；5th C cell（CE5）Signal output part respectively with the 6th clock C cell（CE6-CG）Secondary signal input,
Two clock C cells（CE2-CG）The first signal input part be connected；6th clock C cell（CE6-CG）Signal output part point
Not with the 7th C cell（CE7）The first signal input part, the 3rd C cell（CE3）Secondary signal input be connected；7th C
Unit（CE7）Signal output part respectively with the 8th clock C cell（CE8-CG）Secondary signal input, the 4th clock C it is mono-
Unit（CE4-CG）The first signal input part be connected；8th clock C cell（CE8-CG）Signal output part respectively with a C
Unit（CE1）The first signal input part, the 5th C cell（CE5）Secondary signal input be connected；8th clock C cell
（CE8-CG）Signal output part be this latch data output end；The first described transmission gate（TG1）, the second transmission gate
（TG2）, the 3rd transmission gate（TG3）, the 4th transmission gate（TG4）With identical clock, the second described clock C cell（CE2-
CG）, the 4th clock C cell（CE4-CG）, the 6th clock C cell（CE6-CG）, the 8th clock C cell（CE8-CG）With identical
Clock.
2. the binode of high-performance low overhead according to claim 1 overturns restoration-online latch, it is characterised in that
The C cell circuit is made up of the first PMOS MP1, the second PMOS MP2, the first NMOS tube MN1 and the second NMOS tube MN2；
Wherein, the grid of the first PMOS MP1 is connected with the grid of the first NMOS tube MN1, and tie point is the first letter of C cell circuit
Number input（I1）；The grid of the second PMOS MP2 is connected with the grid of the second NMOS tube MN2, and tie point is C cell circuit
Secondary signal input（I2）；The drain electrode of the second PMOS MP2 is connected with the drain electrode of the first NMOS tube MN1, and tie point is C
The signal output part of element circuit（Out）；The drain electrode of the first PMOS MP1 is connected with the source electrode of the second PMOS MP2；First
The source electrode of NMOS tube MN1 is connected with the drain electrode of the second NMOS tube MN2；The source electrode of the first PMOS MP1, the first PMOS MP1
Substrate, the substrate of the second PMOS MP2 be all connected with power supply（VDD）；The substrate of the first NMOS tube MN1, the second NMOS tube MN2
The source grounding of substrate, the second NMOS tube MN2.
3. the binode of high-performance low overhead according to claim 1 overturns restoration-online latch, it is characterised in that
The clock C cell circuit is by the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1,
Two NMOS tube MN2 and the 3rd NMOS tube MN3 are constituted；Wherein, the grid of the grid of the first PMOS MP1 and the second NMOS tube MN2
It is connected, tie point is the first signal input part of clock C cell circuit（I1）；The grid and the 3rd of the second PMOS MP2
The grid of NMOS tube MN3 is connected, and tie point is the secondary signal input of clock C cell circuit（I2）；3rd PMOS MP2
Drain electrode be connected with the drain electrode of the first NMOS tube MN1, tie point for clock C cell circuit signal output part（Out）；First
The drain electrode of PMOS MP1 is connected with the source electrode of the second PMOS MP2；The drain electrode of the second PMOS MP2 and the 3rd PMOS MP3
Source electrode be connected；The source electrode of the first NMOS tube MN1 is connected with the drain electrode of the second NMOS tube MN2；The source of the second NMOS tube MN2
Pole is connected with the drain electrode of the 3rd NMOS tube MN3；Substrate, second of the source electrode of the first PMOS MP1, the first PMOS MP1
The substrate of PMOS MP2, the substrate of the 3rd PMOS MP3 are all connected with power supply（VDD）；Substrate, second of the first NMOS tube MN1
The substrate of NMOS tube MN2, the substrate of the 3rd NMOS tube MN3, the source grounding of the 3rd NMOS tube MN3.
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| CN201710022408.2A CN106849913A (en) | 2017-01-12 | 2017-01-12 | High-performance low-overhead double-node flip online self-recovery latch |
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| CN201710022408.2A CN106849913A (en) | 2017-01-12 | 2017-01-12 | High-performance low-overhead double-node flip online self-recovery latch |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
| CN108270429A (en) * | 2018-01-09 | 2018-07-10 | 中国科学院微电子研究所 | Latch of anti two node upset |
| CN109525236A (en) * | 2018-11-26 | 2019-03-26 | 中北大学 | The D-latch of anti-binode upset |
| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN113098449A (en) * | 2021-03-31 | 2021-07-09 | 安徽理工大学 | Three-node overturning self-recovery latch with high robustness |
| CN113726326A (en) * | 2021-07-28 | 2021-11-30 | 南京航空航天大学 | Latch structure tolerant to single-particle double-point upset |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070268054A1 (en) * | 2006-05-18 | 2007-11-22 | Fujitsu Limited | Latch circuit |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN104852722A (en) * | 2015-06-04 | 2015-08-19 | 合肥工业大学 | Self-recovery latch register for preventing single event upset |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
-
2017
- 2017-01-12 CN CN201710022408.2A patent/CN106849913A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070268054A1 (en) * | 2006-05-18 | 2007-11-22 | Fujitsu Limited | Latch circuit |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN104852722A (en) * | 2015-06-04 | 2015-08-19 | 合肥工业大学 | Self-recovery latch register for preventing single event upset |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
Non-Patent Citations (2)
| Title |
|---|
| 方文庆等: "一种低开销的抗SEU锁存器", 《微电子学》 * |
| 黄正峰等: "基于C单元反馈回路的容SEU锁存器设计", 《微电子学》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
| CN108134597B (en) * | 2018-01-08 | 2021-05-25 | 安徽大学 | Latch with three internal nodes completely immune in overturning |
| CN108270429A (en) * | 2018-01-09 | 2018-07-10 | 中国科学院微电子研究所 | Latch of anti two node upset |
| CN108270429B (en) * | 2018-01-09 | 2021-10-15 | 中国科学院微电子研究所 | Latch of anti two node upset |
| CN109525236A (en) * | 2018-11-26 | 2019-03-26 | 中北大学 | The D-latch of anti-binode upset |
| CN109525236B (en) * | 2018-11-26 | 2022-03-08 | 中北大学 | D latch resistant to double-node overturning |
| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111162772B (en) * | 2020-01-15 | 2022-09-20 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN113098449A (en) * | 2021-03-31 | 2021-07-09 | 安徽理工大学 | Three-node overturning self-recovery latch with high robustness |
| CN113098449B (en) * | 2021-03-31 | 2023-11-10 | 安徽理工大学 | High-robustness three-node overturning self-recovery latch |
| CN113726326A (en) * | 2021-07-28 | 2021-11-30 | 南京航空航天大学 | Latch structure tolerant to single-particle double-point upset |
| CN113726326B (en) * | 2021-07-28 | 2023-11-07 | 南京航空航天大学 | Latch structure capable of tolerating single-event double-point overturn |
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