CN109525236B

CN109525236B - D-Latch Resistant to Double Node Toggle

Info

Publication number: CN109525236B
Application number: CN201811417823.9A
Authority: CN
Inventors: 郭靖; 朱磊
Original assignee: North University of China; Qiqihar University
Current assignee: North University of China; Qiqihar University
Priority date: 2018-11-26
Filing date: 2018-11-26
Publication date: 2022-03-08
Anticipated expiration: 2038-11-26
Also published as: CN109525236A

Abstract

A D latch resistant to double-node inversion belongs to the field of anti-nuclear reinforcement in the reliability of integrated circuits. It solves the problems that the existing latch needs a lot of hardware, large area, high power consumption, long propagation delay time, poor ability to resist double-node inversion and inability to realize fault tolerance to dual-node inversion. The present invention includes 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1 to P12, and uses few devices, small size and simple structure. Because of the few devices used, the power consumption of the entire latch is reduced and the hardware overhead is low. . The signal at the input end of the latch can be transmitted to the output port through only one transmission gate. The data transmission time is short, and it can also realize fault tolerance to any single-node and double-node flipping, so as to realize fault-tolerant protection against single-node and double-node flipping. The present invention is especially suitable for the nuclear radiation effect in aerospace, aerospace flight, nuclear power plant and the like.

Description

D latch resistant to double-node overturning

Technical Field

The invention belongs to the field of anti-nuclear reinforcement in the reliability of integrated circuits.

Background

D-latches are widely used in various digital integrated circuits, such as decoders and timing control circuits. However, since the latch has a function of holding information, the radiation particle will change the information held by the latch, thereby causing an error in the electronic system.

The existing latch generally uses a triple modular redundancy or even more modular redundancy mode to achieve the purpose of resisting the interference of external radiation particles, but the existing latch needs more hardware (up to 102 transistors), has a large area, high power consumption and long propagation delay time, and although the dual-node flip resistance can be achieved, the dual-node flip resistance is poor, and even the dual-node flip fault tolerance cannot be achieved, so the above problems need to be solved urgently.

Disclosure of Invention

The invention provides a novel double-node turnover resistant D latch, aiming at solving the problems of more required hardware, large area, high power consumption, long propagation delay time, poor double-node turnover resistant capability and incapability of realizing fault tolerance of double-node turnover in the conventional latch.

A D latch resisting double node turnover, comprising 20 NMOS transistors N1-N20, 12 PMOS transistors P1-P12;

the sources of the transistors P1-P6 are all connected with a power supply; the sources of the transistors N1-N6 are all connected to the power ground;

the drain of the transistor P1, the source of the transistor P7, the gate of the transistor P6, and the gates of the transistors N17 and N19 are connected together to form a node X6; the gate of the transistor P1, the gate of the transistor N18, the gate of the transistor N20, the drain of the transistor P6, and the source of the transistor P8 are connected at the same time and then form a node X5; the gate of the transistor P7, the source of the transistor N17, the drain of the transistor N2, and the gate of the transistor P3 are connected together to form a node X1; the drain of the transistor P7 is connected to the drain of the transistor N7, the gate of the transistor N7 is connected to the node X4, the source of the transistor N7 is connected to the drain of the transistor N1, and the gate of the transistor N1 is connected to the node X2;

the gate of the transistor P2, the source of the transistor N20, the gate of the transistor P8, the drain of the transistor N5, and the gate of the transistor N4 are connected together to form a node X4; the drain of the transistor P2 is connected to the drain of the transistor N17, the drain of the transistor N2 is connected to the gate of the transistor N5, and the gate of the transistor N2, the source of the transistor N18, the drain of the transistor N3, and the gate of the transistor P4 are connected together to form a node X2;

the drain of the transistor P3 is connected to the drain of the transistor N18, and the gate of the transistor N3, the source of the transistor N19, the drain of the transistor N4, and the gate of the transistor P5 are simultaneously connected to form a node X3;

the drain of the transistor P4 is connected to the drain of the transistor N19;

the drain of the transistor P5 is connected to the drain of the transistor N20;

the drain of the transistor P8 is connected to the drain of the transistor N8; the source of the transistor N8 is connected to the drain of the transistor N6; the gate of transistor N8 is taken as node X1; the gate of transistor N6 is taken as node X3;

sources of the transistors N10 to N13 serve as nodes X1 to X4, respectively; the gates of the transistors N9-N13 and the gate of the transistor P11 are connected together and used as the input terminal of the latch clock signal CLK; the drain of the transistor N10, the drain of the transistor N12, the source of the transistor P12 and the drain of the transistor N9 are connected together and then serve as input terminals of a latch data signal D; the drain of the transistor N11 is connected to the drain of the transistor N13 and serves as the input terminal of the latch data signal DN;

the source electrode of the transistor P9 is connected with a power supply; the gate of the transistor P9 and the gate of the transistor N15 are connected to each other to serve as a node X4; the drain of the transistor P9 is connected to the source of the transistor P10; the gate of the transistor P10 is connected to the drain of the transistor N16 to serve as a node X2; the drain of the transistor P10 is connected to the source of the transistor P11; the drain electrode of the transistor P11, the drain electrode of the transistor N14, the drain electrode of the transistor P12 and the source electrode of the transistor N9 are connected at the same time and then are used as the output end of the latch output signal Q; the gate of the transistor N14 is connected to the gate of the transistor P12 and serves as the input terminal of the latch clock signal CLKN; the source of the transistor N14 is connected with the drain of the transistor N15, the source of the transistor N15 is connected with the drain of the transistor N16, and the source of the transistor N16 is connected with the power ground;

the data signal D received at the input of the latch data signal D is the inverse of the data signal DN received at the input of the latch data signal DN, and the clock signal CLKN received at the input of the latch clock signal CLKN is the inverse of the clock signal CLK received at the input of the latch clock signal CLK.

Preferably, when the clock signal CLK is at a high level "1", the latch is turned on; when the clock signal CLK is at low level "0", the latch latches.

Preferably, when the latch latches a low level "0", the sensitive nodes of the latch are X2, X4, X6;

when the latch latches a high level "1", the sensitive nodes of the latch are X1, X3, X5.

Preferably, the D latch resisting double-node upset comprises a normal operating state and a fault-tolerant operating state.

The normal working state comprises the following conditions:

the first condition is as follows: assuming that the data signal D is 1, DN is 0;

(1) when CLK is equal to 1, CLKN is equal to 0, NMOS transistors N10 to N13 are turned on, NMOS transistors N3, N5, N6, N8 are turned on, and NMOS transistors N1, N2, N4, N7 are turned off; PMOS transistors P1, P2, P4, P8 are turned on, and PMOS transistors P3, P5, P6, P7 are turned off, which will result in node X5 being 0 and X6 being 1; then, NMOS transistors N17 and N19 will be turned on, and NMOS transistors N18 and N20 will be turned off, at which time, X1 ═ X3 ═ X6 ═ 1, X2 ═ X4 ═ X5 ═ 0, NMOS transistor N9 and PMOS transistor P12 are turned on, and PMOS transistors P9 and P10 are also turned on, while NMOS transistors N15 and N16 are turned off, and since NMOS transistor N14 and PMOS transistor P14 are turned off, the latch output signal Q is 1;

(2) when CLK is equal to 0, CLKN is 1, the latch enters a latch state, at this time, NMOS transistors N9 to N13 are turned off, PMOS transistor P11 is turned on, and at this time, the output end of the latch output signal Q is directly connected to the power supply through the turned-on PMOS transistors P9 to P11, and the output signal Q is latched all the time because of the latch inside;

case two: assuming that the data signal D is 0, DN is 1;

(1) when CLK is equal to 1, CLKN is equal to 0, at this time, NMOS transistors N10 to N13 are turned on, NMOS transistors N1, N2, N4, N7 are turned on, and NMOS transistors N3, N5, N6, N8 are turned off; PMOS transistors P3, P5, P6, P7 are turned on, and PMOS transistors P1, P2, P4, P8 are turned off, which will result in node X5 being 1 and X6 being 0, then NMOS transistors N18 and N20 being turned on, NMOS transistors N17 and N19 being turned off, and thus X1 being X3 being X6 being 0, X2 being X4 being X5 being 1, NMOS transistor N9 and PMOS transistor P12 being turned on, and NMOS transistors N15 and N16 being turned on, and PMOS transistors P9 and P10 being turned off, and since NMOS transistor N14 and PMOS transistor P14 are turned off, output signal Q being 0;

(2) when CLK is equal to 0, CLKN is equal to 1, the latch enters a latch state, at this time, NMOS transistors N9-N13 are turned off, and NMOS transistor N14 is turned on, at this time, the output terminal of the latch output signal Q is directly connected to the power ground through the turned-on NMOS transistors N14-N16, and the output signal Q is equal to 0 because of latch inside the latch.

Fault tolerant operating conditions occur during latching of the latch, including the following:

the first condition is as follows:

when the latch latches low level '0', the sensitive nodes of the latch are X2, X4 and X6, and when any one or two of the sensitive nodes are overturned, because the states of the sensitive nodes which are not overturned and two or more than two nodes in the nodes X1, X3 and X5 are always kept unchanged, the overturned one or two nodes can be restored to the original states;

case two:

when the latch latches high level '1', the sensitive nodes of the latch are X1, X3 and X5, and when any one or two of the sensitive nodes are overturned, because the states of the sensitive nodes which are not overturned and two or more than two nodes in the nodes X2 and X4 always remain unchanged, the overturned one or two nodes can be restored to the original states.

Principle analysis:

the fault-tolerant operating state is independent of the data signal D received by the input end of the latch data signal D, the state occurs in the latch latching state of the latch and is related to the data latched by each node in the latch, and the fault-tolerant operating state of the D latch resisting double-node overturning is analyzed as follows: when the clock signal CLK is 0, CLKN is 1, 6 internal nodes X1, X3, X6, X2, X4, X5 are 0, the output signal Q is 1, there are 3 internal sensitive nodes of the latch at this time, which are X1, X3, and X5, respectively, and the specific case when one or two of the 3 sensitive nodes are flipped is as follows:

1. when the node X1 is flipped to 0, the PMOS transistors P3 and P7 will be turned on, but since the NMOS transistors N18, N4, N2 are turned off, the other nodes will not be affected and remain in the original state. Therefore, the NMOS transistor N17 and the PMOS transistor P2 will be always turned on, so the node X1 will be pulled back to the original 1 state, and the state of the output signal Q will not change.

2. When the node X3 is bombarded and overturned, the NMOS transistor N6 is closed, the PMOS transistor P5 is opened, and the node X5 is kept unchanged, so that the NMOS transistor N20 is always in a closed state, the node X4 is not influenced, and the node X3 can be pulled back to the original state because the PMOS transistor P4 and the NMOS transistor N19 are always in an open state, and the state of the output signal Q is not changed.

3. When node X5 is bombarded to become 1, which will cause NMOS transistors N18 and N20 to turn on temporarily, while PMOS transistor P1 will be turned off temporarily, the state of node X6 remains unchanged, so that NMOS transistors N17 and N19 will always turn on. However, since the states of the nodes X1 to X4 are not changed, the NMOS transistors N6 and N8 and the PMOS transistor P8 are always turned on. Therefore, node X5 will be pulled back down to 0 and the state of the output signal Q will not change.

4. When the states of the nodes X1 and X3 change, the NMOS transistors N6 and N8 are turned off, and the PMOS transistors P3 and P5 are turned on, but since the states of the nodes X5 and X6 do not change, the states of the NMOS transistors N17 to N20 do not change, and as a result, the states of the nodes X2 and X4 do not change, which causes the PMOS transistors P2 and P4 to be turned on all the time, and therefore, the states of the nodes X1 and X3 are restored to the original 1 state, and the state of the output signal Q does not change.

5. When the states of the nodes X1 and X5 change, the NMOS transistors N8 and N5 are turned off, the PMOS transistors P3 and P7 are turned on, the NMOS transistors N18 and N20 are turned on temporarily, and the PMOS transistor P1 is turned off temporarily, so that the state of the node X6 remains unchanged, so that the NMOS transistors N17 and N19 are turned on all the time, but since the state of the node X4 does not change, the PMOS transistor P2 is turned on all the time, the node X1 is pulled back to 1, the NMOS transistor N8 is turned on, the node X5 is pulled back to 0 by the turned on NMOS transistors N6 and N8 and the turned P8, and finally the state of the output signal Q does not change.

6. When the states of the nodes X3 and X5 change, the NMOS transistors N3 and N6 are turned off, the PMOS transistor P5 is turned on, the NMOS transistors N18 and N20 are turned on temporarily, and the PMOS transistor P1 is turned off temporarily, so that the state of the node X6 remains unchanged, so that the NMOS transistors N17 and N19 are turned on all the time, but since the state of the node X2 does not change, the PMOS transistor P4 is turned on all the time, the node X3 is pulled back to the original 1, the NMOS transistor N6 is turned on, and the node X5 is pulled back to 0 by the turned on NMOS transistors N6 and N8 and the PMOS transistor P8, so that the state of the output signal Q does not change.

In summary, when one or two of the 3 sensitive nodes flip, it can be found through the above analysis that two or more nodes always have no change, and the state of these flips can be recovered through the saved values.

The invention is designed to be reinforced according to the physical characteristics generated by the radiation particle bombarding semiconductor device, therefore, the number of the nodes of the latch is 6, namely X1, X2, X3, X4, X5 and X6, but according to the latched value, the invention reduces the number of the sensitive nodes in the latch to 3, reduces the sensitive area, causes the probability of being bombarded by the radiation particle to be reduced, and compared with the existing latch, the area, the power consumption and the delay of the latch are greatly reduced.

The invention has the advantages that,

(1) the latch comprises 32 transistors, uses few devices, has small volume and simple structure, reduces the power consumption of the whole latch due to the few devices, and has lower hardware expense.

(2) In the present invention, the signal at the input terminal can be transmitted to the output port through only one transmission gate (i.e., the latch is in the on state, the input terminal of the latch data signal D and the output terminal of the latch output signal Q are directly connected through the transmission gate formed by the transistor N9 and the transistor P12), and therefore, the delay thereof is also reduced.

(3) The existing latch generally needs to be combined with layout to achieve good anti-overturning capability, the invention does not need to be matched with layout optimization, and any single node or double node in the latch can be recovered after overturning, so that the single-node and double-node overturning resistant capability of the latch is improved.

The invention is especially suitable for aerospace, aerospace flight, nuclear power station and other nuclear radiation effects.

Drawings

FIG. 1 is a schematic diagram of a dual-node flip-flop resistant D-latch according to the present invention;

FIG. 2 is a simulation diagram of the D-latch of the present invention for resisting double node flip.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, the D latch with dual-node flip-flop resistance according to this embodiment includes 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1 to P12;

the drain of the transistor P4 is connected to the drain of the transistor N19;

the drain of the transistor P5 is connected to the drain of the transistor N20;

The D latch with double node flip resistance described in this embodiment has two data input terminals, two clock signal input terminals, and one signal output terminal.

Referring to fig. 1, the preferred embodiment is described, in which when the clock signal CLK is high level "1", the latch is turned on (the input terminal of the latch data signal D is directly connected to the output terminal of the latch output signal Q through the transmission gate formed by the transistor N9 and the transistor P12); when the clock signal CLK is at low level "0", the latch latches.

Although the number of the nodes of the latch is 6, namely X1, X2, X3, X4, X5 and X6, the number of the sensitive nodes of the latch is reduced to 3 according to the latched value:

when the latch latches a low level '0', sensitive nodes of the latch are X2, X4 and X6;

Referring to fig. 1, the preferred embodiment is described, in which the D latch against double node flipping includes a normal operating state and a fault-tolerant operating state.

The (first) normal working state comprises the following conditions:

(2) when CLK is equal to 0, CLKN is 1, the latch enters a latch state, at this time, NMOS transistors N9 to N13 are turned off, PMOS transistor P11 is turned on, and at this time, the output end of the latch output signal Q is directly connected to the power supply through the turned-on PMOS transistors P9 to P11, and because of the latch inside, the output signal Q is always latched and is not affected by the change of the input signal D;

case two: assuming that the data signal D is 0, DN is 1;

(2) when CLK is equal to 0, CLKN is equal to 1, the latch enters a latch state, at this time, NMOS transistors N9-N13 are turned off, NMOS transistor N14 is turned on, and at this time, the output end of the latch output signal Q is directly connected to the power ground through the turned-on NMOS transistors N14-N16, and the latch is internally latched, so that the output signal Q is always latched and is not affected by the change of the input signal D.

(II) fault-tolerant operating states occur during latching of the latch, including the following:

the first condition is as follows:

case two:

And (3) verification test: referring specifically to fig. 2, a simulation diagram of the dual-node flip-flop resistant D latch of the present invention is shown in fig. 2, and through the simulation diagram, it can be seen that the timing function and the fault tolerance function of the dual-node flip-flop resistant D latch constructed by the present invention are correct. For example, during the time from 25ns to 65ns, the nodes X1, X3 and X5 and the double nodes X1-X3, X1-X5 and X3-X5 are respectively turned over, and all the nodes are turned over from the original state to the opposite state, but all the nodes can be finally restored to the original respective states, so that the fault tolerance of double-node turning is realized.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. The D latch that resists double node inversion, is characterized in that, comprises 20 NMOS transistors N1 to N20, 12 PMOS transistors P1 to P12;

The sources of the transistors P1 to P6 are all connected to the power supply; the sources of the transistors N1 to N6 are all connected to the power ground;

The drain of the transistor P1, the source of the transistor P7, the gate of the transistor P6, and the gates of the transistors N17 and N19 are connected at the same time as the node X6; the gate of the transistor P1, the gate of the transistor N18, and the gate of the transistor N20 After the pole, the drain of the transistor P6 and the source of the transistor P8 are connected at the same time, it is used as the node X5; the gate of the transistor P7, the source of the transistor N17, the drain of the transistor N2 and the gate of the transistor P3 are connected at the same time. X1; the drain of transistor P7 is connected to the drain of transistor N7, the gate of transistor N7 is used as node X4, the source of transistor N7 is connected to the drain of transistor N1, and the gate of transistor N1 is used as node X2;

The gate of transistor P2, the source of transistor N20, the gate of transistor P8, the drain of transistor N5 and the gate of transistor N4 are connected at the same time as node X4; the drain of transistor P2 is connected to the drain of transistor N17, the transistor The drain of N2 is connected to the gate of transistor N5, and the gate of transistor N2, the source of transistor N18, the drain of transistor N3 and the gate of transistor P4 are connected at the same time as node X2;

The drain of the transistor P3 is connected to the drain of the transistor N18, and the gate of the transistor N3, the source of the transistor N19, the drain of the transistor N4 and the gate of the transistor P5 are connected simultaneously to serve as the node X3;

The drain of transistor P4 is connected to the drain of transistor N19;

The drain of the transistor P5 is connected to the drain of the transistor N20;

The drain of transistor P8 is connected to the drain of transistor N8; the source of transistor N8 is connected to the drain of transistor N6; the gate of transistor N8 is used as node X1; the gate of transistor N6 is used as node X3;

The sources of the transistors N10 to N13 are used as nodes X1 to X4 respectively; the gates of the transistors N9 to N13 and the gate of the transistor P11 are connected at the same time as the input terminals of the latch clock signal CLK; the drain of the transistor N10, the transistor After the drain of N12, the source of transistor P12 and the drain of transistor N9 are connected at the same time, they serve as the input terminal of the latch data signal D; after the drain of transistor N11 and the drain of transistor N13 are connected, they serve as latch data the input of the signal DN;

The source of the transistor P9 is connected to the power supply; the gate of the transistor P9 is connected to the gate of the transistor N15 as a node X4; the drain of the transistor P9 is connected to the source of the transistor P10; the gate of the transistor P10 is connected to the drain of the transistor N16 After the pole is connected, it is used as node X2; the drain of transistor P10 is connected to the source of transistor P11; the drain of transistor P11, the drain of transistor N14, the drain of transistor P12 and the source of transistor N9 are connected at the same time, as a lock The output terminal of the register output signal Q; the gate of the transistor N14 is connected to the gate of the transistor P12, and it is used as the input terminal of the latch clock signal CLKN; the source of the transistor N14 is connected to the drain of the transistor N15. The source is connected to the drain of the transistor N16, and the source of the transistor N16 is connected to the power ground;

The data signal D received by the input terminal of the latch data signal D is opposite to the data signal DN received by the input terminal of the latch data signal DN, and the clock signal CLKN received by the input terminal of the latch clock signal CLKN and the latch clock The input of the signal CLK receives the opposite clock signal CLK.

2. The D latch of claim 1, wherein when the clock signal CLK is a high level "1", the latch is turned on; the clock signal CLK is a low level "0" ”, the latch latches.

3. The D latch of anti-dual node inversion according to claim 1 or 2, is characterized in that,

When the latch latches a low level "0", the sensitive nodes of the latch are X2, X4, and X6;

When the latch latches a high level "1", the sensitive nodes of the latch are X1, X3, and X5.

4 . The D latch of claim 1 , characterized in that it includes a normal working state and a fault-tolerant working state. 5 .

5. The D latch of anti-dual node inversion according to claim 4, is characterized in that, the normal working state comprises the following situation:

Case 1: Assuming that the data signal D=1, then DN=0;

(1) When CLK=1, CLKN=0, NMOS transistors N10 to N13 are turned on, NMOS transistors N3, N5, N6, N8 are turned on, NMOS transistors N1, N2, N4, N7 are turned off; PMOS transistors P1, P2, P4, P8 is turned on, and PMOS transistors P3, P5, P6, P7 are turned off, which will cause node X5 = 0, X6 = 1; then, NMOS transistors N17 and N19 will be turned on, NMOS transistors N18 and N20 will be turned off, at this time, X1 = X3=X6=1, X2=X4=X5=0, NMOS transistor N9 and PMOS transistor P12 are turned on, and PMOS transistors P9 and P10 are also turned on, while NMOS transistors N15 and N16 are turned off, since NMOS transistor N14 and PMOS transistor P14 are turned off , therefore, the latch output signal Q=1;

(2) When CLK=0, CLKN=1, the latch enters the latching state. At this time, the NMOS transistors N9 to N13 are turned off, and the PMOS transistor P11 will be turned on. At this time, the output terminal of the latch output signal Q will directly Connect to the power supply through the turned-on PMOS transistors P9 to P11, because the latch is internally latched, the output signal Q=1 will always be latched;

Case 2: Assuming that the data signal D=0, then DN=1;

(1) When CLK=1, CLKN=0, at this time, NMOS transistors N10 to N13 are turned on, NMOS transistors N1, N2, N4, N7 are turned on, NMOS transistors N3, N5, N6, N8 are turned off; PMOS transistors P3, P5 , P6, P7 are on, and PMOS transistors P1, P2, P4, P8 are off, this will cause nodes X5 = 1, X6 = 0, then, NMOS transistors N18 and N20 will be on, NMOS transistors N17 and N19 will be off, so, X1=X3=X6=0, X2=X4=X5=1, NMOS transistor N9 and PMOS transistor P12 are turned on, and NMOS transistors N15 and N16 are turned on, while PMOS transistors P9 and P10 are turned off, since NMOS transistor N14 and PMOS transistor P14 is closed, so the output signal Q=0;

(2) When CLK=0, CLKN=1, the latch enters the latching state. At this time, the NMOS transistors N9-N13 are turned off, and the NMOS transistor N14 will be turned on. At this time, the output terminal of the latch output signal Q will directly Through the NMOS transistors N14 to N16 being turned on and connected to the power ground, since the latch is internally latched, the output signal Q=0 will always be latched.

6. The D latch of anti-dual node flipping according to claim 4, is characterized in that, the fault-tolerant working state occurs in the process of latch latching, and the fault-tolerant working state comprises the following situation:

Case 1:

When the latch latches a low level of "0", the sensitive nodes of the latch are X2, X4, and X6. When any one or two sensitive nodes of the above sensitive nodes are flipped, the sensitive nodes and nodes that have not flipped will not be flipped. There are always two or more nodes in X1, X3 and X5 whose states remain unchanged, so one or two nodes that have flipped above can be restored to their original states;

Case two:

When the latch latches a high level of "1", the sensitive nodes of the latch are X1, X3, and X5. When any one or two sensitive nodes of the above sensitive nodes are flipped, due to the sensitive nodes and nodes that have not flipped There are always two or more nodes in X2 and X4 whose states remain unchanged, so one or two nodes that have flipped above can be restored to their original states.