CN106788379A - A kind of radiation hardening latch based on isomery duplication redundancy - Google Patents

Abstract

The invention relates to a radiation-resistant hardened latch based on heterogeneous dual-mode redundancy, comprising a first storage unit, a transmission unit, a second storage unit and a C unit; the first storage unit, the transmission unit, the second storage unit The signal input terminals of the unit are all connected to the input signal D, the signal output terminal of the first storage unit is connected with the first signal input terminal of the C unit, and the signal output terminal of the second storage unit is connected with the second signal input terminal of the C unit. The terminals are connected, the signal output terminal of the transmission unit is connected to the signal output terminal of the C unit, and the signal output terminal of the C unit is used as the output terminal of the anti-radiation hardened latch. The SET filtering function of the Schmitt trigger in the present invention makes the latch filter the SET pulse in the transparent period; the first storage unit and the second storage unit used in the present invention have the ability to tolerate single-point and double-point reversal, and the It is combined with the C unit, so that the latch can tolerate single-point flip and multi-point flip, and has good fault-tolerant performance.

Description

A radiation hardened latch based on heterogeneous dual-mode redundancy

technical field

The invention relates to the technical field of radiation-resistant integrated circuit design, in particular to a radiation-resistant hardened latch based on heterogeneous dual-mode redundancy.

Background technique

In the aviation environment, due to the influence of cosmic rays, various particles will be produced, including alpha particles, protons and neutrons. When these particles hit the aircraft, it will cause single event transient SET or single event in the circuit in the chip. Flipping SEUs, and even multi-point flipping MNUs will occur as the size of integrated circuits shrinks. This flips the logic value stored in the circuit, causing a functional error in the circuit. Therefore, in order to make the circuit perform the correct function, it is necessary to carry out anti-radiation hardening design on the circuit.

Latches are commonly used sequential logic devices, so an important aspect of anti-radiation hardening design is to harden the latches. Currently commonly used reinforcement methods mainly include process and design. The process mainly refers to layout-level reinforcement. In terms of design, the current classics mainly include triple-mode redundancy and DICE (Dual-Interlocked storage Cell), but they can only tolerate single-point Flip, and triple-mode redundancy has a large area overhead, delay and power consumption.

Contents of the invention

The object of the present invention is to provide a radiation-hardened latch based on heterogeneous dual-mode redundancy that can tolerate single-event flipping and multi-point flipping, so that the latch can store correct logic values.

In order to achieve the above object, the present invention adopts the following technical solutions: a radiation-resistant hardened latch based on heterogeneous dual-mode redundancy, including a first storage unit, a transmission unit, a second storage unit and a C unit; A storage unit is composed of 4 sets of transistor pairs, and each pair of transistors is composed of two NMOS transistors and a PMOS transistor; the transmission unit is composed of a transmission gate TG3, an inverter INV and a Schmitt trigger; The second storage unit is composed of 4 groups of transistor pairs, wherein two groups are two NMOS transistors and one PMOS transistor, and the other two groups are two PMOS transistors and one NMOS transistor; the C unit is composed of two PMOS transistors and two Composed of NMOS transistors; the signal input ends of the first storage unit, the transmission unit, and the second storage unit are all connected to the input signal D, and the signal output end of the first storage unit is connected to the first signal input end of the C unit, so The signal output end of the second storage unit is connected to the second signal input end of the C unit, the signal output end of the transmission unit is connected to the signal output end of the C unit, and the signal output end of the C unit is used as the radiation-resistant hardened latch output.

The 4 groups of transistor pairs included in the first storage unit are respectively the first group of transistor pairs, the second group of transistor pairs, the third group of transistor pairs and the fourth group of transistor pairs; the first group of transistor pairs consists of M1 transistors, N1 tube and N12 tube are composed, the source of M1 tube is connected to VDD, the gate of M1 tube is connected to the source of N12 tube, the drain of M1 tube is connected to the drain of N1 tube, the source of N1 tube is connected to GND, and the gate of N1 tube is connected to GND. The gate of N12 tube is connected to the drain of N4 tube, the source of N12 tube is connected to the grid of M1 tube, the grid of N12 tube is connected to CLK clock signal, and the drain of N12 tube is connected to the drain of M2 tube; the second group The transistor pair is composed of M2 tube, N2 tube and N23 tube. The source of M2 tube is connected to VDD, the gate of M2 tube is connected to the source of N23 tube, the drain of M2 tube is connected to the drain of N2 tube, and the source of N2 tube is The pole is connected to GND, the source gate of N2 tube is connected to the drain of N1 tube, the source of N23 tube is connected to the gate of M2 tube, the gate of N23 tube is connected to CLK clock signal, the drain of N23 tube and the drain of M3 tube The third group of transistors is composed of M3 tube, N3 tube and N34 tube, the source of M3 tube is connected to VDD, the gate of M3 tube is connected to the source of N34 tube, the drain of M3 tube and the drain of N3 tube The drain is connected, the source of the N3 tube is connected to GND, the gate of the N3 tube is connected to the drain of the N2 tube, the source of the N34 tube is connected to the gate of the M3 tube, the gate of the N34 tube is connected to the CLK clock signal, and the drain of the N34 tube The pole is connected to the drain of the M4 tube; the fourth group of transistors is composed of the M4 tube, the N4 tube and the N41 tube, the source of the M4 tube is connected to VDD, the gate of the M4 tube is connected to the source of the N41 tube, and the M4 tube The drain is connected to the drain of the N4 tube, the source of the N4 tube is connected to GND, the gate of the N4 tube is connected to the drain of the N3 tube, the source of the N41 tube is connected to the gate of the M4 tube, and the gate of the N41 tube is connected to the CLK clock signal, the drain of the N41 tube is connected to the drain of the M1 tube.

The Schmitt trigger of the transmission unit is composed of M9 tube, M10 tube, M11 tube, N9 tube, N10 tube and N11 tube, the source of the M9 tube is connected to VDD, the drain of the M9 tube is connected to the source of the M10 tube The gate of the M9 tube is connected to the output of the inverter INV, the source of the M10 tube is connected to the drain of the M9 tube, the gate of the M10 tube is connected to the output of the inverter INV, the source of the N9 tube is connected to the output of the N10 tube The drain of the N9 tube is connected to the output of the inverter INV, the drain of the N9 tube is connected to the signal output terminal of the C unit, the source of the N10 tube is connected to GND, and the gate of the N10 tube is connected to the inverter INV The output of the N10 tube is connected to the source of the N9 tube, the source of the M11 tube is connected to GND, the gate of the M11 tube is connected to the gate of the N11 tube, the drain of the M11 tube is connected to the drain of the M9 tube, and the N11 The source of the tube is connected to VDD, the gate of the N11 tube is connected to the gate of the M11 tube, and the drain of the N11 tube is connected to the drain of the N10.

The second storage unit includes 4 sets of transistor pairs that are respectively the fifth set of transistor pairs, the sixth set of transistor pairs, the seventh set of transistor pairs, and the eighth set of transistor pairs; the fifth set of transistor pairs is composed of M5 transistor pairs. , N5 tube and N34 tube, the source of M5 tube is connected to VDD, the gate of M5 tube is connected to the drain of M8 tube, the drain of M5 tube is connected to the drain of N5 tube, and the source of N5 tube is connected to GND , the gate of the N5 tube is connected to the source of the N34 tube, the source of the N34 tube is connected to the grid of the N5 tube, the gate of the N34 tube is connected to the CLK clock signal, and the drain of the N34 tube is connected to the drain of the M6 tube; The sixth group of transistors is composed of M6 tube, N6 tube and M45 tube. The source of M6 tube is connected to VDD, the gate of M6 tube is connected to the drain of M5 tube, and the drain of M6 tube is connected to the drain of N6 tube. , the source of the N6 tube is connected to GND, the gate of the N6 tube is connected to the drain of the M7 tube, the source of the M45 tube is connected to the drain of the M6 tube, the gate of the M45 tube is connected to the CLKB clock signal, and the drain of the M45 tube is connected to the drain of the M7 tube. The gates of M7 tubes are connected; the seventh group of transistors is composed of M7 tubes, N7 tubes and M56 tubes, the source of M7 tubes is connected to VDD, the gate of M7 tubes is connected to the drain of M45 tubes, and the drain of M7 tubes The pole is connected to the drain of the N7 tube, the source of the N7 tube is connected to GND, the gate of the N7 tube is connected to the source of the N56 tube, the source of the N56 tube is connected to the gate of the N7 tube, and the gate of the N56 tube is connected to CLK Clock signal, the drain of the N56 tube is connected to the drain of the M8 tube; the eighth group of transistors is composed of the M8 tube, the N8 tube and the M63 tube, the source of the M8 tube is connected to VDD, the gate of the M8 tube is connected to the M7 tube The drain of the M8 tube is connected to the drain of the N8 tube, the source of the N8 tube is connected to GND, the gate of the N8 tube is connected to the drain of the M5 tube, the source of the M63 tube is connected to the drain of the M8 tube The gate of the M63 tube is connected to the CLKB clock signal, and the drain of the M63 tube is connected to the gate of the M5 tube.

The C unit includes M11 tube, M12 tube, N11 tube and N12 tube, the source of the M11 tube is connected to VDD, the gate of the M11 tube is connected to the drain of the M4 tube to the node Q1, and the drain of the M11 tube is connected to the drain of the M12 tube. The source is connected, the source of the M12 tube is connected to the drain of the M11 tube, the gate of the M12 tube is connected to the drain of the M8 tube to the node Q2, the drain of the M12 tube is connected to the signal output terminal Q of the C unit, and the N11 tube’s The source is connected to the drain of the N12 tube, the source gate of the N11 tube is connected to the drain of the M8 tube to the node Q2, the source and drain of the N11 tube are connected to the signal output terminal of the C unit, and the source of the N12 tube is connected to GND , the gate of the N12 tube is connected to the drain of the M4 tube to the node Q1, and the drain of the N12 tube is connected to the source of the N11 tube.

The M1 tube, M2 tube, M3 tube and M4 tube are all PMOS transistors, and the N1 tube, N2 tube, N3 tube, N4 tube, N12 tube, N23 tube, N34 tube and N41 tube are all NMOS transistors.

The M9 tube, the M10 tube, and the M11 tube are all PMOS transistors, and the N9 tube, N10 tube, and N11 tube are all NMOS transistors.

The M5 tube, M6 tube, M7 tube, M8 tube, M45 tube and M63 tube are all PMOS transistors, and the N5 tube, N6 tube, N7 tube, N8 tube, N34 tube and N56 tube are all NMOS transistors.

The M11 tube and the M12 tube are PMOS transistors, and the N11 tube and N12 tube are NMOS transistors

Known by above-mentioned technical scheme, the advantage of the present invention is: first, the present invention owing to have used the transmission path that is made up of transmission gate, inverter and Schmitt trigger, because the SET filtering function of Schmitt trigger makes The latch filters the SET pulse during the transparent period; the second, the first storage unit and the second storage unit used in the present invention have the ability to tolerate single-point and double-point inversion, and it is combined with the C unit to make the latch It tolerates single-point flipping and multi-point flipping, and has good fault-tolerant performance; thirdly, compared with other reinforced structures that can tolerate multi-point flipping, the present invention has fewer transistors, which can reduce area overhead, power consumption and delay.

Description of drawings

Fig. 1 is a schematic circuit diagram of the present invention;

Fig. 2 is the circuit schematic diagram of the first storage unit in Fig. 1;

Fig. 3 is a schematic circuit diagram of the transmission unit in Fig. 1;

Fig. 4 is the circuit schematic diagram of the second storage unit in Fig. 1;

FIG. 5 is a schematic circuit diagram of unit C in FIG. 1 .

detailed description

As shown in Figure 1, a radiation-resistant hardened latch based on heterogeneous dual-mode redundancy includes a first storage unit 1, a transmission unit 2, a second storage unit 3 and a C unit 4; the first storage unit 1 is composed of 4 sets of transistor pairs, each pair of transistors is composed of two NMOS transistors and a PMOS transistor; the transmission unit 2 is composed of a transmission gate TG3, an inverter INV and a Schmitt trigger; the The second storage unit 3 is made up of 4 groups of transistor pairs, wherein two groups are two NMOS transistors and one PMOS transistor, and the other two groups are two PMOS transistors and one NMOS transistor; the C unit 4 is composed of two PMOS transistors and two The signal input terminals of the first storage unit 1, the transmission unit 2 and the second storage unit 3 are all connected to the input signal D, and the signal output terminal of the first storage unit 1 is connected with the first storage unit 4 of the C unit 4. The signal input end is connected, the signal output end of the second storage unit 3 is connected with the second signal input end of the C unit 4, the signal output end of the transmission unit 2 is connected with the signal output end of the C unit 4, and the signal output end of the C unit 4 is connected. The signal output terminal serves as the output terminal of the radiation hardened latch.

As shown in Figure 2, the 4 groups of transistor pairs included in the first storage unit 1 are respectively the first group of transistor pairs, the second group of transistor pairs, the third group of transistor pairs and the fourth group of transistor pairs; The group transistor pair is composed of M1 tube, N1 tube and N12 tube. The source of M1 tube is connected to VDD, the gate of M1 tube is connected to the source of N12 tube, the drain of M1 tube is connected to the drain of N1 tube, and the drain of N1 tube The source is connected to GND, the gate of N1 tube is connected to the drain of N4 tube, the source of N12 tube is connected to the gate of M1 tube, the gate of N12 tube is connected to CLK clock signal, the drain of N12 tube and the drain of M2 tube connected; the second group of transistors is composed of M2 tube, N2 tube and N23 tube, the source of M2 tube is connected to VDD, the gate of M2 tube is connected to the source of N23 tube, the drain of M2 tube and the drain of N2 tube The source of the N2 tube is connected to GND, the source gate of the N2 tube is connected to the drain of the N1 tube, the source of the N23 tube is connected to the gate of the M2 tube, the gate of the N23 tube is connected to the CLK clock signal, and the gate of the N23 tube is connected to the CLK clock signal. The drain is connected to the drain of the M3 tube; the third group of transistors is composed of the M3 tube, the N3 tube and the N34 tube, the source of the M3 tube is connected to VDD, the gate of the M3 tube is connected to the source of the N34 tube, and the M3 tube The drain of the N3 tube is connected to the drain of the N3 tube, the source of the N3 tube is connected to GND, the gate of the N3 tube is connected to the drain of the N2 tube, the source of the N34 tube is connected to the gate of the M3 tube, and the gate of the N34 tube is connected to CLK Clock signal, the drain of the N34 tube is connected to the drain of the M4 tube; the fourth group of transistors is composed of the M4 tube, the N4 tube and the N41 tube, the source of the M4 tube is connected to VDD, and the gate of the M4 tube is connected to the N41 tube The source of the tube, the drain of the M4 tube is connected to the drain of the N4 tube, the source of the N4 tube is connected to GND, the gate of the N4 tube is connected to the drain of the N3 tube, the source of the N41 tube is connected to the gate of the M4 tube, and the N41 The gate of the tube is connected to the CLK clock signal, and the drain of the N41 tube is connected to the drain of the M1 tube. The M1 tube, M2 tube, M3 tube and M4 tube are all PMOS transistors, and the N1 tube, N2 tube, N3 tube, N4 tube, N12 tube, N23 tube, N34 tube and N41 tube are all NMOS transistors.

As shown in Figure 3, the Schmitt trigger of the transmission unit 2 is composed of M9 tube, M10 tube, M11 tube, N9 tube, N10 tube and N11 tube, the source of the M9 tube is connected to VDD, and the source of the M9 tube The drain is connected to the source of the M10 tube, the gate of the M9 tube is connected to the output of the inverter INV, the source of the M10 tube is connected to the drain of the M9 tube, the gate of the M10 tube is connected to the output of the inverter INV, and N9 The source of the tube is connected to the drain of the N10 tube, the gate of the N9 tube is connected to the output of the inverter INV, the drain of the N9 tube is connected to the signal output terminal of the C unit 4, the source of the N10 tube is connected to GND, and the N10 tube’s The gate is connected to the output of the inverter INV, the drain of the N10 tube is connected to the source of N9, the source of the M11 tube is connected to GND, the gate of the M11 tube is connected to the gate of the N11 tube, and the drain of the M11 tube is connected to the M9 The drains of the tubes are connected, the source of the N11 tube is connected to VDD, the gate of the N11 tube is connected to the gate of the M11 tube, and the drain of the N11 tube is connected to the drain of the N10. The M9 tube, M10 tube, and M11 tube are all PMOS transistors, and the N9 tube, N10 tube, and N11 tube are all NMOS transistors.

As shown in FIG. 4 , the second storage unit 3 includes four sets of transistor pairs that are respectively the fifth set of transistor pairs, the sixth set of transistor pairs, the seventh set of transistor pairs and the eighth set of transistor pairs; The five groups of transistor pairs are composed of M5 tube, N5 tube and N34 tube. The source of M5 tube is connected to VDD, the gate of M5 tube is connected to the drain of M8 tube, and the drain of M5 tube is connected to the drain of N5 tube. The source of the N5 tube is connected to GND, the gate of the N5 tube is connected to the source of the N34 tube, the source of the N34 tube is connected to the gate of the N5 tube, the gate of the N34 tube is connected to the CLK clock signal, and the drain of the N34 tube is connected to The drain of the M6 tube; the sixth group of transistors is composed of the M6 tube, the N6 tube and the M45 tube, the source of the M6 tube is connected to VDD, the gate of the M6 tube is connected to the drain of the M5 tube, and the drain of the M6 tube It is connected to the drain of the N6 tube, the source of the N6 tube is connected to GND, the gate of the N6 tube is connected to the drain of the M7 tube, the source of the M45 tube is connected to the drain of the M6 tube, and the gate of the M45 tube is connected to the CLKB clock signal , the drain of the M45 tube is connected to the gate of the M7 tube; the seventh group of transistors is composed of the M7 tube, the N7 tube and the M56 tube, the source of the M7 tube is connected to VDD, the gate of the M7 tube is connected to the drain of the M45 tube The drain of the M7 tube is connected to the drain of the N7 tube, the source of the N7 tube is connected to GND, the gate of the N7 tube is connected to the source of the N56 tube, and the source of the N56 tube is connected to the gate of the N7 tube. The gate of the N56 tube is connected to the CLK clock signal, and the drain of the N56 tube is connected to the drain of the M8 tube; the eighth group of transistors is composed of the M8 tube, the N8 tube and the M63 tube, and the source of the M8 tube is connected to VDD, and the M8 tube is connected to the drain of the M8 tube. The gate of the tube is connected to the drain of the M7 tube, the drain of the M8 tube is connected to the drain of the N8 tube, the source of the N8 tube is connected to GND, the gate of the N8 tube is connected to the drain of the M5 tube, and the source of the M63 tube The pole is connected with the drain of the M8 tube, the gate of the M63 tube is connected with the CLKB clock signal, and the drain of the M63 tube is connected with the gate of the M5 tube. The M5 tube, M6 tube, M7 tube, M8 tube, M45 tube and M63 tube are all PMOS transistors, and the N5 tube, N6 tube, N7 tube, N8 tube, N34 tube and N56 tube are all NMOS transistors.

As shown in Figure 5, the C unit 4 includes M11 tube, M12 tube, N11 tube and N12 tube, the source of M11 tube is connected to VDD, the gate of M11 tube is connected to node Q1 with the drain of M4 tube, and the M11 tube The drain of the M12 tube is connected to the source of the M12 tube, the source of the M12 tube is connected to the drain of the M11 tube, the gate of the M12 tube is connected to the drain of the M8 tube to the node Q2, and the drain of the M12 tube is connected to the C unit 4 Signal output terminal Q, the source of the N11 tube is connected to the drain of the N12 tube, the source gate of the N11 tube is connected to the drain of the M8 tube to the node Q2, and the source and drain of the N11 tube are connected to the signal output of the C unit 4 terminal, the source of the N12 tube is connected to GND, the gate of the N12 tube is connected to the drain of the M4 tube to the node Q1, and the drain of the N12 tube is connected to the source of the N11 tube. The tubes M11 and M12 are PMOS transistors, and the tubes N11 and N12 are NMOS transistors.

The present invention will be further described below in conjunction with FIGS. 1 to 5 .

When CLK is high and CLKB is low, transmission gate TG1, transmission gate TG2, transmission gate TG3, transmission gate TG4 and transmission gate TG5 are turned on, and the latch is in the transparent period, the first storage unit 1, transmission unit 2, the second The second storage unit 3 is turned on, and the input signal D reaches the output Q of the latch through the transmission gate TG3, the inverter INV and the Schmitt trigger. The input signal D is respectively written into the nodes X0 and X2 through the transmission gate TG1 and the transmission gate TG2 , and then the value of the node Q1 of the first storage unit 1 is used as the input of the C unit 4 . The input signal D writes the signals into the nodes X3 and X5 respectively through the transmission gate TG4 and the transmission gate TG5, and the value of the node Q2 of the second storage unit 3 is used as another input of the C unit 4, and the two inputs of the C unit 4 are respectively Q1, Q2, the output is the output Q of the latch.

Analysis of the present invention's resistance to single-event transient SET, when CLKB is low level and CLK is high level, the latch is in the transparent period. At this time, only the problem of SET needs to be considered. When the input D has SET When the input signal D passes through the transmission gate TG3, the inverter INV, and the Schmitt trigger, the SET pulse generated will be filtered out. Since the first storage unit and the second storage unit have dual-point self-recovery capabilities, the generated The SET pulse is also eliminated so that the Q delivered to the output is not affected by the SET.

Analyzing the present invention's resistance to single event upset SEU, when CLKB is at high level and CLK is at low level, the latch is in the latching period. Only the first storage unit 1 and the transmission unit 2 are turned on. The first storage unit 1 has 8 internal nodes respectively X0, X1, X2, Q1, BL, CL, QL and AL, and the transmission unit 2 has 8 internal nodes. The nodes are X3, X4, X5, Q2, DL, DR, QL1 and QR respectively. The first storage unit 1 and the second storage unit 3 are improved on the basis of the DICE structure, and both have single-point self-recovery capabilities, so any SEU in any of the 16 nodes can achieve self-recovery.

To analyze the resistance of the present invention to MNU, first consider the situation of double-point flipping, and there are 16 internal nodes in total. There are two types of discussion: In the first case, one node in the first storage unit 1 and the second storage unit 3 is reversed, because both the first storage unit 1 and the second storage unit 3 can be single-point self-recovery, Therefore, the double-point inversion can be self-recovering; in the second case, two nodes in the TDCIE module 1 are inverted or two nodes in the second storage unit 3 are inverted.

For TDCIE module 1, there are a total of 8 internal nodes, which can be divided into two groups, X0, X1, X2 and Q1 are one group, BL, CL, QL and AL are another group, and three typical situations are selected for analysis. . When the logical value of (X0,X1,X2,Q1) is (0, 1, 0, 1), and the logical value of (BL, CL, QL, AL) is (1, 0, 1, 0):

(1) When X0 is turned to 1 and X1 is turned to 0, since CL is still 0 and M2 is turned on, X1 will be restored to 1, Q1 is 1, and N1 is turned on, which will restore the logic value of X0 to 0, completed a self-recovery process;

(2) When X0 is turned to 1 and BL is turned to 0, the N2 transistor will be turned on, and the logic value of X1 point will be turned to 0. Since the logic value of Q1 point is 1 and the N1 transistor is turned on, the logic value of X0 point will be restored to 0, the logic value of CL is 0, and the M2 tube is turned on, so that the logic value of X1 point returns to 1, and a self-recovery process is completed;

(3) When CL is turned to 1 and QL is turned to 0, the M3 transistor is turned on, and the logic value of X2 point is turned to 1, so that the N4 transistor is turned on, and the logic value of Q1 point is turned to 0. Since AL is 0, M4 The tube is turned on, the logic value of Q1 point is restored to 1, and because the logic value of X1 point is 1, and the N3 transistor is turned on, the logic value of point X2 is restored to 0, and a self-recovery process is completed.

For the second storage unit 3, there are a total of 8 internal nodes, which can be divided into two groups, X3, X4, X5 and Q2 are one group, DL, DR, QL1 and QR are another group, and three typical cases are selected Analyze it. When the logic value of (X3,X4,X5,Q2) is (0,1,0,1), (DL,DR,QL1,QR) is (1,1,1,1):

(1) When X3 is turned to 1 and X4 is turned to 0, the N8 transistor is turned on, the logic value of Q2 is turned to 0, the logic value of X5 is 0, the M8 transistor is turned on, and the logic value of Q2 is restored from 0 to 1 , the DL logic is 1, the N5 tube is turned on, and the logic value of the X3 point is restored to 0, so that the M6 transistor is turned on, and the logic value of the X4 point is restored to 1, and a self-recovery process is completed;

(2) When X4 is turned from 1 to 0, and DL is turned from 1 to 0, X3 is 0, M6 is turned on, and the logic value of X4 is restored from 1 to 0, completing a self-recovery process;

(3) When the logic values of QL1 and QR are flipped from 1 to 0, the M5 transistor is turned on, the logic value of X3 is flipped from 0 to 1, the N8 transistor is turned on, and the logic value of Q2 is flipped from 1 to 0, because DL is 1, The N5 tube is turned on, the logic value of the X3 point is restored from 1 to 0, the logic value of the X5 point is 0, the M8 transistor is turned on, and the logic value of the Q2 point is restored from 0 to 1, and a self-recovery process is completed.

The first storage unit 1 and the second storage unit 3 are also unable to self-recovery. For example, when CL and AL in the first storage unit 1 are flipped at the same time, the logic value of the entire latch is flipped. When the double-point reversal cannot be tolerated, the wrong logic value is transmitted to the C unit 4, which will cause the latch to enter a high-impedance state, and the logic value Q output by the circuit remains unaffected. Based on the above analysis, the present invention can tolerate double-point flipping, and self-recovery cannot be realized in a few cases.

Since both the first storage unit 1 and the second storage unit 3 are capable of double-point flip self-recovery, when the particle bombardment causes one node in one of the first storage unit 1 and the second storage unit 3 to flip, the other If two nodes in the unit are flipped, or both nodes of the first storage unit 1 and the second storage unit 3 are flipped, the circuit outputs a correct logic value, so the present invention can tolerate 3-point flips or 4 flips.

Combining the above analysis, it can be seen that the present invention can filter SET and tolerate single-event reversal SEU. For double-point reversal, most of them can realize self-recovery, and 3-point reversal or 4-point reversal can realize partial self-recovery. The invention can be used in the design of highly reliable integrated circuit latches in the aerospace field, and has important significance for improving circuit stability.

Claims (9)

1. a kind of radiation hardening latch based on isomery duplication redundancy, it is characterised in that：Including the first memory cell（1）、 Transmission unit（2）, the second memory cell（3）And C cell（4）；First memory cell（1）By 4 group transistors to constituting, often To transistor to being made up of two NMOS tubes and a PMOS；The transmission unit（2）By a transmission gate TG3, one it is anti- Phase device INV and a Schmidt trigger composition；Second memory cell（3）By 4 group transistors to constituting, wherein two groups are Two NMOS tubes, a PMOS, two groups is two PMOSs, a NMOS tube in addition；The C cell（4）By two PMOS Transistor and two nmos pass transistor compositions；First memory cell（1）, transmission unit（2）, the second memory cell（3）'s Signal input part meets input signal D, first memory cell（1）Signal output part and C cell（4）The first signal it is defeated Enter end to be connected, second memory cell（3）Signal output part and C cell（4）Secondary signal input be connected, the biography Defeated unit（2）Signal output termination C cell（4）Signal output part, C cell（4）Signal output part add as radioresistance The output end of solid lock storage.

2. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：Described One memory cell（1）Comprising 4 group transistors to be respectively the first group transistor to, the second group transistor to, the 3rd group it is brilliant Body pipe pair and the 4th group transistor pair；First group transistor by M1 to being managed, N1 pipes and N12 pipes are constituted, and the source electrode of M1 pipes connects The grid of VDD, M1 pipe connects the source electrode of N12 pipes, and the drain electrode of M1 pipes is connected with the drain electrode of N1 pipes, and the source electrode of N1 pipes meets GND, N1 pipes Grid connects the drain electrode of N4 pipes, and the source electrode of N12 pipes connects the grid of M1 pipes, and the grid of N12 pipes connects CLK clock signals, the drain electrode of N12 pipes Drain electrode with M2 pipes is connected；Second group transistor by M2 to being managed, N2 pipes and N23 pipes are constituted, and the source electrode of M2 pipes meets VDD, M2 The grid of pipe connects the source electrode of N23 pipes, and the drain electrode of M2 pipes is connected with the drain electrode of N2 pipes, and the source electrode of N2 pipes meets GND, the source electrode grid of N2 pipes Pole connects the drain electrode of N1 pipes, and the source electrode of N23 pipes connects the grid of M2 pipes, and the grid of N23 pipes connects CLK clock signals, the drain electrode of N23 pipes and The drain electrode of M3 pipes is connected；3rd group transistor by M3 to being managed, N3 pipes and N34 pipes are constituted, and the source electrode of M3 pipes meets VDD, M3 pipes Grid connect the source electrode of N34 pipes, the drain electrode of M3 pipes is connected with the drain electrode of N3 pipes, and the source electrode of N3 pipes meets GND, and the grid of N3 pipes meets N2 The drain electrode of pipe, the source electrode of N34 pipes connects the grid of M3 pipes, and the grid of N34 pipes connects CLK clock signals, drain electrode and the M4 pipes of N34 pipes Drain electrode is connected；4th group transistor by M4 to being managed, N4 pipes and N41 pipes are constituted, and the source electrode of M4 pipes meets VDD, the grid of M4 pipes The source electrode of N41 pipes is connect, the drain electrode of M4 pipes is connected with the drain electrode of N4 pipes, and the source electrode of N4 pipes meets GND, and the grid of N4 pipes connects the leakage of N3 pipes Pole, the source electrode of N41 pipes connects the grid of M4 pipes, and the grid of N41 pipes connects CLK clock signals, the drain electrode and the drain electrode of M1 pipes of N41 pipes It is connected.

3. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：The biography Defeated unit（2）Schmidt trigger by M9 pipe, M10 pipe, M11 pipe, N9 pipe, N10 pipe and N11 pipes constitute, the source of the M9 pipes Pole meets VDD, and the drain electrode of M9 pipes is connected with the source electrode of M10 pipes, and the grid of M9 pipes connects the output of phase inverter INV, the source electrode of M10 pipes with The drain electrode of M9 pipes is connected, and the grid of M10 pipes connects the output of phase inverter INV, and the source electrode of N9 pipes is connected with the drain electrode of N10 pipes, N9 pipes Grid connect the output of phase inverter INV, the drain electrode of N9 pipes and C cell（4）Signal output part be connected, the source electrode of N10 pipes connects The grid of GND, N10 pipe connects the output of phase inverter INV, and the drain electrode of N10 pipes is connected with the source electrode of N9, and the source electrode of M11 pipes meets GND, The grid of M11 pipes is connected with the grid of N11 pipes, and the drain electrode of M11 pipes is connected with the drain electrode of M9 pipes, and the source electrode of N11 pipes meets VDD, N11 The grid of pipe is connected with the grid of M11 pipes, and the drain electrode of N11 pipes is connected with the drain electrode of N10.

4. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：Described Two memory cell（3）Including 4 group transistors that are included to be respectively the 5th group transistor to, the 6th group transistor to, the 7th Group transistor pair and the 8th group transistor pair；5th group transistor by M5 to being managed, N5 pipes and N34 pipes are constituted, the source of M5 pipes Pole meets VDD, the grid of M5 pipes connects the drain electrode of M8 pipes, the drain electrode of M5 pipes is connected with the drain electrode of N5 pipes, and the source electrode of N5 pipes meets GND, The grid of N5 pipes is connected with the source electrode of N34 pipes, and the source electrode of N34 pipes is connected with the grid of N5 pipes, and the grid of N34 pipes connects CLK clocks Signal, the drain electrode of N34 pipes connects the drain electrode of M6 pipes；6th group transistor by M6 to being managed, N6 pipes and M45 pipes are constituted, M6 pipes Source electrode meets VDD, and the grid of M6 pipes is connected with the drain electrode of M5 pipes, and the drain electrode of M6 pipes is connected with the drain electrode of N6 pipes, and the source electrode of N6 pipes connects The grid of GND, N6 pipe connects the drain electrode of M7 pipes, and the source electrode of M45 pipes is connected with the drain electrode of M6 pipes, and the grid of M45 pipes connects CLKB clocks Signal, the drain electrode of M45 pipes is connected with the grid of M7 pipes；7th group transistor by M7 to being managed, N7 pipes and M56 pipes are constituted, M7 The source electrode of pipe meets VDD, and the grid of M7 pipes is connected with the drain electrode of M45 pipes, and the drain electrode of M7 pipes is connected with the drain electrode of N7 pipes, the source of N7 pipes Pole meets GND, and the grid of N7 pipes is connected with the source electrode of N56 pipes, and the source electrode of N56 pipes is connected with the grid of N7 pipes, and the grid of N56 pipes connects CLK clock signals, the drain electrode of N56 pipes is connected with the drain electrode of M8 pipes；8th group transistor by M8 to being managed, N8 pipes and M63 are managed Composition, the source electrode of M8 pipes meets VDD, and the grid of M8 pipes is connected with the drain electrode of M7 pipes, and the drain electrode of M8 pipes is connected with the drain electrode of N8 pipes, N8 The source electrode of pipe meets GND, and the grid of N8 pipes is connected with the drain electrode of M5 pipes, and the source electrode of M63 pipes is connected with the drain electrode of M8 pipes, M63 pipes Grid connects CLKB clock signals, and the drain electrode of M63 pipes is connected with the grid of M5 pipes.

5. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：The C Unit（4）Including M11 pipes, M12 pipes, N11 pipes and N12 pipes, the source electrode of M11 pipes connects VDD, the grid of M11 pipes and the drain electrode of M4 pipes The drain electrode for being connected in node Q1, M11 pipe is connected with the source electrode of M12 pipes, and the source electrode of M12 pipes is connected with the drain electrode of M11 pipes, M12 pipes The drain electrode of grid and M8 pipes be connected in the drain electrode of node Q2, M12 pipe and connect C cell（4）Signal output part Q, N11 pipe source electrode Drain electrode with N12 pipes is connected, and the source drain that the source gate of N11 pipes is connected in node Q2, N11 pipe with the drain electrode of M8 pipes meets C Unit（4）Signal output part, the source electrode of N12 pipes meets GND, and the grid of N12 pipes is connected in node Q1, N12 with the drain electrode of M4 pipes The drain electrode of pipe is connected with the source electrode of N11 pipes.

6. the radiation hardening latch based on isomery duplication redundancy according to claim 2, it is characterised in that：The M1 Pipe, M2 pipes, M3 pipes and M4 pipes are PMOS transistor, the N1 pipes, N2 pipes, N3 pipes, N4 pipes, N12 pipes, N23 pipes, N34 pipes and N41 pipes are nmos pass transistor.

7. the radiation hardening latch based on isomery duplication redundancy according to claim 3, it is characterised in that：The M9 Pipe, M10 pipes, M11 pipes are PMOS transistor, and the N9 pipes, N10 pipes, N11 pipes are nmos pass transistor.

8. the radiation hardening latch based on isomery duplication redundancy according to claim 4, it is characterised in that：The M5 Pipe, M6 pipes, M7 pipes, M8 pipes, M45 pipes and M63 pipes are PMOS transistor, the N5 pipes, N6 pipes, N7 pipes, N8 pipes, N34 pipes and N56 pipes are nmos pass transistor.

9. the radiation hardening latch based on isomery duplication redundancy according to claim 5, it is characterised in that：It is described M11 pipes, M12 pipes are PMOS transistor, and the N11 pipes, N12 pipes are nmos pass transistor.