CN106558604A - A kind of gate control diode for ESD protection - Google Patents
A kind of gate control diode for ESD protection Download PDFInfo
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- CN106558604A CN106558604A CN201510613288.4A CN201510613288A CN106558604A CN 106558604 A CN106558604 A CN 106558604A CN 201510613288 A CN201510613288 A CN 201510613288A CN 106558604 A CN106558604 A CN 106558604A
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- dummy gate
- main grid
- gate control
- control diode
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- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 238000000407 epitaxy Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 102000000584 Calmodulin Human genes 0.000 description 1
- 108010041952 Calmodulin Proteins 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- QNZFKUWECYSYPS-UHFFFAOYSA-N lead zirconium Chemical compound [Zr].[Pb] QNZFKUWECYSYPS-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of gate control diode for ESD protection, is related to technical field of semiconductors.Including：Semiconductor substrate；Well region；Some fin separations are located in Semiconductor substrate and extend in a first direction；Body active area is connected with one end of some fins and is extended along the second direction vertical with first direction；Main grid pole structure division covers some fins and extends in a second direction；Some first dummy gates are located at interval at main grid structure side, partly cover some fins and extend in a second direction；Some second dummy gates are located at interval at the opposite side of main grid structure, part nappe active area and extend in a second direction；Some source regions are located in some fins between main grid structure and the first dummy gate and adjacent first dummy gate；Some drain regions are located in the body active area between adjacent second dummy gate and extend in a second direction, with the second conduction type.The gate control diode of the present invention has excellent reliability and ESD protection capability.
Description
Technical field
The present invention relates to technical field of semiconductors, is used for ESD protection in particular to a kind of
Gate control diode.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is not mainly by
What the disconnected size for reducing IC-components was realized with improving its speed.At present, due to
In pursuing high device density, high-performance and low cost, semi-conductor industry has advanced to nanotechnology
Process node.However, this progressive trend can produce unfavorable shadow to the reliability of end product
Ring：In technical field of semiconductors, static discharge (ESD) phenomenon is to integrated circuit one
Big to threaten, which can puncture integrated circuit and semiconductor element, promote component ageing, reduce life
Finished products rate.Therefore, with the continuous reduction of manufacture of semiconductor process, ESD protection sets
Meter becomes more and more challenging and difficulty in nano level CMOS technology.
In the prior art, multiple layer metal oxide device, ceramic condenser and diode all may be used
To effectively act as ESD protection effect.Wherein prior art is usually used two pole of MOS structure
Pipe is carrying out ESD protection.Gate control diode (Gated Diode) is a kind of typical electrostatic
Electric discharge (ESD) protective device, wherein, grid is used to define N+ diffusion regions and P+ diffusions
Spacing between area.
As shown in figure 1, FinFET gate control diodes are typically by using a P+ doped and substituted
The N+ in the drain region of nmos device adulterates and is formed.Two under body (bulk) FF that TLP is measured
Secondary breakdown current (It2) tool compared with SOI FF has greatly improved, but the lifting is also still
So not enough.
At present, the layout structure of gate control diode is as shown in Fig. 2 the problem being primarily present is leakage
The current crowding of area side in the bottom of epitaxial layer, and due to the narrower width of fin so that its
It is very little with the calmodulin binding domain CaM of epitaxial layer, therefore limit the discharge capability of device.
Therefore, it is necessary to a kind of new gate control diode for ESD protection is proposed, to solve
Certainly the deficiencies in the prior art.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be concrete real
Further describe in applying mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, the present invention to provide a kind of grid for ESD protection
Control diode, including：
Semiconductor substrate；
Well region with the first conduction type, in the Semiconductor substrate；
Some fins, are located at interval in the Semiconductor substrate and extend in a first direction；
Body active area, is connected simultaneously with one end of some fins in the Semiconductor substrate
Extend along the second direction vertical with the first direction；
Main grid structure, partly covers some fins and extends along the second direction；
Some first dummy gates, are spaced positioned at the main grid structure side, partly cover
Cover some fins and extend along the second direction；
Some second dummy gates, are spaced opposite side positioned at the main grid structure, portion
Divide and cover the body active area and extend along the second direction；
Some source regions, positioned at the main grid structure and first dummy gate and adjacent institute
State in the described some fins between the first dummy gate, with the first conduction type；
Some drain regions, in the body active area between adjacent second dummy gate and
Extend along the second direction, with the second conduction type.
Further, the quantity of some second dummy gates is 2, some drain regions
Quantity is 1.
Further, some second dummy gates and main grid pole spacing structure, if described
Dry drain region and main grid pole spacing structure.
Further, the first epitaxial layer is formed with some source regions, in some drain regions
In be formed with the second epitaxial layer.
Further, first conduction type is p-type, and second conduction type is N-type,
First epitaxial layer is SiGe, and second epitaxial layer is silicon epitaxy layer, or, it is described
First conduction type be N-type, second conduction type be p-type, first epitaxial layer
For silicon epitaxy layer, second epitaxial layer is SiGe.
Further, each described first dummy gate and second dummy gate include virtual
Gate dielectric and the composition of the dummy gate material layer on the dummy gate dielectric layer
Lamination.
Further, also include and source region, each described drain region and the main grid pole each described
Multiple contacts that structure is respectively connected with.
In sum, the gate control diode for ESD protection of the invention, its drain region is formed
In body active area rather than on fin, therefore improve the relieving capacity of electrostatic induced current.And in source
Area and drain region increase multiple dummy gates to control the micro loading effect of epitaxial layer, while making main grid
Certain spacing distance is kept between pole structure and drain region, under the influence of drain region high voltage can be avoided
Grid oxygen breakdown problem generation, therefore, the present invention semiconductor device there is excellent reliability
Property and ESD protection capability.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the generalized section of the existing gate control diode for ESD protection；
Fig. 2 shows the plane figure of the existing gate control diode for ESD protection；
Fig. 3 A show the PMOS grid-control for ESD protection in one embodiment of the invention
The plane figure of diode；
Fig. 3 B show the PMOS grid-control for ESD protection in one embodiment of the invention
The generalized section of diode；
Fig. 4 A show the NMOS grid-control for ESD protection in one embodiment of the invention
The plane figure of diode；
Fig. 4 B show the NMOS grid-control for ESD protection in one embodiment of the invention
The generalized section of diode.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments
Entirely, and those skilled in the art be will fully convey the scope of the invention to.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that work as element or layer be referred to as " ... on ", " with ... it is adjacent ", " connection
To " or when " being coupled to " other elements or layer, its can directly on other elements or layer,
It is adjacent thereto, be connected or coupled to other elements or layer, or there may be element between two parties or
Layer.Conversely, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " directly connect
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.
Although it should be understood that various elements, portion can be described using term first, second, third, etc.
Part, area, floor and/or part, these elements, part, area, floor and/or part should not be by
These terms are limited.These terms are used merely to distinguish element, part, area, floor or a portion
Divide and another element, part, area, floor or part.Therefore, without departing from present invention teach that
Under, the first element discussed below, part, area, floor or part be represented by the second element,
Part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ...
Under ", " ... on ", " above " etc., can describe for convenience here and be used
So as to describe an element or feature shown in figure with other elements or the relation of feature.Should
Understand, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and grasping
The different orientation of the device in work.For example, if the device upset in accompanying drawing, then, description
It is that " below other elements " or " under it " or " under which " element or feature will take
To for other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below with reference to grid for ESD protection of Fig. 3 A-3B and Fig. 4 A-4B to the present invention
Control diode is described in detail.
Wherein, Fig. 3 A show the PMOS for ESD protection in one embodiment of the invention
The plane figure of gate control diode；Fig. 3 B show being used in one embodiment of the invention
The generalized section of the PMOS gate control diodes of ESD protection；Fig. 4 A show the present invention one
The plane figure of the NMOS gate control diodes for ESD protection in embodiment；Fig. 4 B
Show cuing open for the NMOS gate control diodes for ESD protection in one embodiment of the invention
Face schematic diagram.
As shown in figs 3 a and 3b, a kind of NMOS gate control diodes be it illustrates, mainly with
It is illustrated as a example by NMOS gate control diodes.
First, gate control diode of the invention includes：Semiconductor substrate 100.
Specifically, the Semiconductor substrate 100 can be in the following material being previously mentioned at least
It is a kind of：It is laminated on silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator
On stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulator
Germanium (GeOI) etc..
It is formed with isolation structure (not shown) in Semiconductor substrate 100, isolation structure can be with
Isolate (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench, in this enforcement
In example, isolation structure is preferably fleet plough groove isolation structure.
It is also formed with the well region with the first conduction type in Semiconductor substrate 100, described first
Conduction type is N-type or p-type, for example, as shown in Figure 4 B, is formed in PMOS areas
There is N-type well region, as shown in Figure 3 B, P type trap zone is formed with nmos area.
If also including what is be located at interval in the Semiconductor substrate 100 and extend in a first direction
Dry fin 10.Also include body active area 11, body active area 11 is located in Semiconductor substrate 100
It is connected with one end of some fins 10 and along the second direction vertical with the first direction
Extend.Body active area 11 has certain width in the first direction.
The material of the fin 10 and body active area 11 can be the quasiconductors such as silicon, germanium or germanium silicon
Material.Fin 10 is used as the raceway groove of FinFET.Exemplarily, 10 He of the fin
The forming method of body active area 11 can be：Form quasiconductor material first on a semiconductor substrate
The well region with the first conduction type, the quasiconductor have been formed in the bed of material, Semiconductor substrate
Material layer can be with Si, SiGe, Ge or III-V material, then in the semiconductor material layer
The upper mask layer for forming patterning, such as photoresist mask layer, the photoresist mask layer definition
The width of the fin and body active area, length and position etc., then with the photoresist
Mask layer is semiconductor material layer described in mask etch, to form fin and body active area, then
The photoresist mask layer is removed, the method for removing the photoresist mask layer can be oxidation ash
Change method.
In another example, the forming method of the fin 10 and body active area 11 can be with
For：Semiconductor substrate is provided, the trap with the first conduction type is formed with Semiconductor substrate
Area, forms the mask layer of patterning, such as photoresist mask layer on a semiconductor substrate, described
Photoresist mask layer defines width, length and position of the fin and body active area etc.,
Then with the photoresist mask layer as mask etch described in Semiconductor substrate, to form the fin
Piece and body active area, then remove the photoresist mask layer.
It should be noted that the forming method of the fin 10 and body active area 11 is only to show
Example property, it is not limited to said method.
The gate control diode of the present invention also covers some fins 10 and along described including part
The main grid structure 102 that second direction extends.
Specifically, main grid structure 102 includes gate dielectric from bottom to top and grid electricity
Pole.Gate electrode can include each material, described each material including but not limited to：Some
Metal, metal alloy, metal nitride and metal silicide, and its laminate and its be combined
Thing.Gate electrode can also include that the polysilicon and polysilicon-Ge alloy material of doping (that is, has
Have the doping content from about 1e18 per cubic centimeter to about 1e22 foreign atom) and
Polycide (polycide) material (polysilicon of doping/metal silicide laminated material
Material).Similarly, it would however also be possible to employ any one of several methods forms previous materials.Non- limit
Property example processed includes self-aligned metal silicate method, process for chemical vapor deposition of materials and physical vapor
Deposition process, such as, but not limited to：Method of evaporating and sputtering method.Generally, gate electrode bag
Include the polycrystalline silicon material of the doping with from about 50 to about 2000 angstroms of thickness.
Gate dielectric can include traditional dielectric substance such as have electric medium constant from
The oxide of the silicon of about 4 to about 20 (true aerial surveties), nitride and nitrogen oxides.Or
Person, gate dielectric can be included with electric medium constant from about 20 at least about 100
It is usual compared with high dielectric constant dielectric substance.It is this compared with high dielectric constant electrolyte
Can be including but not limited to：Hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and zirconium
Lead titanates (PZTs).Can appointing using the several methods of the material for being adapted to gate dielectric composition of layer
A kind of what formation gate dielectric.It is included but nonrestrictive have heat or plasma oxidation or nitrogen
Change method, process for chemical vapor deposition of materials and physical vapor deposition methods.Generally, gate dielectric
Including the thermal oxidation silicon dielectric substance with from about 5 to about 70 angstroms of thickness.
Can also be formed with a semiconductor substrate 100 positioned at 102 both sides of main grid structure and tight
By the clearance wall structure of main grid structure 102.Wherein, clearance wall structure can include at least one
Layer oxide skin(coating) and/or at least one of which nitride layer.It should be noted that clearance wall structure is
Optional and nonessential, which is mainly used in being etched or protection grid knot during ion implanting
The side wall of structure is injury-free.
The gate control diode of the present invention also includes some first dummy gate 101a, and which is to each other
Every positioned at 102 side of main grid structure, partly cover some fins 10 and along institute
State second direction extension.
The gate control diode of the present invention also includes some second dummy gate 101b, is spaced
Opposite side positioned at the main grid structure 102, partly cover the body active area 11 edge
The second direction extends.
Each first dummy gate 101a and the second dummy gate 101b are situated between including dummy gate
The lamination of electric layer and the composition of the dummy gate material layer on the dummy gate dielectric layer.
The material of dummy gate dielectric layer is preferably oxide, such as silicon dioxide.Dummy gate material
The material of the bed of material includes polysilicon or amorphous carbon, preferably polysilicon.Dummy gate dielectric
The forming method of layer and dummy gate material layer can adopt what those skilled in the art were familiar with
Any prior art, such as preferred chemical vapour deposition technique (CVD), low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD),
Plasma enhanced chemical vapor deposition (PECVD).On a semiconductor substrate 100 can be with shape
Into having respectively positioned at the first dummy gate 101a and the second dummy gate 101b both sides and against the
The clearance wall structure of one dummy gate 101a and the second dummy gate 101b, the clearance wall structure
It is alternatively and nonessential.
The gate control diode of the present invention also includes some source regions 103, and which is located at the main grid pole knot
Between structure 102 and the first dummy gate 101a and adjacent first dummy gate
In some fins 10, with the first conduction type.As shown in Figure 3 B, for NMOS
For gate control diode, the first conduction type is p-type, and the source region 103 is P+ type.Can lead to
Crossing in the predetermined fin for forming source region carries out p type impurity (such as boron etc.) ion implanting and shape
Into.As illustrated in figures 4 a and 4b, for PMOS gate control diodes, the first conductive-type
Type is N-type, and the source region 103 is N+ types.Can be by the predetermined fin 10 for forming source region
In carry out N-type impurity (such as phosphorus, arsenic etc.) ion implanting and formed.
The gate control diode of the present invention also includes some drain regions 104, and which is located at adjacent described second
Extend in the body active area 11 between dummy gate 101b and along the second direction, tool
There is the second conduction type.As shown in Figure 3 B, for NMOS gate control diodes, the
Two conduction types are N-type, it is preferred that drain region 104 is N+ types.Can be by predetermined formation
N-type impurity ion implanting is carried out in the fin in drain region and is formed.As illustrated in figures 4 a and 4b,
For PMOS gate control diodes, the second conduction type is p-type, it is preferred that the leakage
Area 104 is P+ type.Can by carry out in the predetermined fin 10 for forming drain region p type impurity from
Son injects and is formed.Drain region 104 is formed in body active area, is formed in fin with existing
Drain region compare, its ability for wearing of resistance strengthens, therefore can improve the reliability of gate control diode.
Increase the micro loading effect of the controllable epitaxial layer of multiple dummy gates in source region and drain region, reduce electricity
Flow the aggregation in the epitaxial layer bottom of drain region side.
Exemplarily, the quantity of some second dummy gate 101b is 2, some drain regions
104 quantity is 1, fin of the drain region 104 between two the second dummy gate 101b
In.
It is preferred that between some second dummy gate 101b and the main grid structure 102
Every some drain regions 104 are spaced with the main grid structure 102.Second dummy gate and
It is spaced a distance between main grid structure 102, under the influence of drain region high voltage can be avoided
The generation of grid oxygen breakdown problem.
Further, the first epitaxial layer is formed with some source regions 103, if described
The second epitaxial layer is formed with dry drain region 104.
Exemplarily, as shown in Figure 3 B, institute's semiconductor device is NMOS gate control diodes,
Then first conduction type is p-type, and second conduction type is N-type, i.e. source region 103
For P+ type source region, drain region 104 is N+ types drain region, and correspondingly, first epitaxial layer is
SiGe, SiGe are used as compressive stress layer.Second epitaxial layer be silicon epitaxy layer, such as SiC,
SiC is used as tension layer etc..As drain region is formed in body active area, in the epitaxial layer in drain region
Significantly increase with body active region contact, therefore its contact area, accordingly improve electrostatic induced current
Relieving capacity.
In another example, as shown in Figure 4 B, institute's semiconductor device is PMOS grid-control two
Pole pipe, then first conduction type is N-type, and second conduction type is p-type, i.e.,
Source region 103 is N+ type source regions, and drain region 104 is P+ type drain region, correspondingly, outside described first
It is silicon epitaxy layer to prolong layer, and such as SiC, SiC are used as tension layer etc., second epitaxial layer
For SiGe, SiGe is used as compressive stress layer.
Further, gate control diode of the invention also includes and source region each described 103 and every
The individual drain region 104 and the multiple contacts being respectively connected with the main grid structure 102
105.Also include metal interconnecting layer for being connected with main grid structure 102 etc..
In sum, the gate control diode for ESD protection of the invention, its drain region is formed
In body active area rather than on fin, therefore improve the relieving capacity of electrostatic induced current.And in source
Area and drain region increase multiple dummy gates to control the micro loading effect of epitaxial layer
(micro-loading effect), while between making to keep certain between main grid structure and drain region
Gauge from, the generation of the grid oxygen breakdown problem under the influence of the high voltage of drain region can be avoided, therefore,
The semiconductor device of the present invention has excellent reliability and ESD protection capability.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also be made more kinds of modifications and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (7)
1. a kind of gate control diode for ESD protection, including：
Semiconductor substrate；
Well region with the first conduction type, in the Semiconductor substrate；
Some fins, are located at interval in the Semiconductor substrate and extend in a first direction；
Body active area, is connected simultaneously with one end of some fins in the Semiconductor substrate
Extend along the second direction vertical with the first direction；
Main grid structure, partly covers some fins and extends along the second direction；
Some first dummy gates, are spaced positioned at the main grid structure side, partly cover
Cover some fins and extend along the second direction；
Some second dummy gates, are spaced opposite side positioned at the main grid structure, portion
Divide and cover the body active area and extend along the second direction；
Some source regions, positioned at the main grid structure and first dummy gate and adjacent institute
State in the described some fins between the first dummy gate, with the first conduction type；
Some drain regions, in the body active area between adjacent second dummy gate and
Extend along the second direction, with the second conduction type.
2. gate control diode according to claim 1, it is characterised in that described some
The quantity of the second dummy gate is 2, and the quantity in some drain regions is 1.
3. gate control diode according to claim 1, it is characterised in that described some
Second dummy gate and main grid pole spacing structure, some drain regions are tied with the main grid pole
Structure is spaced.
4. gate control diode according to claim 1, it is characterised in that if described
The first epitaxial layer is formed with dry source region, the second epitaxial layer is formed with some drain regions.
5. gate control diode according to claim 4, it is characterised in that described first
Conduction type is p-type, and second conduction type is N-type, and first epitaxial layer is SiGe,
Second epitaxial layer be silicon epitaxy layer, or, first conduction type be N-type, institute
The second conduction type is stated for p-type, first epitaxial layer is silicon epitaxy layer, second extension
Layer is SiGe.
6. gate control diode according to claim 1, it is characterised in that described in each
First dummy gate and second dummy gate include dummy gate dielectric layer and are located at institute
State the lamination of the dummy gate material layer composition on dummy gate dielectric layer.
7. gate control diode according to claim 1, it is characterised in that also include with
It is multiple that each described source region, each described drain region and the main grid structure are respectively connected with
Contact.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021249262A1 (en) * | 2020-06-13 | 2021-12-16 | International Business Machines Corporation | Nanosheet gated diode |
| WO2022041235A1 (en) * | 2020-08-31 | 2022-03-03 | 华为技术有限公司 | Fin field-effect transistor, esd protection circuit, filter circuit and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311237A (en) * | 2012-03-08 | 2013-09-18 | 台湾积体电路制造股份有限公司 | FinFET-Based ESD Devices and Methods for Forming the Same |
| US20150171074A1 (en) * | 2013-12-16 | 2015-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Finfet and transistors with resistors and protection against electrostatic discharge (esd) |
-
2015
- 2015-09-24 CN CN201510613288.4A patent/CN106558604B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311237A (en) * | 2012-03-08 | 2013-09-18 | 台湾积体电路制造股份有限公司 | FinFET-Based ESD Devices and Methods for Forming the Same |
| US20150171074A1 (en) * | 2013-12-16 | 2015-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Finfet and transistors with resistors and protection against electrostatic discharge (esd) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021249262A1 (en) * | 2020-06-13 | 2021-12-16 | International Business Machines Corporation | Nanosheet gated diode |
| WO2022041235A1 (en) * | 2020-08-31 | 2022-03-03 | 华为技术有限公司 | Fin field-effect transistor, esd protection circuit, filter circuit and electronic device |
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| CN106558604B (en) | 2019-07-26 |
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