CN106558604B - A kind of gate control diode for ESD protection - Google Patents
A kind of gate control diode for ESD protection Download PDFInfo
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- CN106558604B CN106558604B CN201510613288.4A CN201510613288A CN106558604B CN 106558604 B CN106558604 B CN 106558604B CN 201510613288 A CN201510613288 A CN 201510613288A CN 106558604 B CN106558604 B CN 106558604B
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- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
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- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of gate control diode for ESD protection, is related to technical field of semiconductors.It include: semiconductor substrate；Well region；Several fin separations are located in semiconductor substrate and extend in a first direction；Body active area is connected with one end of several fins and extends along the second direction vertical with first direction；Main grid pole structure division covers several fins and extends in a second direction；Several first dummy gates are located at interval at main gate structure side, partially cover several fins and extend in a second direction；Several second dummy gates are located at interval at the other side of main gate structure, part nappe active area and extend in a second direction；Several source regions are in several fins between main gate structure and the first dummy gate and adjacent first dummy gate；Several drain regions are in the body active area between adjacent second dummy gate and extend in a second direction, have the second conduction type.Gate control diode of the invention has excellent reliability and ESD protection capability.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of gate control diode for ESD protection.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to nanotechnology process node.However, this progressive trend can generate the reliability of end product
Detrimental effect: in technical field of semiconductors, static discharge (ESD) phenomenon is threatened greatly the one of integrated circuit, can
Puncture integrated circuit and semiconductor element, promote component ageing, reduces production yield rate.Therefore, with manufacture of semiconductor technique
The continuous reduction of size, ESD protection design become more and more challenging and difficulty in nanoscale CMOS technology.
In the prior art, multiple layer metal oxide device, ceramic condenser and diode can effectively act as ESD
Protective action.Wherein the prior art carries out ESD protection usually using MOS structure diode.Gate control diode (Gated
It Diode) is a kind of typical static discharge (ESD) protective device, wherein grid is used to define the diffusion region N+ and the diffusion region P+
Between spacing.
As shown in Figure 1, FinFET gate control diode is generally by using the N in the drain region of a P+ doped and substituted NMOS device
+ adulterate and formed.Secondary breakdown current (It2) has compared with SOI FF under body (bulk) FF that TLP is measured has greatly improved,
But the promotion is also still not enough.
Currently, the layout structure of gate control diode is as shown in Fig. 2, the problem of being primarily present is the current crowding of drain region side
In the bottom of epitaxial layer, and due to the narrower width of fin, so that the bond area of itself and epitaxial layer is very small, therefore limit
The discharge capability of device.
Therefore, it is necessary to propose a kind of new gate control diode for ESD protection, so as to solve the deficiencies in the prior art.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of gate control diode for ESD protection, comprising:
Semiconductor substrate；
Well region with the first conduction type is located in the semiconductor substrate；
Several fins are located at interval in the semiconductor substrate and extend in a first direction；
Body active area, be connected in the semiconductor substrate with one end of several fins simultaneously edge and the first party
Extend to vertical second direction；
Main gate structure partially covers several fins and extends along the second direction；
Several first dummy gates are spaced each other positioned at the main gate structure side, partially cover several fins
And extend along the second direction；
Several second dummy gates are spaced each other the other side positioned at the main gate structure, partially cover the body and have
Source region simultaneously extends along the second direction；
Several source regions are located at the main gate structure and first dummy gate and adjacent first dummy gate
Between several fins in, have the first conduction type；
Several drain regions, in the body active area between adjacent second dummy gate and along the second direction
Extend, there is the second conduction type.
Further, the quantity of several second dummy gates is 2, and the quantity in several drain regions is 1.
Further, several second dummy gates and main grid pole spacing structure, several drain regions and the master
Gate structure interval.
Further, it is formed with the first epitaxial layer in several source regions, is formed with outside second in several drain regions
Prolong layer.
Further, first conduction type is p-type, and second conduction type is N-type, and first epitaxial layer is
SiGe, second epitaxial layer are silicon epitaxy layer, alternatively, first conduction type is N-type, second conduction type is P
Type, first epitaxial layer are silicon epitaxy layer, and second epitaxial layer is SiGe.
Further, each first dummy gate and second dummy gate include dummy gate dielectric layer and position
The lamination of dummy gate material layer composition on the dummy gate dielectric layer.
It further, further include being respectively connected with each source region, each drain region and the main gate structure
Multiple contacts.
In conclusion the gate control diode for ESD protection of the invention, drain region is formed in body active area rather than fin
On piece, therefore improve the relieving capacity of electrostatic induced current.And increase multiple dummy gates in source region and drain region to control epitaxial layer
Micro loading effect, while making to keep certain spacing distance between main gate structure and drain region, can be to avoid drain region high voltage
Under the influence of grid oxygen breakdown problem generation, therefore, semiconductor devices of the invention have excellent reliability and ESD protection energy
Power.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the diagrammatic cross-section of the existing gate control diode for ESD protection；
Fig. 2 shows the plane figures of the existing gate control diode for ESD protection；
Fig. 3 A shows the plane figure of the PMOS gate control diode for ESD protection in one embodiment of the invention；
Fig. 3 B shows the diagrammatic cross-section of the PMOS gate control diode for ESD protection in one embodiment of the invention；
Fig. 4 A shows the plane figure of the NMOS gate control diode for ESD protection in one embodiment of the invention；
Fig. 4 B shows the diagrammatic cross-section of the NMOS gate control diode for ESD protection in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
Embodiment one
The gate control diode for ESD protection of the invention is done below with reference to Fig. 3 A-3B and Fig. 4 A-4B and is retouched in detail
It states.
Wherein, Fig. 3 A shows the planar cloth of the PMOS gate control diode for ESD protection in one embodiment of the invention
Office's figure；Fig. 3 B shows the diagrammatic cross-section of the PMOS gate control diode for ESD protection in one embodiment of the invention；Fig. 4 A
Show the plane figure of the NMOS gate control diode for ESD protection in one embodiment of the invention；Fig. 4 B shows this
Invent the diagrammatic cross-section of the NMOS gate control diode for ESD protection in an embodiment.
As shown in figs 3 a and 3b, it illustrates a kind of NMOS gate control diode, is mainly carried out by taking NMOS gate control diode as an example
It illustrates.
Firstly, gate control diode of the invention includes: semiconductor substrate 100.
Specifically, the semiconductor substrate 100 can be following at least one of the material being previously mentioned: silicon, insulator
Silicon (SSOI) is laminated on upper silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Isolation structure (not shown) is formed in semiconductor substrate 100, isolation structure can be shallow trench isolation (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure, in the present embodiment, isolation structure is preferably shallow trench isolation knot
Structure.
Be also formed with the well region with the first conduction type in semiconductor substrate 100, first conduction type be N-type or
P-type as shown in Figure 3B, is formed with p-type trap for example, as shown in Figure 4 B, N-type well region is formed in the area PMOS in NMOS area
Area.
It further include being located at interval at several fins 10 in the semiconductor substrate 100 and extended in a first direction.Further include
Body active area 11, body active area 11 be located in semiconductor substrate 100 be connected with one end of several fins 10 and along with it is described
The vertical second direction of first direction extends.Body active area 11 has certain width along first direction.
The material of the fin 10 and body active area 11 can be the semiconductor materials such as silicon, germanium or germanium silicon.Fin 10 is used as
The channel of FinFET.Illustratively, the forming method of the fin 10 and body active area 11 can be with are as follows: first in semiconductor
Semiconductor material layer is formed on substrate, and the well region with the first conduction type, the semiconductor have been formed in semiconductor substrate
Then material layer can form patterned mask layer with Si, SiGe, Ge or III-V material on the semiconductor material layer,
Such as photoresist mask layer, the photoresist mask layer define width, length and the position of the fin and body active area
Deng then using the photoresist mask layer as semiconductor material layer described in mask etch, to form fin and body active area, then
The photoresist mask layer is removed, the method for removing the photoresist mask layer can be oxidative ashing method.
In another example, the forming method of the fin 10 and body active area 11 can be with are as follows: provides semiconductor lining
Bottom, is formed with the well region with the first conduction type in semiconductor substrate, forms patterned exposure mask on a semiconductor substrate
Layer, such as photoresist mask layer, the photoresist mask layer define width, length and the position of the fin and body active area
It sets, then using the photoresist mask layer as semiconductor substrate described in mask etch, to form the fin and body active area,
Then the photoresist mask layer is removed.
It should be noted that the forming method of the fin 10 and body active area 11 is only exemplary, do not limit to
In the above method.
Gate control diode of the invention further includes that part covers several fins 10 and extends along the second direction
Main gate structure 102.
Specifically, main gate structure 102 includes gate dielectric and gate electrode from bottom to top.Gate electrode can wrap
Include each material, each material including but not limited to certain metals, metal alloy, metal nitride and metal silicide,
And its laminate and its compound.Gate electrode also may include doping polysilicon and polysilicon-Ge alloy material (that is,
With the doping concentration from about 1e18 per cubic centimeter to about 1e22 foreign atom) and polycide
(polycide) material (polysilicon of doping/metal silicide laminated material).It similarly, can also appointing using several methods
What formation previous materials.Non-limiting example includes self-aligned metal silicate method, process for chemical vapor deposition of materials and object
Vapour deposition method is managed, such as, but not limited to: method of evaporating and sputtering method.In general, gate electrode includes having thickness from big
The polycrystalline silicon material of about 50 to about 2000 angstroms of doping.
Gate dielectric may include traditional dielectric substance such as with electric medium constant from about 4 to about 20
Oxide, nitride and the nitrogen oxides of the silicon of (true aerial survety).Alternatively, gate dielectric may include normal with dielectric
Number from about 20 at least about 100 it is usual compared with high dielectric constant dielectric substance.It is this to be electrolysed compared with high dielectric constant
Material can include but is not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and lead zirconate titanate (PZTs).It can
To form gate dielectric using any of the several methods for the material for being suitble to gate dielectric composition of layer.Included but non-limit
Property processed has heat or plasma oxidation or nitriding method, process for chemical vapor deposition of materials and physical vapor deposition methods.In general, grid
Dielectric layer includes the thermal oxidation silicon dielectric substance with from about 5 to about 70 angstroms of thickness.
It can also be formed on a semiconductor substrate 100 positioned at main 102 two sides of gate structure and against main gate structure 102
Clearance wall structure.Wherein, clearance wall structure may include at least one layer of oxide skin(coating) and/or at least one layer of nitride layer.It needs
It is noted that clearance wall structure be it is optional rather than required, be mainly used for the protection when being etched or ion implanting
The side wall of gate structure is injury-free.
Gate control diode of the invention further includes several first dummy gate 101a, is spaced each other positioned at the main grid pole
102 side of structure partially covers several fins 10 and extends along the second direction.
Gate control diode of the invention further includes several second dummy gate 101b, is spaced each other and ties positioned at the main grid pole
The other side of structure 102 partially covers the body active area 11 and extends along the second direction.
Each first dummy gate 101a and the second dummy gate 101b includes dummy gate dielectric layer and is located at described
The lamination of dummy gate material layer composition on dummy gate dielectric layer.The material of dummy gate dielectric layer preferably aoxidizes
Object, such as silica.The material of dummy gate material layer includes polysilicon or amorphous carbon, preferably polysilicon.Virtually
Any existing skill that the forming method of gate dielectric and dummy gate material layer can be familiar with using those skilled in the art
Art, preferably chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD),
Fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).May be used also on a semiconductor substrate 100
The first dummy gate 101a and the second two sides dummy gate 101b are located at and against the first dummy gate 101a to be formed with
With the clearance wall structure of the second dummy gate 101b, which is optionally rather than required.
Gate control diode of the invention further includes several source regions 103, is located at the main gate structure 102 and described first
In several fins 10 between dummy gate 101a and adjacent first dummy gate, there is the first conduction type.
As shown in Figure 3B, for NMOS gate control diode, the first conduction type is p-type, which is P+ type.Can pass through to
It carries out p type impurity (such as boron etc.) ion implanting in the predetermined fin for forming source region and is formed.As illustrated in figures 4 a and 4b, for
For PMOS gate control diode, the first conduction type is N-type, which is N+ type.It can be by the predetermined fin for forming source region
N-type impurity (such as phosphorus, arsenic etc.) ion implanting is carried out in piece 10 and is formed.
Gate control diode of the invention further includes several drain regions 104, be located at the adjacent second dummy gate 101b it
Between the body active area 11 in and along the second direction extend, have the second conduction type.As shown in Figure 3B, for NMOS
For gate control diode, the second conduction type is N-type, preferably, drain region 104 is N+ type.It can be by forming drain region to predetermined
N-type impurity ion implanting is carried out in fin and is formed.As illustrated in figures 4 a and 4b, for PMOS gate control diode, second is led
Electric type is p-type, preferably, the drain region 104 is P+ type.It can be by carrying out p type impurity into the predetermined fin 10 for forming drain region
Ion implanting and formed.Drain region 104 is formed in body active area, compared with the existing drain region being formed in fin, is resisted
The ability enhancing worn, therefore the reliability of gate control diode can be improved.It is controllable to increase multiple dummy gates in source region and drain region
The micro loading effect of epitaxial layer reduces electric current in the aggregation of the epitaxial layer bottom of drain region side.
Illustratively, the quantity of several second dummy gate 101b is 2, and the quantity in several drain regions 104 is 1, a leakage
Area 104 is located in the fin between two the second dummy gate 101b.
Preferably, several second dummy gate 101b and the main gate structure 102 are spaced, several drain regions
104 are spaced with the main gate structure 102.It is spaced a distance between second dummy gate and main gate structure 102, it can be with
Avoid the generation of the grid oxygen breakdown problem under the influence of the high voltage of drain region.
Further, it is formed with the first epitaxial layer in several source regions 103, is formed in several drain regions 104
There is the second epitaxial layer.
Illustratively, as shown in Figure 3B, institute's semiconductor devices is NMOS gate control diode, then first conduction type is
P-type, second conduction type are N-type, i.e., source region 103 is P+ type source region, and drain region 104 is N+ type drain region, correspondingly, described the
One epitaxial layer is SiGe, and SiGe is as compressive stress layer.Second epitaxial layer is silicon epitaxy layer, such as SiC, SiC are answered as drawing
Power layer etc..Since drain region is formed in body active area, epitaxial layer and body active region contact in drain region, therefore its contact area is aobvious
It writes and increases, correspondinglyd increase the relieving capacity of electrostatic induced current.
In another example, as shown in Figure 4 B, institute's semiconductor devices is PMOS gate control diode, then described first is conductive
Type is N-type, and second conduction type is p-type, i.e., source region 103 is N+ type source region, and drain region 104 is P+ type drain region, correspondingly,
First epitaxial layer is silicon epitaxy layer, such as SiC, SiC as tensile stress layer etc., and second epitaxial layer is SiGe, SiGe
As compressive stress layer.
Further, gate control diode of the invention further include with each source region 103 and each drain region 104 with
And the multiple contacts 105 being respectively connected with the main gate structure 102.It further include the metal being connected with main gate structure 102
Interconnection layer etc..
In conclusion the gate control diode for ESD protection of the invention, drain region is formed in body active area rather than fin
On piece, therefore improve the relieving capacity of electrostatic induced current.And increase multiple dummy gates in source region and drain region to control epitaxial layer
Micro loading effect (micro-loading effect), while making to keep certain interval distance between main gate structure and drain region
From, it can be to avoid the generation of the grid oxygen breakdown problem under the influence of the high voltage of drain region, therefore, semiconductor devices of the invention has excellent
Different reliability and ESD protection capability.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (7)
1. a kind of gate control diode for ESD protection, comprising:
Semiconductor substrate；
Well region with the first conduction type is located in the semiconductor substrate；
Several fins are located at interval in the semiconductor substrate and extend in a first direction；
Body active area is connected with one end of several fins in the semiconductor substrate and hangs down along with the first direction
Straight second direction extends；
Main gate structure partially covers several fins and extends along the second direction；
Several first dummy gates are spaced each other positioned at the main gate structure side, partially cover several fins and edge
The second direction extends；
Several second dummy gates are spaced each other the other side positioned at the main gate structure, partially cover the body active area
And extend along the second direction；
Several source regions, between the main gate structure and first dummy gate and adjacent first dummy gate
Several fins in, have the first conduction type；
Several drain regions are prolonged in the body active area between adjacent second dummy gate and along the second direction
It stretches, there is the second conduction type.
2. gate control diode according to claim 1, which is characterized in that the quantity of several second dummy gates is 2
A, the quantity in several drain regions is 1.
3. gate control diode according to claim 1, which is characterized in that several second dummy gates and the main grid
Pole spacing structure, several drain regions and main grid pole spacing structure.
4. gate control diode according to claim 1, which is characterized in that be formed with the first extension in several source regions
Layer, is formed with the second epitaxial layer in several drain regions.
5. gate control diode according to claim 4, which is characterized in that first conduction type be p-type, described second
Conduction type is N-type, and first epitaxial layer is SiGe, and second epitaxial layer is silicon epitaxy layer, alternatively, described first is conductive
Type is N-type, and second conduction type is p-type, and first epitaxial layer is silicon epitaxy layer, and second epitaxial layer is
SiGe。
6. gate control diode according to claim 1, which is characterized in that each first dummy gate and described second
Dummy gate includes dummy gate dielectric layer and the dummy gate material layer composition on the dummy gate dielectric layer
Lamination.
7. gate control diode according to claim 1, which is characterized in that further include and each source region, each described
Multiple contacts that drain region and the main gate structure are respectively connected with.
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