CN103377940B - A kind of P-type transmission gridistor for SRAM and preparation method thereof - Google Patents
A kind of P-type transmission gridistor for SRAM and preparation method thereof Download PDFInfo
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- CN103377940B CN103377940B CN201210124387.2A CN201210124387A CN103377940B CN 103377940 B CN103377940 B CN 103377940B CN 201210124387 A CN201210124387 A CN 201210124387A CN 103377940 B CN103377940 B CN 103377940B
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Abstract
The present invention provides a kind of P-type transmission gridistor for SRAM and preparation method thereof.This manufacture method includes: provide Semiconductor substrate, described Semiconductor substrate is formed with P-type grid electrode；Forming stressor layers in first area in the described Semiconductor substrate of described P-type grid electrode side, described stressor layers is for improving the mobility of carrier；Source electrode is formed in forming drain electrode and the second area in the described Semiconductor substrate of described P-type grid electrode opposite side in described first area.The present invention forms again drain electrode by i.e. forming the stressor layers that can improve carrier mobility in the first area of the Semiconductor substrate of P-type grid electrode side, and in the second area of the Semiconductor substrate of P-type grid electrode opposite side, form source electrode, drain electrode the most only just can be made by simple processing step to be more than, to the electric current of source electrode, the electric current that source electrode extremely drains, and then increase read/write difference between current.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, pass particularly to a kind of p-type for SRAM
Defeated gridistor and preparation method thereof.
Background technology
Static random accesP memorizer (SRAM) is embedded into almost all of large scale integrated circuit
(VLSI) in, and require high speed, high integration, low-power consumption, low cost, short-period should
Critical effect is served in.
In advanced CMOS technology, will face by read/write stability less than the SRAM of 1V
The serious problems reduced and cause.As a example by the cellular construction of the 6T-SRAM including 6 transistors,
One of its root is the conflicting needs for read operation and write operation, i.e. transmits grid (pass
What gate) electric current flowed in transistor should be tried one's best when performing read operation is little, on the contrary, is performing
Should try one's best during write operation big.That is, it is desirable to arrive via transmission gridistor from bit line
The electric current of internal node should be smaller, and wishes to arrive via transmission gridistor from internal node
The electric current of bit line should be larger, i.e. intentionally gets read/write difference between current (read/write margin).
In order to increase read/write difference between current, it is thus proposed that by transmitting source electrode and the drain electrode of gridistor
Between formed asymmetric halo doping, as shown in Figure 1.In substrate 100 below grid 101
Raceway groove in carry out asymmetric halo doping, so that source electrode 102 is big to the electric current of drain electrode 103
Electric current in drain electrode 103 to source electrode 102.By its source electrode 102 being connected to internal node, and will
Drain electrode 103 is connected to bit line and can obtain read/write difference between current.
But, the complex manufacturing technology that the transmission gridistor of this structure needs, and need to increase
Add the most extra mask layer, thus cause occurring that less desirable cost improves.
Accordingly, it would be desirable to a kind of P-type transmission gridistor for SRAM and preparation method thereof, with
Solve problems of the prior art.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in specific embodiment party
Formula part further describes.The Summary of the present invention is not meant to attempt to limit
Go out key feature and the essential features of technical scheme required for protection, more do not mean that and attempt really
The protection domain of fixed technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of P for SRAM
The manufacture method of type transmission gridistor, including: Semiconductor substrate, described Semiconductor substrate are provided
On be formed with P-type grid electrode；First area in the described Semiconductor substrate of described P-type grid electrode side
Interior formation stressor layers, described stressor layers is for improving the mobility of carrier；In described first area
Formed in forming drain electrode and the second area in the described Semiconductor substrate of described P-type grid electrode opposite side
Source electrode.
Preferably, the step forming described stressor layers includes: a) at described Semiconductor substrate and described P
Etching stopping layer is formed on type grid；B) on described etching stopping layer, the described first area of exposure is formed
Photoresist layer；C) the described first area of described etching stopping layer and described Semiconductor substrate is carried out
Etching, to form groove in the described first area of described Semiconductor substrate；D) shape in described groove
Become stressor layers.
Preferably, described stressor layers is germanium silicon stressor layers.
Preferably, the method forming germanium silicon stressor layers in described groove is epitaxy.
Preferably, in described germanium silicon stressor layers, the content of germanium is 10%-70%.
Preferably, described etching stopping layer is silicon nitride layer.
Preferably, after described c) step, also include the step removing described photoresist layer.
Preferably, after described d) step, also include the step removing described etching stopping layer.
Invention additionally discloses a kind of P-type transmission gridistor for SRAM, described P-type transmission
Gridistor includes: Semiconductor substrate；Form P-type grid electrode on the semiconductor substrate；Shape
Become the stressor layers in the first area in the described Semiconductor substrate of described P-type grid electrode side, described
Stressor layers is for improving the mobility of carrier；It is formed at the drain electrode in described first area；And shape
Become the source electrode in the second area in the described Semiconductor substrate of described P-type grid electrode opposite side.
Preferably, described stressor layers is germanium silicon stressor layers.
Preferably, in described germanium silicon stressor layers, the content of germanium is 10%-70%.
The present invention can carry by i.e. being formed in the first area of the Semiconductor substrate of P-type grid electrode side
The stressor layers of high carrier mobility forms again drain electrode, and in the Semiconductor substrate of P-type grid electrode opposite side
Second area in formed source electrode, drain electrode the most only just can be made to source electrode by simple processing step
Electric current is more than the electric current of source electrode to drain electrode, and then increases read/write difference between current.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.In accompanying drawing
Show embodiments of the invention and description thereof, be used for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the sectional view of existing asymmetric transmission gridistor；And
Fig. 2 A-2F is the P-type transmission gridistor process made according to one embodiment of the present invention
In the generalized section of device that obtained of each step.
Detailed description of the invention
It follows that the present invention will be more fully described by conjunction with accompanying drawing, shown in the drawings of the present invention's
Embodiment.But, the present invention can implement in different forms, and should not be construed as being limited to here
The embodiment proposed.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district
Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling
Conjunction is arrived " other element or during layer, its can directly on other element or layer, adjacent thereto, connect
Or be coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, when element quilt
Be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan
When part or layer, the most there is not element between two parties or layer.
The present invention provides the manufacture method of a kind of P-type transmission gridistor.According to Fig. 2 A-2F originally
Invent the device that each step during the P-type transmission gridistor that embodiment makes is obtained
Generalized section.
First, it is provided that Semiconductor substrate, this Semiconductor substrate forms P-type grid electrode.
As shown in Figure 2 A, it is provided that Semiconductor substrate 200.As example, Semiconductor substrate 200 is permissible
It is at least one in the following material being previously mentioned: silicon, silicon-on-insulator (SOI), insulator upper strata
Stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) on folded silicon (SSOI), insulator
And germanium on insulator (GeOI) etc..Additionally, could be formed with isolation junction in Semiconductor substrate 200
Structure, described isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS)
Isolation structure.Described Semiconductor substrate is also formed with the channel layer of various well structure and substrate surface.
In general, ion doping conduction type and the channel layer ion doping conduction type phase of well structure are formed
With, but concentration is low compared with gate channel layer, and the degree of depth of ion implanting is general encloses relatively extensively, needs to reach big simultaneously
The degree of depth in isolation structure.To put it more simply, the most only with a blank semiconductor substrate diagram.
It is formed with P-type grid electrode 201 in this Semiconductor substrate 200.P-type grid electrode 201 can include grid
Pole dielectric layer and gate material layers (the most not shown).Gate dielectric can be silicon oxide (SiO2) nitrogen
Silicon oxide (SiON).Gate material layers can include each material, each material described comprise but not
Be limited to: some metal, metal alloy, metal nitride and metal silicide, and laminate and
Its complex.P-type grid electrode 201 can also include doping polysilicon and polysilicon-Ge alloy material with
And polycide material (polysilicon of doping/metal silicide laminated material).
Then, the formation stressor layers in the first area in the Semiconductor substrate of P-type grid electrode side,
This stressor layers is for improving the mobility of carrier.
For convenience, the region that P-type grid electrode side is used for being formed drain electrode herein is defined as partly leading
The first area of body substrate, and the region that P-type grid electrode opposite side is used for being formed source electrode is defined as partly leading
The second area of body substrate.Those skilled in the art can use multiple method shape in first area
One-tenth can improve the stressor layers of carrier mobility so that drain electrode to source electrode electric current more than source electrode to leakage
The electric current of pole, and then increase read/write difference between current.Describe in detail according to the present invention below in conjunction with accompanying drawing
The method of the formation stressor layers of one embodiment.
With continued reference to Fig. 2 A, Semiconductor substrate 200 and P-type grid electrode 201 form etch stop
Layer 202.Being usually formed the mask layer that grid 201 used is silicon nitride, in order to reduce technique
Step, it is preferable that etching stopping layer 202 is also silicon nitride layer.So forming etching stopping layer 202
Before without removing the mask layer forming grid, as long as and just may be used by a step operation in subsequent step
So that both are removed simultaneously.
Etching stopping layer 202 is formed the photoresist layer 203 exposing first area A, wherein, P
Type grid 201 side is first area A for forming the region of drain electrode, P-type grid electrode 201 opposite side
It is second area B for forming the region of source electrode.Photoresist layer 203 expose first area A be in order to
In the A of first area, form groove (seeing 204 in Fig. 2 B) through subsequent technique, therefore have it
In the case of its layer stops, the size of the opening on photoresist layer 203 can be made to be more than first area A
Size.As shown in Figure 2 A, photoresist layer 203 can also expose P-type grid electrode 201 near first
Mask layer on the sidewall of region A.
As shown in Figure 2 B, the first area A of mask layer 202 and Semiconductor substrate 201 is carved
Erosion, forms groove 204 with the first area A in Semiconductor substrate 200.
As shown in Figure 2 C, photoresist layer 203 is removed.
As shown in Figure 2 D, in groove 204, stressor layers 205 is formed.Preferably, stressor layers 205
For germanium silicon stressor layers.As example, the method forming germanium silicon stressor layers 205 in groove 204 is outward
Prolong method.Epitaxy can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid heat chemical gas
Deposit the one in (RTCVD) and molecular beam epitaxy (MBE) mutually.Epitaxial deposition can be
UHV/CVD reaction chamber is carried out.And in order to obtain suitable read/write difference between current, it is preferable that germanium
In silicon stressor layers 204, the content of germanium is 10%-70%.
As shown in Figure 2 E, etching stopping layer 202 is removed.
After forming stressor layers in the first area of Semiconductor substrate, can be formed in first area
Source electrode is formed, to complete in drain electrode and the second area in the Semiconductor substrate of P-type grid electrode opposite side
The making of P-type transmission gridistor.As shown in Figure 2 F, method conventional in this area can be used
Drain electrode 206A and source is formed respectively in the first area A and second area B of Semiconductor substrate 200
Pole 206B.Drain electrode 206A and source electrode 206B can include shallow doped region.For including shallow doped region
Drain electrode 206A and source electrode 206B for, can first grid both sides formed offset by gap wall
(offset spacer), then employing p-type ion implantation technology is to form shallow doped region, then partially
The both sides moving clearance wall form clearance wall, then use p-type ion implantation technology with the leakage formed
Pole 206A and source electrode 206B.Drain electrode 206A and the formation of source electrode 206B due to above-mentioned various structures
Method is thought and be it is known in the art, therefore, and I will not elaborate.
The present invention can carry by i.e. being formed in the first area of the Semiconductor substrate of P-type grid electrode side
The stressor layers of high carrier mobility forms again drain electrode, and in the Semiconductor substrate of P-type grid electrode opposite side
Second area in formed source electrode, drain electrode the most only just can be made to source electrode by simple processing step
Electric current is more than the electric current of source electrode to drain electrode, and then increases read/write difference between current.
Additionally, the present invention also provides for a kind of P-type transmission gridistor for SRAM, such as figure
Shown in 2F, this P-type transmission gridistor includes Semiconductor substrate 200, is formed at Semiconductor substrate
P-type grid electrode 201, the stressor layers 205 being formed in the A of first area on 200, it is formed at the firstth district
Drain electrode 206A in the A of territory and the source electrode 206B being formed in second area B.Wherein stressor layers 205
For improving the mobility of carrier so that drain electrode to source electrode electric current more than source electrode to drain electrode electric current,
And then increase read/write difference between current.
Preferably, stressor layers 205 is germanium silicon stressor layers.And it is further preferred that in germanium silicon stressor layers
The content of germanium is 10%-70%, to obtain suitable read/write difference between current.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned enforcement
Example is only intended to citing and descriptive purpose, and is not intended to limit the invention to described embodiment
In the range of.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-mentioned enforcement
Example, can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications
Within all falling within scope of the present invention.Protection scope of the present invention is wanted by attached right
Book and equivalent scope thereof is asked to be defined.
Claims (7)
1. the manufacture method for the P-type transmission gridistor of SRAM, it is characterised in that
Including:
Semiconductor substrate is provided, described Semiconductor substrate is formed with P-type grid electrode；
Stressor layers is formed in first area in the described Semiconductor substrate of described P-type grid electrode side,
Described stressor layers is for improving the mobility of carrier；
Drain electrode and the described quasiconductor lining at described P-type grid electrode opposite side is formed in described first area
Source electrode is formed in second area at the end；
Described stressor layers is germanium silicon stressor layers, and in described germanium silicon stressor layers, the content of germanium is 10%-70%.
Manufacture method the most according to claim 1, it is characterised in that form described stressor layers
Step include:
A) in described Semiconductor substrate and described P-type grid electrode, etching stopping layer is formed；
B) on described etching stopping layer, form the photoresist layer of the described first area of exposure；
C) the described first area of described etching stopping layer and described Semiconductor substrate is performed etching, with
Groove is formed in the described first area of described Semiconductor substrate；
D) in described groove, stressor layers is formed.
Manufacture method the most according to claim 2, it is characterised in that shape in described groove
The method becoming germanium silicon stressor layers is epitaxy.
Manufacture method the most according to claim 2, it is characterised in that described etching stopping layer
For silicon nitride layer.
Manufacture method the most according to claim 2, it is characterised in that described c) step it
After also include the step of removing described photoresist layer.
Manufacture method the most according to claim 2, it is characterised in that described d) step it
After also include the step of removing described etching stopping layer.
7. the P-type transmission gridistor for SRAM, it is characterised in that described p-type
Transmission gridistor includes:
Semiconductor substrate；
Form P-type grid electrode on the semiconductor substrate；
The stress being formed in the first area in the described Semiconductor substrate of described P-type grid electrode side
Layer, described stressor layers is for improving the mobility of carrier；
It is formed at the drain electrode in described first area；And
The source being formed in the second area in the described Semiconductor substrate of described P-type grid electrode opposite side
Pole；
Described stressor layers is germanium silicon stressor layers, and in described germanium silicon stressor layers, the content of germanium is 10%-70%.
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| CN201210124387.2A CN103377940B (en) | 2012-04-25 | 2012-04-25 | A kind of P-type transmission gridistor for SRAM and preparation method thereof |
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| CN105845680B (en) * | 2015-01-14 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
| CN108417489B (en) * | 2017-02-10 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory and forming method thereof |
| CN108417537B (en) * | 2017-02-10 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002328A (en) * | 2004-08-24 | 2007-07-18 | 飞思卡尔半导体公司 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device |
| CN101490836A (en) * | 2006-07-28 | 2009-07-22 | 飞思卡尔半导体公司 | Transistor with asymmetry for data storage circuitry |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7355221B2 (en) * | 2005-05-12 | 2008-04-08 | International Business Machines Corporation | Field effect transistor having an asymmetrically stressed channel region |
| US20100207175A1 (en) * | 2009-02-16 | 2010-08-19 | Advanced Micro Devices, Inc. | Semiconductor transistor device having an asymmetric embedded stressor configuration, and related manufacturing method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002328A (en) * | 2004-08-24 | 2007-07-18 | 飞思卡尔半导体公司 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device |
| CN101490836A (en) * | 2006-07-28 | 2009-07-22 | 飞思卡尔半导体公司 | Transistor with asymmetry for data storage circuitry |
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