CN103579003A - Method for manufacturing super joint MOSFET - Google Patents
Method for manufacturing super joint MOSFET Download PDFInfo
- Publication number
- CN103579003A CN103579003A CN201210281452.2A CN201210281452A CN103579003A CN 103579003 A CN103579003 A CN 103579003A CN 201210281452 A CN201210281452 A CN 201210281452A CN 103579003 A CN103579003 A CN 103579003A
- Authority
- CN
- China
- Prior art keywords
- type silicon
- type
- layer
- tagma
- mask layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- JTJMJGYZQZDUJJ-UHFFFAOYSA-N phencyclidine Chemical compound C1CCCCN1C1(C=2C=CC=CC=2)CCCCC1 JTJMJGYZQZDUJJ-UHFFFAOYSA-N 0.000 title abstract 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 98
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000002210 silicon-based material Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000407 epitaxy Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The embodiment of the invention provides a method for manufacturing a super joint MOSFET to solve the problem that the technology for manufacturing the super joint MOSFET is complex in the prior art. The method comprises the steps that P-type ions are injected and driven into a mask layer which is provided with a window in an etching mode, and a P-type silicon body area is formed in an N-type silicon epitaxial layer below the mask layer; a groove is etched in the position corresponding to the window of the mask layer, and the groove penetrates through the P-type silicon body area to reach the N-type silicon epitaxial layer; silicon materials mixed with P-type impurities are injected into the groove in an epitaxial mode until the groove is full of the silicon materials, the etched P-type silicon body area is restored, and a P-type drift area on the lower portion of the P-type silicon body area is formed; the mask layer is removed; two N-type silicon source areas are formed in the P-type silicon body area; an insulating medium layer is grown and etched on the N-type silicon epitaxial layer after the mask layer is removed, a contact hole is formed, metal layers are grown on the insulating medium layer and the contact hole, and a source electrode of the super joint MOSFET is formed; a metal layer is grown on a N-type silicon substrate to form a drain electrode of the super joint MOSFET.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, relate in particular to super node MOSFET device manufacture method.
Background technology
In power electronics application, in order to reduce power consumption, require semiconductor device can bear higher voltage under off-state, under conducting state, there is lower conducting resistance, conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor fieldeffect transistor), conventionally adopt VDMOS(Vertical Double-diffused MOSFET, vertical double-diffused MOS FET) structure, high withstand voltage in order to meet, need to reduce drift region concentration or increase drift region thickness, but conducting resistance also increases thereupon, its conducting resistance and puncture voltage are the relation of 2.5 powers.The drift region that super node MOSFET adopts pn structure alternately to form replaces the N-shaped drift region in VDMOS, has solved the contradiction between conducting resistance and puncture voltage, makes its conducting resistance and puncture voltage be the relation of 1.32 powers.Therefore,, compared with conventional power MOSFET, super node MOSFET is having huge advantage aspect puncture voltage and conducting resistance.
But for the device of this structure of super node MOSFET, p-type drift region lateral dimension is wherein very little, but longitudinal size very dark (generally having 50 μ m left and right) is made very difficult.The at present making of the P type drift region of super node MOSFET by N-type substrate by growth N-type epitaxial loayer with inject P type ion repeatedly mutually alternately and the doping of P type driven in.First at N-type Grown N-type epitaxial loayer, photoetching P district, inject P type ion, then remove photoresist, the step of repeated growth N-type epitaxial loayer, photoetching P district and injection P type ion, until the longitudinal size in P district reaches requirement, is finally carried out the doping of P type again and is driven in the making that can complete P type drift region.This way need to be done repeatedly epitaxial growth and Implantation, so technique is very loaded down with trivial details, and repeatedly carries out the production cost that epitaxially grown technique has also increased super node MOSFET.
Summary of the invention
The embodiment of the present invention provides a kind of method of making super node MOSFET, in order to solve in prior art, makes the problem that super node MOSFET technique is loaded down with trivial details, reduces the production cost of super node MOSFET.
Based on the problems referred to above, a kind of method of making super node MOSFET that the embodiment of the present invention provides, comprising:
To the mask layer that is etched with window, inject P type ion and drive in, in the N-type silicon epitaxy layer under described mask layer, forming P type tagma;
With described mask layer on the correspondence position of window etch groove, described groove penetrates described P type silicon tagma and arrives in N-type epitaxial loayer;
In described groove, extension is mixed the silicon materials of p type impurity until groove is filled, and recovers the P type silicon tagma being etched away and the P type drift region that forms bottom, P type silicon tagma;
Remove described mask layer;
In P type silicon tagma, form two N-type silicon source regions;
Growth and etching insulating medium layer on N-type silicon epitaxy layer after removing mask layer, form contact hole, growing metal layer on described insulating medium layer and in contact hole, the source electrode of formation super node MOSFET;
On N-type silicon substrate, growing metal layer forms the drain electrode of super node MOSFET.
The beneficial effect of the embodiment of the present invention comprises:
A kind of method of making super node MOSFET that the embodiment of the present invention provides, the method by needing the region that forms P type drift region to etch groove in N-type silicon epitaxy layer, then in groove, extension is mixed the silicon materials of p type impurity until groove is filled formation P type drift region, substitute in prior art by N-type Grown N-type epitaxial loayer with inject P type ion repeatedly mutually alternately and the technical process of the P type doping P type drift region that drives in to form, thereby simplified the manufacture craft of making super node MOSFET, reduced the production cost of super node MOSFET.
Accompanying drawing explanation
The schematic diagram of grow on N-type epitaxial loayer grid oxic horizon, polysilicon layer, mask layer that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 etches the schematic diagram of window for what the embodiment of the present invention provided in mask layer and polysilicon layer;
Fig. 3 forms the schematic diagram in P type tagma for what the embodiment of the present invention provided in N-type epitaxial loayer;
Fig. 4 etches the schematic diagram of groove for what the embodiment of the present invention provided in N-type epitaxial loayer;
Fig. 5 forms the schematic diagram of P type epitaxial loayer for what the embodiment of the present invention provided on groove and mask layer;
Fig. 6 recovers the P type silicon tagma be etched away and the schematic diagram that forms the P type drift region of bottom, P type silicon tagma for what the embodiment of the present invention provided in the groove of N-type epitaxial loayer;
The structural representation of the N-type silicon substrate after the removal mask layer that Fig. 7 provides for the embodiment of the present invention and upper each layer thereof;
The photoetching in the top window of P type drift region that Fig. 8 provides for the embodiment of the present invention, the schematic diagram that etches the figure that defines N-type source region;
Fig. 9 forms the schematic diagram in N-type source region for what the embodiment of the present invention provided in P type drift region;
Grow on polysilicon layer insulating medium layer the photoetching that Figure 10 provides for the embodiment of the present invention, etching form the schematic diagram of contact hole;
The growing metal layer on insulating medium layer and in contact hole that Figure 11 provides for the embodiment of the present invention forms the schematic diagram of source electrode and drain electrode.
Embodiment
Below in conjunction with Figure of description, a kind of embodiment of making the method for super node MOSFET that the embodiment of the present invention is provided describes.
A kind of method of making super node MOSFET that the embodiment of the present invention provides, specifically comprises the following steps:
Step 1, injects P type ion to the mask layer that is etched with window, forms P type silicon tagma in the N-type silicon epitaxy layer under this mask layer;
Step 2, with described mask layer on the correspondence position of window etch groove, described groove penetrates described P type silicon tagma and arrives in N-type epitaxial loayer;
Step 3, in this groove, extension is mixed the silicon materials of p type impurity until groove is filled, and recovers the P type silicon tagma being etched away and the P type drift region that forms bottom, P type silicon tagma;
Step 4, removes mask layer;
Step 5 forms two N-type silicon source regions in P type silicon tagma;
Step 6, growth and etching insulating medium layer on the N-type silicon epitaxy layer after removing mask layer, form contact hole, growing metal layer on insulating medium layer and in contact hole, the source electrode of formation super node MOSFET;
Step 7, on N-type silicon substrate, growing metal layer forms the drain electrode of super node MOSFET.
In embodiments of the present invention, before above-mentioned steps one, can also comprise the steps:
As shown in Figure 1, first the N-type silicon epitaxy layer 102 of growing on N-type silicon substrate 101, this N-type silicon epitaxy layer 102 is monocrystalline silicon, the resistivity of this N-type silicon epitaxy layer 102 is generally 10～100 Ω-cm. sacrificial oxide layer (not shown in figure 1) of then growing on N-type silicon epitaxy layer 102, and then removal sacrificial oxide layer, to reach the surperficial object of clean N-type silicon epitaxy layer 102, then on the N-type silicon epitaxy layer 102 after surface is cleaned, adopt the technique growth grid oxic horizon 103 of dry oxidation, the thickness of this grid oxic horizon 103 is generally between 0.05～0.20 μ m, then growing polycrystalline silicon layer 104 on grid oxic horizon 103, its thickness is generally 0.40～1.00 μ m, then, the mask layer 105 of growing on polysilicon layer 104, preferably, mask layer 105 can be silicon nitride, its thickness is generally between 0.05～0.30 μ m.
Finally, as shown in Figure 2, etching window with forming the corresponding polysilicon layer 104 in region of N-type silicon epitaxy layer 102 of P type drift region and the relevant position in mask layer 105, and etching grid oxide layer 103 not.
The detailed process that forms P type silicon tagma in above-mentioned steps one is as follows: to the mask layer that is etched with window, inject P type ion and drive in, P type ion can be B ion, In ion etc.As shown in Figure 3, at the window area of mask layer 105, P type ion sees through grid oxic horizon 103 and is injected in N-type silicon epitaxy layer 102, and the dosage that is wherein injected into the P type ion in N-type silicon epitaxy layer 102 is generally 1E10 ~ 1E13atoms/cm
2, in all the other regions of mask layer 105, the P type ion of injection is all intercepted by mask layer 105.When P type ion is injected in N-type silicon epitaxy layer 102 through grid oxic horizon 103, grid oxic horizon 103 on the one hand can scattering P type ion, make it to slow down, prevent that P type Implantation is excessively dark, on the other hand, in the time of can also preventing that P type ion is directly injected into N-type silicon epitaxy layer 102, the lattice of the monocrystalline silicon in damage N-type silicon epitaxy layer 102.Then, again the P type ion injecting is driven in, the process driving in is characteristic from area with high mercury to low concentration region that utilize ion to spread from, at high temperature, if temperature is between 1000 ℃ to 1200 ℃, make the P type ion injecting to N-type epitaxial loayer 102, not inject the regional diffusion of P type ion, thereby in N-type silicon epitaxy layer 102, form P type silicon tagma 106.
In above-mentioned steps two, etch the detailed process of groove as shown in Figure 4, first the oxide layer of the correspondence position of the window on grid oxic horizon 103 and mask layer 105 is etched away, then on N-type silicon epitaxy layer 102 and mask layer 105, the correspondence position of window etches groove, groove width is generally 0.18um to 5.0um, more than gash depth is about 40 μ m.
The detailed process of the P drift region of the P type silicon tagma that in above-mentioned steps three, recovery is etched away and formation bottom, P type silicon tagma is: as shown in Figure 5, first on mask layer 105 and in groove, extension is mixed the silicon materials of p type impurity, be about to the fluted N-type substrate of etching and put into the cavity that is filled with the silicon material gas that mixes p type impurity, on mask layer 105, mask layer 105, the sidewall of the window in polysilicon layer 104 and grid oxic horizon 103, thereby trenched side-wall and bottom start the silicon materials formation P type silicon epitaxy layer 107 that extension is mixed p type impurity simultaneously, wherein, the resistivity of P type silicon epitaxy layer 107 is generally 10～100 Ω cm., because groove width is much smaller than gash depth, the institute that therefore can be impregnated in very soon the silicon materials of p type impurity in groove and window fills up.Then, as shown in Figure 6, the part of etching P type silicon epitaxy layer on mask layer 105 and in window, until the surface of P type silicon epitaxy layer is concordant with groove opening surface, recovers the P type silicon tagma 106 being etched away and the P type drift region 108 that forms 106 bottoms, P type silicon tagma.
In step 2 and step 3, employing needs the region that forms P type drift region to etch groove in N-type silicon epitaxy layer, then in groove, deposition is mixed the silicon materials of P type ion until groove is filled formation P type drift region, substitute in prior art by N-type Grown N-type epitaxial loayer with inject P type ion repeatedly mutually alternately and the technical process of the P type doping P type drift region that drives in to form, overcome the problem of super node MOSFET complex manufacturing technology in prior art, thereby reduced the production cost of super node MOSFET.
The concrete practice of removing mask layer in above-mentioned steps four can be: if mask layer is silicon nitride layer, general employing concentration is 86%(percentage by weight), temperature is that the phosphoric acid corrosion of 165 ℃ falls silicon nitride layer, and after removal mask layer, the structure of N-type silicon substrate 101, N-type silicon epitaxy layer 102, grid oxic horizon 103, polysilicon layer 104, P type silicon tagma 106 and P type drift region 108 as shown in Figure 7.
After above-mentioned steps four, before step 5, can also carry out following step: as shown in Figure 8, in the window above each P type silicon tagma 106, apply photoresist 109 and make the figure that defines two N-type silicon source regions by lithography.
Further, the detailed process that forms two N-type silicon source regions in above-mentioned steps five is: as shown in Figure 9, in polysilicon layer 104 and window, inject N-type ion, this N-type ion can be P, As plasma.Region covered by photoresist in P type silicon tagma 106, because the N-type ion injecting is intercepted by photoresist, in this region, not having N-type ion is injected into, and region not covered by photoresist in P type silicon tagma 106, thereby can inject N-type ion, form N-type silicon source region 110, the dosage of the N-type ion of injection is generally 1E14 ~ 1E16atoms/cm
2, similarly, in polysilicon layer 104, also can inject N-type ion, can reduce like this resistance of polysilicon layer 104, due to, the grid of MOSFET (not shown in Fig. 8) is arranged in polysilicon layer 104, and therefore, resistance has reduced.Then, remove the photoresist (not shown in Fig. 9) in window, and the N-type ion injecting is driven in, and make the border, side that drives in N-type silicon source region 110 afterwards slightly surpass the border, side of P type drift region 108.
The specific practice that forms the source electrode of super node MOSFET in above-mentioned steps six and form the drain electrode of super node MOSFET in step 7 is: as shown in figure 10, first the insulating medium layer 111 of growing on polysilicon layer 104 and in described window, the insulating medium layer 111 in photoetching, etching window polysilicon layer 104 is wrapped and expose two N-type silicon source regions 110 and two N-type silicon source regions 110 between P type silicon tagma 106 form contact holes; Then, as shown in figure 11, on insulating medium layer 111 and in contact hole, growing metal layer forms source electrode 112, and this metal level can be aluminium (98.5%) silicon (1%) copper (0.5%) alloy (percentage by weight); And on N-type silicon substrate 101 growing metal layer, form drain electrode 113.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (9)
1. a method of making super knot metal-oxide semiconductor fieldeffect transistor MOSFET, is characterized in that, comprising:
To the mask layer that is etched with window, inject P type ion and drive in, in the N-type silicon epitaxy layer under described mask layer, forming P type silicon tagma;
With described mask layer on the correspondence position of window etch groove, described groove penetrates described P type silicon tagma and arrives in N-type epitaxial loayer;
In described groove, extension is mixed the silicon materials of p type impurity until groove is filled, and recovers the P type silicon tagma being etched away and the P type drift region that forms bottom, P type silicon tagma;
Remove described mask layer;
In P type silicon tagma, form two N-type silicon source regions;
Growth and etching insulating medium layer on N-type silicon epitaxy layer after removing mask layer, form contact hole, growing metal layer on described insulating medium layer and in contact hole, the source electrode of formation super node MOSFET;
On N-type silicon substrate, growing metal layer forms the drain electrode of super node MOSFET.
2. the method for claim 1, is characterized in that, in described groove, extension is mixed the silicon materials of p type impurity until groove is filled, and recovers the P type silicon tagma being etched away and the P type drift region that forms bottom, P type silicon tagma, specifically comprises:
The silicon materials that on mask layer and in described groove, extension is mixed p type impurity form P type epitaxial loayer until the window in groove and mask layer is filled;
The part of P type epitaxial loayer on mask layer and in described window described in etching, until the surface of P type epitaxial loayer is concordant with groove opening surface, recovers the P type silicon tagma being etched away and the P type drift region that forms bottom, P type silicon tagma.
3. method as claimed in claim 2, is characterized in that, before forming P type silicon tagma, also comprises in N-type silicon epitaxy layer:
The sacrificial oxide layer of growing on N-type silicon epitaxy layer is also removed;
At N-type silicon epitaxy grow successively grid oxic horizon, polysilicon layer and mask layer;
In mask layer and polysilicon layer, etch window.
4. method as claimed in claim 3, is characterized in that, forms N-type silicon source region, specifically comprises:
In window above P type silicon tagma, apply photoresist and make the figure that defines two N-type silicon source regions by lithography;
Window to polysilicon layer and top, P type silicon tagma injects N-type ion;
Remove the photoresist in window and the N-type ion injecting is driven in.
5. method as claimed in claim 4, is characterized in that, growth and etching insulating medium layer on the N-type silicon epitaxy layer after removing mask layer, form contact hole, growing metal layer on described insulating medium layer and in contact hole, the source electrode of formation super node MOSFET, specifically comprises:
The insulating medium layer of growing on polysilicon layer and in described window, the insulating medium layer in photoetching, etching window polysilicon layer is wrapped and expose two N-type silicon source regions and two N-type silicon source regions between P type silicon tagma form contact hole;
Growing metal layer in insulating medium layer and contact hole.
6. the method as described in claim 1-5 any one, is characterized in that, the gash depth etching is more than 40 μ m.
7. the method as described in claim 3-5 any one, is characterized in that, adopts the technique of the dry oxidation grid oxic horizon of growing on N-type silicon epitaxy layer.
8. the method as described in claim 3-5 any one, is characterized in that, the thickness of described grid oxic horizon is 0.05 μ m～0.2 μ m.
9. the method as described in claim 3-5 any one, is characterized in that, the thickness of described polysilicon layer is 0.4 μ m～1 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210281452.2A CN103579003B (en) | 2012-08-09 | 2012-08-09 | A kind of method making super node MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210281452.2A CN103579003B (en) | 2012-08-09 | 2012-08-09 | A kind of method making super node MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579003A true CN103579003A (en) | 2014-02-12 |
| CN103579003B CN103579003B (en) | 2016-02-03 |
Family
ID=50050512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210281452.2A Active CN103579003B (en) | 2012-08-09 | 2012-08-09 | A kind of method making super node MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103579003B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845576A (en) * | 2015-01-16 | 2016-08-10 | 北大方正集团有限公司 | Super-junction MOSFET making method |
| CN107104050A (en) * | 2016-02-19 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and field-effect transistor of field-effect transistor |
| CN108922851A (en) * | 2018-08-31 | 2018-11-30 | 江苏丽隽功率半导体有限公司 | A kind of trench VDMOS device and preparation method thereof with super-junction structure |
| CN105448722B (en) * | 2014-08-06 | 2019-02-01 | 北大方正集团有限公司 | A kind of production method and semiconductor device of superjunction semiconductor field |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
| CN117612935A (en) * | 2024-01-24 | 2024-02-27 | 北京智芯微电子科技有限公司 | Source region self-aligned injection method of super-junction semiconductor and super-junction semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282007A (en) * | 2002-10-08 | 2004-10-07 | Internatl Rectifier Corp | Super junction device with added charge at top of pylon to enhance ruggedness |
| US20090317959A1 (en) * | 2008-06-23 | 2009-12-24 | Fuji Electric Device Technology Co., Ltd. | Method for manufacturing semiconductor device |
| CN102254850A (en) * | 2010-05-20 | 2011-11-23 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
-
2012
- 2012-08-09 CN CN201210281452.2A patent/CN103579003B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282007A (en) * | 2002-10-08 | 2004-10-07 | Internatl Rectifier Corp | Super junction device with added charge at top of pylon to enhance ruggedness |
| US20090317959A1 (en) * | 2008-06-23 | 2009-12-24 | Fuji Electric Device Technology Co., Ltd. | Method for manufacturing semiconductor device |
| CN102254850A (en) * | 2010-05-20 | 2011-11-23 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448722B (en) * | 2014-08-06 | 2019-02-01 | 北大方正集团有限公司 | A kind of production method and semiconductor device of superjunction semiconductor field |
| CN105845576A (en) * | 2015-01-16 | 2016-08-10 | 北大方正集团有限公司 | Super-junction MOSFET making method |
| CN107104050A (en) * | 2016-02-19 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and field-effect transistor of field-effect transistor |
| CN108922851A (en) * | 2018-08-31 | 2018-11-30 | 江苏丽隽功率半导体有限公司 | A kind of trench VDMOS device and preparation method thereof with super-junction structure |
| CN108922851B (en) * | 2018-08-31 | 2023-09-29 | 江苏丽隽功率半导体有限公司 | Trench type VDMOS device with super junction structure and manufacturing method thereof |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
| CN117612935A (en) * | 2024-01-24 | 2024-02-27 | 北京智芯微电子科技有限公司 | Source region self-aligned injection method of super-junction semiconductor and super-junction semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579003B (en) | 2016-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100834740B1 (en) | Methods of forming field effect transistors having silicon-germanium source and drain regions | |
| CN104217953B (en) | PMOS transistor and preparation method thereof | |
| CN103579003B (en) | A kind of method making super node MOSFET | |
| CN102983171B (en) | The vertical structure without knot surrounding-gate MOSFET device and manufacture method thereof | |
| CN103035521B (en) | Realize the process of few groove-shaped IGBT of sub-accumulation layer | |
| CN105789334A (en) | Schottky barrier semiconductor rectifier and manufacturing method therefor | |
| CN103632974A (en) | Manufacturing method for improving in-plane uniformity of P type LDMOS surface channel device | |
| CN111668312A (en) | Groove silicon carbide power device with low on-resistance and manufacturing process thereof | |
| CN102468176B (en) | Method for making longitudinal region of super junction device | |
| CN103367157A (en) | Preparation method of super junction MOSFET | |
| CN103390545A (en) | Method for increasing drain-source breakdown voltage of trench NMOS and structure of trench NMOS | |
| KR101315699B1 (en) | Power mosfet having superjunction trench and fabrication method thereof | |
| CN100394616C (en) | Integrated high-voltage VDMOS transistor structure and production thereof | |
| CN112951715B (en) | Groove gate structure and preparation method of groove type field effect transistor structure | |
| CN104916686A (en) | VDMOS device and manufacturing method thereof | |
| CN102916047B (en) | SOI body contact structure and the formation method of oxygen corrosion technology are buried in a kind of utilization | |
| CN108054099B (en) | Method for manufacturing semiconductor power device | |
| CN105336612A (en) | Planar VDMOS device and manufacturing method thereof | |
| CN104217956B (en) | PMOS (P-channel metal oxide semiconductor) transistor and manufacture method thereof | |
| CN105810723B (en) | It can realize the structures and methods of the MOSFET of reverse blocking | |
| CN203721734U (en) | Low-VF power MOSFET device | |
| CN103545202B (en) | Pmos transistor and forming method thereof | |
| CN101459132B (en) | Manufacturing process for high voltage planar power MOS device | |
| CN107994077B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN104576311A (en) | Forming and filling method of trenches |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220720 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |