CN105005510B - Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching - Google Patents
Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching Download PDFInfo
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
The invention discloses a kind of error correction protection architectures and method applied to solid state disk resistance-variable storing device caching; the code length of the mapping table of coarseness management is identical as the code length of caching of page data; in data processing, access frequency in the mapping table of coarseness management is more than in the mapping table address information storage to the mapping table cache of fine granularity management of preset value；Data are exchanged as unit of page between mapping table cache and the mapping table of coarseness management of fine granularity management, it will be all placed in the mapping table cache of fine granularity management from one page map information read in the mapping table of coarseness management, latter 10 in the logical address request of input are regard as bits of offset, using the remaining bit in the logical address of input as index bit.The present invention, which efficiently, can be obtained reliably, reads mapping table address information, and the redundant space consumed is limited.
Description
Technical field
The invention belongs to nonvolatile memory resistance-variable storing device design fields, are related to a kind of applied to solid state disk resistive
The error correction protection architecture and method of memory buffer.
Background technology
Caching in solid state hard disk system can effectively reduce access of the host to flash memory, and the performance to improving whole system has
Important function, there are big leakage current, power-off to lose information, high quiet for traditional caching based on dynamic random access memory
The problems such as state power consumption, nonvolatile memory resistance-variable storing device have many advantages, such as that density is high, read or write speed is fast, low-power consumption, are recognized
To be the ideal replacer of dynamic random access memory in solid state hard disk system, but resistance-variable storing device asking there are reliability
Topic, especially the resistance-variable storing device memory of cross array structure, with the increase of array length, crosstalk can be increasing, reliably
Sex chromosome mosaicism is more prominent.
With the development of nonvolatile memory, the caching using nonvolatile memory as External memory equipment is
Become practical, the user data of caching, map information (Physical page are mainly stored in typical caching
Number, abbreviation PPN) and other data such as a small amount of firmware.
It is well known that memory devices only have user's bit error rate to be less than 10-15User demand could be met, although resistance
Transition storage caches raw bit error rate height, but it can be made to meet user's bit error rate by the protection of error correcting code
Requirement.According to error correcting code encoding and decoding principle, the more high so error correcting code redundancy of the longer code check of code length is smaller, for example, bit-errors
Rate is 10-4, use traditional galois field for 2 BCH encoding and decoding, code length needs the redundancy of 30bit when being 4B, and same original ratio
Special error rate, code length is that 4KB redundancies need 416bit, so its redundancy of ecc code length difference differs greatly.
Invention content
It is an object of the invention to overcome the above-mentioned prior art, provides one kind and deposited applied to solid state disk resistive
The error correction protection architecture and method of reservoir caching, the framework and method can efficiently, reliably obtain reading mapping table address letter
Breath, and the redundant space consumed is limited.
In order to achieve the above objectives, the error correction protection architecture of the present invention applied to solid state disk resistance-variable storing device caching
The code length of the mapping table of middle coarseness management is identical as the code length of caching of page data, in data processing, by coarseness pipe
Access frequency is more than in the mapping table address information storage to the mapping table cache of fine granularity management of preset value in the mapping table of reason,
The entry of the mapping table of one coarseness management is spelled by 1024 address mapping table, in the mapping table cache of fine granularity management
Each entry include a map information and a map information error correcting code redundancy；
Data are exchanged as unit of page between mapping table cache and the mapping table of coarseness management of fine granularity management, it will
It is all placed in the mapping table cache of fine granularity management from one page map information read in the mapping table of coarseness management,
In, one page map information is spliced by 1024 map informations, by rear 10 works in the logical address request of input
For bits of offset, using the remaining bit in the logical address of input as index bit.
Error correction guard method of the present invention applied to solid state disk resistance-variable storing device caching includes the following steps：
The logical address request of input is divided into index bit and bits of offset, reflecting for fine granularity management is searched by index bit
Firing table caches, when the logical address request of input is hit in the mapping table cache of fine granularity management, then according to the inclined of input
It moves Address requests and reads corresponding mapping table address information from the page comprising request map information；When the logical address of input
When request is not hit in the mapping table cache of fine granularity management, then found out from the mapping table of coarseness management comprising request
The page of map information then directly will be from the mapping table of coarseness management when the mapping table of fine granularity management is cached with space
It is middle to read the page for including request map information, and the page comprising request map information of reading is pressed into fine granularity management strategy
It writes in the mapping table cache of fine granularity management；When there is no space in the mapping table cache of fine granularity management, then according to coarseness
Strategy writes back to the last page in the mapping table cache of fine granularity management in the mapping table of coarseness management, then again will packet
The page of the map information containing request is write according to fine granularity management strategy in the mapping table cache of fine granularity management, last according to partially
It moves Address requests and reads corresponding mapping table address information from the page comprising request map information.
The mapping table cache of fine granularity management can cache multiple pages of mapping table address information, wherein every page is reflected
Firing table address information is the corresponding flash memory physical address in 1024 continuous logic addresses, in the mapping table address information of every page
The corresponding logical address of first flash memory physical address be this page logical address index；
When the logical address request of access is hit in the mapping table cache of fine granularity management, then corresponded to according to index bit
Call number, the size and page of the first address of storage address map information in resistance-variable storing device, each address information entry
Bias internal obtains required address map information position, wherein required address map information position=resistance-change memory
Size × 1024 × call number+page bias internal of the first address of storage address map information+each address information entry in device
The size of × each address information entry.
The size of each address information entry by an address mapping information and the address mapping information superfluous group of error correcting code
At.
By the Static RAM of directory entry storage to solid state hard disk system, cached data mapping table and mapping
In the storage to the SRAM of solid state hard disk system of table cache index array, the piece of address mapping table information storage to solid state hard disk system
In outer caching resistance-variable storing device.
The invention has the advantages that：
It is of the present invention applied to solid state disk resistance-variable storing device caching error correction protection architecture and method in operation,
The code length of the mapping table of coarseness management is identical as the code length of caching of page data, and by the larger mapping table address of access frequency
In information storage to the mapping table of fine granularity management, it is significantly reduced error correction redundancy loss, while ensureing to map the speed of table access
Degree.In addition, the entry of the mapping table of a coarseness management is spelled by 1024 address mapping table, while in fine granularity management
Mapping table cache and the mapping table of coarseness management between exchange data as unit of page, while one page map information by
1024 map informations are spliced, to effectively improve the hit rate of mapping table cache.To sum up, The present invention reduces reflect
The loss of error correcting code redundant space in turn ensures speed in firing table, is obviously improved to whole solid state hard disk system performance.
Further, the corresponding logical address of first flash memory physical address in the mapping table address information of every page is to be somebody's turn to do
The logical address index of page, the effective speed for improving index reduce the error rate of index.
Description of the drawings
Fig. 1 is the structure chart of the present invention；
Fig. 2 is the flow chart of the present invention；
Fig. 3 is the management structure chart of the mapping table cache of fine granularity management in the present invention；
Fig. 4 is that index array protects solid state hard disk system Organization Chart in the hybrid error correction of on piece.
Specific implementation mode
The present invention is described in further detail below in conjunction with the accompanying drawings：
With reference to figure 1, coarse grain in the error correction protection architecture of the present invention applied to solid state disk resistance-variable storing device caching
The code length for spending the mapping table of management is identical as the code length of caching of page data, in data processing, by reflecting for coarseness management
Access frequency is more than in the mapping table address information storage to the mapping table cache of fine granularity management of preset value in firing table, and one thick
The entry of the mapping table of granular management is spelled by 1024 address mapping table, each item in the mapping table cache of fine granularity management
Mesh includes the error correcting code redundancy of a map information and a map information；The mapping table cache of fine granularity management with
Exchange data between the mapping table of coarseness management are as unit of page, one page for will being read from the mapping table of coarseness management
Map information is all placed in the mapping table cache of fine granularity management, wherein one page map information is by 1024 mapping tables
Information is spliced, and regard latter 10 in the logical address request of input as bits of offset, will be surplus in the logical address of input
Remaining position is as index bit.
With reference to figure 2, it is of the present invention applied to solid state disk resistance-variable storing device caching error correction guard method include with
Lower step：
The logical address request of input is divided into index bit and bits of offset, reflecting for fine granularity management is searched by index bit
Firing table, when the logical address request of input is hit in the mapping table cache of fine granularity management, then according to the offset of input
Location request reads corresponding mapping table address information from the page comprising request map information；When the logical address request of input
When not hit in the mapping table cache of fine granularity management, then found out from the mapping table of coarseness management comprising request mapping
The page of table information then will directly be read when the mapping table of fine granularity management is cached with space from the mapping table of coarseness management
Go out the page for including request map information, and the page comprising request map information of reading is write by fine granularity management strategy
In the mapping table cache of fine granularity management；When there is no space in the mapping table cache of fine granularity management, then according to coarse-grained policies
Last page in the mapping table cache of fine granularity management is write back in the mapping table of coarseness management, then will include to ask again
The page of map information is asked to be write in the mapping table cache of fine granularity management according to fine granularity management strategy, finally according to offset ground
Location request reads corresponding mapping table address information from the page comprising request map information.
With reference to figure 3, the mapping table cache of fine granularity management can cache multiple pages of mapping table address information, wherein every
The mapping table address information of one page is the corresponding flash memory physical address in 1024 continuous logic addresses, the mapping table of every page
The corresponding logical address of first flash memory physical address in the information of location is that the logical address of this page indexes；When access logically
When location request is hit in the mapping table cache of fine granularity management, then according in the corresponding call number of index bit, resistance-variable storing device
The first address of storage address map information, the size of each address information entry and page bias internal obtain required address of cache
Table information position, wherein storage address mapping table is believed in required address map information position=resistance-variable storing device
Size × 1024 × call number+page bias internal of the first address of breath+each address information entry × each address information entry
Size, the size of each address information entry by an address mapping information and the address mapping information error correcting code redundancy group
At.
With reference to figure 4, by the Static RAM of directory entry storage to solid state hard disk system, cached data mapping
In table and mapping table cache index array storage to the SRAM of solid state hard disk system, address mapping table information storage to solid state disk
It is cached in resistance-variable storing device outside the piece of system.
Claims (3)
1. a kind of error correction protection architecture applied to solid state disk resistance-variable storing device caching, which is characterized in that coarseness management
The code length of mapping table is identical as the code length of caching of page data, in data processing, will be visited in the mapping table of coarseness management
Ask that frequency is more than in the mapping table address information storage to the mapping table cache of fine granularity management of preset value, a coarseness management
The entry of mapping table be spliced by 1024 address mapping table, each entry in the mapping table cache of fine granularity management is wrapped
Error correcting code redundancy containing a map information and a map information；
Data are exchanged as unit of page between mapping table cache and the mapping table of coarseness management of fine granularity management, it will be from thick
One page map information read in the mapping table of granular management is all placed in the mapping table cache of fine granularity management, wherein
One page map information is spliced by 1024 map informations, and rear 10 conducts in the logical address request of input is inclined
Displacement, using the remaining bit in the logical address of input as index bit.
2. a kind of error correction guard method applied to solid state disk resistance-variable storing device caching, which is characterized in that be based on claim 1
The error correction protection architecture for being applied to solid state disk resistance-variable storing device caching, includes the following steps：
The logical address request of input is divided into index bit and bits of offset, the mapping table of fine granularity management is searched by index bit
Caching, when the logical address request of input is hit in the mapping table cache of fine granularity management, then logically according to input
Location request reads corresponding mapping table address information from the page comprising request map information；When the logical address request of input
When not hit in the mapping table cache of fine granularity management, then found out from the mapping table of coarseness management comprising request mapping
The page of table information is then directly read from the mapping table of coarseness management when the mapping table of fine granularity management is cached with space
Include the page of request map information, and the page comprising request map information of reading is write carefully by fine granularity management strategy
In the mapping table cache of granular management；It, then will according to coarse-grained policies when there is no space in the mapping table cache of fine granularity management
Last page in the mapping table cache of fine granularity management writes back in the mapping table of coarseness management, then will include request again
The page of map information is write according to fine granularity management strategy in the mapping table cache of fine granularity management, finally according to logical address
It asks to read corresponding mapping table address information from the page comprising request map information；
The mapping table cache of fine granularity management can cache multiple pages of mapping table address information, wherein the mapping table of every page
Address information is the corresponding flash memory physical address in 1024 continuous logic addresses, and in the mapping table address information of every page
The corresponding logical address of one flash memory physical address is that the logical address of this page indexes；
When the logical address request of access is hit in the mapping table cache of fine granularity management, then according to the corresponding rope of index bit
In quotation marks, resistance-variable storing device in the first address of storage address map information, the size of each address information entry and page partially
Move to obtain required address map information position, wherein in required address map information position=resistance-variable storing device
Size × 1024 × call number+page bias internal of the first address of storage address map information+each address information entry × every
The size of a address information entry；
By the Static RAM of directory entry storage to solid state hard disk system, cached data mapping table and mapping table are slow
It deposits in index array storage to the SRAM of solid state hard disk system, it is slow outside the piece of address mapping table information storage to solid state hard disk system
It deposits in resistance-variable storing device.
3. the error correction guard method according to claim 2 applied to solid state disk resistance-variable storing device caching, feature exists
In each address information entry is made of the error correcting code redundancy of an address mapping information He the address mapping information.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510382445.5A CN105005510B (en) | 2015-07-02 | 2015-07-02 | Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching |
| PCT/CN2015/098137 WO2017000517A1 (en) | 2015-07-02 | 2015-12-21 | Error correction protection architecture and method applied to resistive random access memory cache of solid state disk |
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| CN201510382445.5A CN105005510B (en) | 2015-07-02 | 2015-07-02 | Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching |
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| CN105005510B (en) * | 2015-07-02 | 2018-07-17 | 西安交通大学 | Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching |
| CN106681932B (en) * | 2016-11-14 | 2020-10-16 | 合肥兆芯电子有限公司 | Memory management method, memory control circuit unit and memory storage device |
| CN108595349B (en) * | 2017-12-28 | 2020-01-31 | 贵阳忆芯科技有限公司 | Address translation method and device for mass storage device |
| CN109828931B (en) * | 2019-01-25 | 2020-12-01 | 深圳忆联信息系统有限公司 | DRAM fragment management method and device thereof |
| CN110109873B (en) * | 2019-05-08 | 2023-04-07 | 重庆大学 | File management method for message queue |
| CN113450863B (en) * | 2021-07-09 | 2024-09-10 | 上海交通大学 | Method for resisting hard failure error of resistive random access memory |
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| WO2017000517A1 (en) | 2017-01-05 |
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