CN102063340A - Method for improving fault-tolerant capability of high-speed cache of magnetoresistance RAM (Random Access Memory) - Google Patents
Method for improving fault-tolerant capability of high-speed cache of magnetoresistance RAM (Random Access Memory) Download PDFInfo
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Abstract
The invention provides a method for improving the fault-tolerant capability of a high-speed cache of a magnetoresistance RAM (Random Access Memory), which is capable of effectively correcting or tolerating random storing and writing errors and realizing a lower storing and writing voltage or a higher storing and writing speed. The storing and writing operation substitutes traditional storing and writing operation by adopting a recursive write-read-check technology to correct random storing and writing errors caused by changing the storing and writing capacity limit or the storing and writing speed. The write-read-check technology means that data are written into a high-speed cache of an MRAM (Magneto-Resistive Random Access Memory), immediately read out and compared with written data; and the write-read-check operation is repeated until all data bits are rightly programmed in case of failures. Based on the write-read-check operation, error-checking codes or error record buffer logic is added to the MRAM high-speed cache, the fault-tolerant capability of the MRAM high-speed cache is enhanced and processor performance degradation brought by the write-read-check operation is reduced.
Description
Technical field
The invention belongs to storer and Computer Architecture technical field, particularly a kind of method that improves the anti-wrong ability of magneto-resistor random access memory high-speed cache.
Background technology
Magneto-resistor random access memory (MRAM) is one of novel memory technology of concerned by the industry.Compare with the legacy memory technology, but advantage such as that the magneto-resistor random access memory has is non-volatile, the high micro ability of storage density is strong, read or write speed is fast and quiescent dissipation is low.Therefore, the magneto-resistor random access memory is considered to the most competitive embedded memory technology under the following smaller szie integrated circuit technology, is with a wide range of applications.Wherein, high-speed cache is the main application fields of magneto-resistor random access memory on the sheet of high-performance processor.Adopt the magneto-resistor random access memory to replace high-speed cache on the static RAM design sheet, can effectively improve buffer memory capacity on the sheet, to alleviate serious day by day " storage wall " problem.Simultaneously, bottlenecks such as the power consumption of high-performance processor and thermal design also can further be improved or alleviate to the magneto-resistor random access memory.
Magnetic tunnel-junction is the essential information storage unit of magneto-resistor random access memory.Each magnetic tunnel-junction is made up of up and down two ferromagnetic layers and middle tunnel barrier layer, can change the storage of its resistance states realization information by Current Control.But current research shows that there is the limitation of the technology that is difficult to overcome in the tolerance limit of writing of magneto-resistor random access memory.When depositing of magneto-resistor random access memory write overtension, cause the permanent failure of magnetic tunnel-junction easily; Simultaneously, deposit and write that voltage is low can to cause a large amount of write errors of depositing at random again.Therefore, the tolerance limit of writing of magneto-resistor random access memory has been subjected to serious threat, how to improve and writes the key that tolerance limit has become the success of magneto-resistor random access memory technology.In addition, the writing rate of depositing that write error also can improve the magneto-resistor random access memory is deposited in tolerance at random.
Summary of the invention
Technical matters to be solved by this invention provides a kind of method that improves the anti-wrong ability of magneto-resistor random access memory high-speed cache, can effectively correct or tolerates and deposit write error at random, realizes that lower depositing write voltage or deposit writing rate faster.
The inventive method reduces that depositing of MRAM high-speed cache write voltage or writing rate is deposited in raising, corrects simultaneously or the random error that write operation produces is deposited in tolerance.Correct and to deposit write error at random and adopt the write operation of depositing that recursion " writes-read-verification ".Be operating as the basis with " writing-read-verification ", utilize the protection of error-checking code homogeneous to realize that the MRAM high-speed cache is fault-tolerant; It is flexible and efficient fault-tolerant perhaps to utilize error logging to be buffered between data cached group, reduces and writes MRAM high-speed cache number of times.
The present invention improves the method for the anti-wrong ability of magneto-resistor random access memory high-speed cache, and the write operation of depositing of MRAM high-speed cache adopts recursion " to write-read-verification " mode, may further comprise the steps:
Step 1: with data D
wWrite the MRAM high-speed cache;
Step 2: the data that write are read, be kept in the register of MRAM high-speed cache;
Step 3: relatively also judge the data D that is written to the MRAM high-speed cache
wWhether equate with the data of from the register of MRAM high-speed cache, reading,, jump to step 4 if equate; If unequal, jump to step 1;
Step 4: deposit write operation and finish.
As the preferred embodiments of the present invention, in the MRAM high-speed cache, increase the error-checking code logic, in described step 1, at data D
wWrite before the MRAM high-speed cache, at first with these data D
wCarry out the error-checking code coding and generate checking data, then with this checking data and the data D that will write
wWrite the MRAM high-speed cache simultaneously; In described step 2, when sense data, after the error-checking code decoding and error, obtain the data D that reads
r, and then with these data D
rWith the data D that writes
wCompare;
As the preferred embodiments of the present invention, in the MRAM high-speed cache, increase the error logging logic, the described write operation of depositing may further comprise the steps:
Step 1: the tag array of visit MRAM high-speed cache, the physical address of acquisition hiting data piece;
Step 2: the MRAM high-speed cache is carried out once " writing-read-verification " operation, relatively and analyze misdata figure place and the address that write operation is deposited in this time;
Step 3: with step 2 while, the read error record buffer memory, collect error logging unit number available in this error logging group, described available error logging unit comprises: invalid error logging unit and the effective error logging unit that belongs to same visit data piece;
Step 4: relatively deposit the misdata figure place of write operation and available error logging unit number,, then jump to step 2 if available error logging unit number is not enough to the storage errors data; If available error logging unit number can be stored all misdatas, then upgrade the error logging buffer memory, the content of described renewal comprises that new misdata address of storage and the significance bit of putting the error logging unit that does not re-use are invalid;
Step 5: deposit write operation and finish.
As the preferred embodiments of the present invention, described error logging buffer memory comprises tag array and data array, and described each address of depositing write error at random is stored in the error logging unit of error logging buffer memory;
As the preferred embodiments of the present invention, described each error logging unit comprises: significance bit, data block index and three parts of address information, wherein, significance bit and data block index stores are in tag array, address information is stored in the data array, make mistakes ID number of caching data block of described data block index stores, and the address of misdata position in this data block of address information data storage;
As the preferred embodiments of the present invention, the mode that the data organization employing group in the described error logging buffer memory links to each other, promptly all misaddress recorded informations of the space cache data blocks of facing mutually are distributed in same group.
The method that the present invention improves the anti-wrong ability of magneto-resistor random access memory high-speed cache has the following advantages at least: the present invention adopts recursion " to write-read-verification " the deposit write operation of technology generation for usually simple MRAM high-speed cache, promptly after data are write the MRAM high-speed cache, read immediately, and with write data contrasts; If make mistakes, it is correct until all data bit programmings then to repeat " writing-read-verification " operation.Be accompanied by MRAM and deposit and write voltage and reduce and to take place owing to MRAM deposits write error at random, and adopt recursion " writing-read-verification " can make the data in the MRAM high-speed cache guarantee under the situation of other protection mechanisms that it deposits the correctness of write operation not having.Adopt error-checking code or error logging buffer memory to increase MRAM high-speed cache fault-tolerant ability, significantly reduce by increasing the magneto-resistor random access memory and write tolerance limit and repeat to deposit the performance decline that write operation brings.
Description of drawings
Fig. 1 is the entire block diagram of technical solution of the present invention;
Fig. 2 is the process flow diagram that the present invention " writes-read-verification " operation;
Fig. 3 adopts the data flowchart of error-checking code protection for the present invention;
Fig. 4 is the structural representation of the error logging buffer memory of MRAM cache design of the present invention;
Fig. 5 is the structural representation of error logging cache read operation of the present invention;
Fig. 6 utilizes the MRAM cache read operational flowchart of error logging buffer memory for the present invention;
Fig. 7 utilize for the present invention the error logging buffer memory the MRAM buffer memory deposit the write operation process flow diagram.
Embodiment
The present invention is primarily aimed at the MRAM high-speed cache and writes tolerance limit and improve, tolerance MRAM high-speed cache owing to deposit write voltage reduce cause deposit the write error defective at random.See also Fig. 1, the present invention adopts " writing-read-verification " scheme, can in time detect and revise all and deposit write error at random.Meanwhile, adopt two kinds of fault-tolerant design methods to alleviate because the processor performance that " writing-read-verification " postpones to be caused loses problem.By " writing-read-verification " scheme and auxiliary fault-tolerant design method, present invention can be implemented under the situation that influences system performance hardly, tolerate the higher write error ratio of defects of depositing at random, thereby significantly improve the tolerance limit of writing of MRAM high-speed cache.Below in conjunction with accompanying drawing the method that the present invention improves the anti-wrong ability of magneto-resistor random access memory high-speed cache is described in detail:
The present invention adopts recursion " to write-read-verification " the deposit write operation of technology generation for usually simple MRAM high-speed cache, guarantees the correctness of depositing the write operation programming data.Described " writing-read-verification " technology refers to read immediately after data are write the MRAM high-speed cache, and with write data contrasts; If make mistakes, it is correct until all data bit programmings then to repeat " writing-read-verification " operation.Be accompanied by the write operation of depositing that MRAM deposits and take place owing to MRAM deposits write error at random, adopt " writing-read-verification " technology of recursion in time to discern to deposit write error at random and corrected, thereby the correctness that the write operation programming data is deposited in assurance, see also below shown in Figure 2, the concrete step of introducing " writing-read-verification ":
1. with data D
wWrite the MRAM high-speed cache;
2. the data that write are read, be kept in the register of MRAM high-speed cache;
3. relatively also judge the data D that is written to the MRAM high-speed cache
wWith from the MRAM high-speed cache
Whether the data of reading in the register equate, if equate, jump to step 4; If unequal, jump to step 1;
4. depositing write operation finishes.
In above-mentioned steps, be written to the data D of MRAM high-speed cache
wCan temporarily be kept in the register of MRAM high-speed cache with the data of from the register of MRAM high-speed cache, reading.
Need to prove: in " writing-read-verification " operating process, will forbid the MRAM high-speed cache is conducted interviews, and normally move with the integrality and the program that guarantee data.But, because the delay of " writing-read-verification " operation is longer, simply use this scheme will cause long write delay, thereby influence the overall performance level of MRAM high-speed cache.For this reason, the present invention adopts error-checking code (ECC) to alleviate " writing-read-verification " influence to the MRAM cache performance, and is specific as follows.
Described " writing-read-verification " technology refers to read immediately after data are write the MRAM high-speed cache, and with write data contrasts; If make mistakes, it is correct until all data bit programmings then to repeat " writing-read-verification " operation.Adopt error-checking code protection MRAM high-speed cache, but Enhanced MRA M is to depositing the tolerance power of write error at random.When the mistake among the MRAM is protected by error-checking code and can be recovered correct data, then stop follow-up " writing-read-verification " recurrence, thereby alleviate because recursion " is write-read-verification " technology and caused the influence of write delay to the overall performance of MRAM high-speed cache.The error-checking code resist technology mainly is applicable to and deposits the relatively low situation of write error rate at random, has higher efficiency-cost ratio.
Below, see also shown in Figure 3ly, it is for adopting " writing-read-verification " operational flowchart of error-checking code protection, and its step of depositing write operation is as follows:
1. the data D that will write
wCarry out the error-checking code coding and generate checking data, then with D
wWrite the MRAM high-speed cache simultaneously with checking data;
2. the data that write (are comprised the data D that writes
wWith checking data) read, through the data D that obtains after the error-checking code decoding and error to read
r
3. judge the data D that writes
wWith the data D that reads
rValue whether equate, if equate, jump to step 4; Otherwise, jump to step 1;
4. depositing write operation finishes.
The read operation of the MRAM high-speed cache of being protected by error-checking code needs to be written to the data in the MRAM high-speed cache and reads simultaneously through the checking data that the error-checking code programming generates, through obtaining correct data after the error-checking code decoding and error.The protection of employing error-checking code can effectively reduce the recurrence number of times of " writing-read-verification " recursive operation, thereby reduces the delay of depositing write operation of MRAM high-speed cache, and then reduces the performance loss of MRAM high-speed cache.
Yet need to prove, adopt the technical scheme of error-checking code protection MRAM high-speed cache, can only use depositing at random under the lower situation of write error ratio of defects, thus effectively guarantee the MRAM high-speed cache write tolerance limit and performance.But, when depositing the write error rate at random when higher, because the fault-tolerant dirigibility shortcoming of error-checking code will cause performance loss and expend rising.
For this reason, the invention provides a kind of fault-tolerant design method with higher flexibility, i.e. error logging buffer memory, it can be tackled in the tolerance limit of writing of depositing at random under the higher situation of write error rate and improve problem.
See also shown in Figure 4, the structured flowchart of the error logging buffer memory that proposes for the present invention.Wherein, the MRAM high-speed cache designs with reference to traditional cache, and adopts " writing-read-verification " technology to discern and correct MRAM to be cached at and to deposit the random error that produces in the write operation process; Described error logging buffer memory adopts and the similar architecture design of high-speed cache, difference is: the address of all misdata positions in its store M RAM high-speed cache, in case of necessity, provide the misdata bit address to assist the MRAM high-speed cache to realize the fault-tolerant of whole cache systems.
As shown in Figure 4, described error logging buffer memory and traditional buffer memory design class seemingly comprise tag array and data array two parts.Each address of depositing write error at random is stored in the error logging unit of error logging buffer memory.Each error logging unit comprises: significance bit, data block index and three parts of address information.Wherein, significance bit and data block index stores are in tag array, and address information is stored in the data array.Significance bit is represented the state of this error logging unit, and " 0 " represents that this record cell is invalid, and " 1 " represents that this record cell is effective.Make mistakes ID number of caching data block of data block index stores, and the address of misdata position in this data block of address information data storage.Therefore,, just can obtain all the misdata positions in this visit data piece, realize error correction by the data block of comparison cache access and the ID of the data block index in the error logging buffer memory.
The mode that data organization employing group in the error logging buffer memory of the present invention links to each other, that is: all misaddress recorded informations of the cache data blocks that the space is faced mutually are distributed in same group, do not expend so that searching of misdata bit address significantly do not increased system design.The error logging cache access and the matching way of the continuous pattern of group, as shown in Figure 5, the physical address of cache data blocks is interpreted as index and piece ID two parts.According to the data bit of index part, can judge and visit which error logging group.After obtaining the error logging group, all valid data piece ID in this error logging group are read and compare with visit data piece ID, if the two is identical, illustrates that then this error logging stored the misdata bit address in the visit data piece, thereby obtain this wrong error correction information.
The link to each other grade of mode of described error logging buffer memory group can be according to the structure of error rate and high-speed cache and corresponding adjustment.The different groups grade that links to each other, corresponding different fault-tolerant grade and system design costs.
The present invention adopts the error logging buffer memory to protect the MRAM high-speed cache, is in order to reduce the recurrence number of times of " writing-read-verification " operation equally.Like this, the read-write operation of MRAM high-speed cache need increase the visit to the error logging buffer memory, and its read-write operation need be done corresponding adjustment.The data flowchart that reads the MRAM high-speed cache that is shown in Figure 6.The concrete operations step is as follows:
1. visit the tag array of MRAM high-speed cache, obtain the physical address of hiting data piece;
2. read the data in the hiting data piece;
3. with step 2 while, the read error record buffer memory according to the physical address of visit data piece, is collected the misdata bit address that all belong to this visit data piece;
4. revise all the misdata positions in the visit data piece;
5. read operation is finished.
Figure 7 shows that the process flow diagram of depositing write operation of MRAM high-speed cache.Depositing write operation needs to upgrade the error logging buffer memory when writing the MRAM high-speed cache, and it is invalid that original effective error logging is changed to, and upgrade misaddress information.The concrete steps of depositing write operation are as follows:
1. visit the tag array of MRAM high-speed cache, obtain the physical address of hiting data piece;
2. the MRAM high-speed cache is carried out once " writing-read-verification " operation, relatively and analyze misdata figure place and the address that write operation is deposited in this time;
3. with step 2 while, the read error record buffer memory is collected error logging unit number available in this error logging group, and described available error logging unit comprises: invalid error logging unit and the effective error logging unit that belongs to same visit data piece;
4. relatively deposit the misdata figure place of write operation and available error logging unit number,, then jump to step 2 if available error logging unit number is not enough to the storage errors data; Otherwise, upgrade the error logging buffer memory, the content of described renewal comprises that new misdata address of storage and the significance bit of putting the error logging unit that does not re-use are invalid;
5. depositing write operation finishes.
Because the error logging buffer memory only writes down and protect the data bit that write operation is made mistakes of depositing of MRAM high-speed cache, and provide the protection of homogeneous unlike error-checking code, so its fault-tolerant efficient is higher, dirigibility is stronger.The error logging caching technology is deposited write error at random for high probability effective and rational technical solution is provided.
The present invention improves the method for the anti-wrong ability of magneto-resistor random access memory high-speed cache, can effectively correct or tolerates and deposit the mistake of writing at random, realizes that lower depositing write voltage or deposit writing rate faster; Simultaneously, the speed of processor is had no significant effect, can guarantee performance of processors substantially.
The above only is one embodiment of the present invention, it or not whole or unique embodiment, the conversion of any equivalence that those of ordinary skills take technical solution of the present invention by reading instructions of the present invention is claim of the present invention and contains.
Claims (8)
1. one kind is improved the method that magneto-resistor random access memory high-speed cache resists wrong ability; it is characterized in that: it is corrected and to deposit write error at random and adopt the write operation of depositing that recursion " writes-read-verification "; be operating as the basis with " writing-read-verification ", utilize the protection of error-checking code or error logging buffer memory homogeneous to realize that the MRAM high-speed cache is fault-tolerant.
2. one kind is improved the method that magneto-resistor random access memory high-speed cache resists wrong ability, it is characterized in that: the write operation of depositing of MRAM high-speed cache adopts " writing-read-verification " operation, may further comprise the steps:
Step 1: with data D
wWrite the MRAM high-speed cache;
Step 2: the data that write are read, be kept in the register of MRAM high-speed cache;
Step 3: relatively also judge the data D that is written to the MRAM high-speed cache
wWhether equate with the data of from the register of MRAM high-speed cache, reading,, jump to step 4 if equate; If unequal, jump to step 1;
Step 4: deposit write operation and finish.
3. the method for the anti-wrong ability of raising magneto-resistor random access memory high-speed cache as claimed in claim 2 is characterized in that: increase the error-checking code logic in the MRAM high-speed cache, in described step 1, at data D
wWrite before the MRAM high-speed cache, at first with these data D
wCarry out the error-checking code coding and generate checking data, then with this checking data and the data D that will write
wWrite the MRAM high-speed cache simultaneously.
4. the method for the anti-wrong ability of raising magneto-resistor random access memory high-speed cache as claimed in claim 3 is characterized in that: in described step 2, when sense data, obtain the data D that reads after the error-checking code decoding and error
r, and then with these data D
rWith the data D that writes
wCompare.
5. the method for the anti-wrong ability of raising magneto-resistor random access memory high-speed cache as claimed in claim 2 is characterized in that: increase the error logging cache logic in the MRAM high-speed cache, the described write operation of depositing may further comprise the steps:
Step 1: the tag array of visit MRAM high-speed cache, the physical address of acquisition hiting data piece;
Step 2: the MRAM high-speed cache is carried out once " writing-read-verification " operation, relatively and analyze misdata figure place and the address that write operation is deposited in this time;
Step 3: the time with step 2, the read error record buffer memory, collect error logging unit number available in this error logging group, described available error logging unit comprises: invalid error logging unit and the effective error logging unit that belongs to same visit data piece;
Step 4: relatively deposit the misdata figure place of write operation and available error logging unit number,, then jump to step 2 if available error logging unit number is not enough to the storage errors data; Otherwise, upgrade the error logging buffer memory, the content of described renewal comprises that new misdata address of storage and the significance bit of putting the error logging unit that does not re-use are invalid;
Step 5: deposit write operation and finish.
6. the method for the anti-wrong ability of raising magneto-resistor random access memory high-speed cache as claimed in claim 5, it is characterized in that: described error logging buffer memory comprises tag array and data array, and described each address of depositing write error at random is stored in the error logging unit of error logging buffer memory.
7. the method for the anti-wrong ability of raising magneto-resistor random access memory high-speed cache as claimed in claim 6, it is characterized in that: described each error logging unit comprises: significance bit, data block index and three parts of address information, wherein, significance bit and data block index stores are in tag array, address information is stored in the data array, make mistakes ID number of caching data block of described data block index stores, and the address of misdata position in this data block of address information data storage.
8. as the method for the anti-wrong ability of claim 6 or 7 described raising magneto-resistor random access memory high-speed caches, it is characterized in that: the mode that the data organization employing group in the described error logging buffer memory links to each other, promptly all misaddress recorded informations of the space cache data blocks of facing mutually are distributed in same group.
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| CN102063340B (en) | 2012-11-28 |
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