CN113450863B - Method for resisting hard failure error of resistive random access memory - Google Patents
Method for resisting hard failure error of resistive random access memory Download PDFInfo
- Publication number
- CN113450863B CN113450863B CN202110776874.6A CN202110776874A CN113450863B CN 113450863 B CN113450863 B CN 113450863B CN 202110776874 A CN202110776874 A CN 202110776874A CN 113450863 B CN113450863 B CN 113450863B
- Authority
- CN
- China
- Prior art keywords
- address
- remapping
- remapped
- block
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000013519 translation Methods 0.000 claims abstract description 65
- 235000019580 granularity Nutrition 0.000 claims abstract description 44
- 230000015654 memory Effects 0.000 claims abstract description 37
- 238000005457 optimization Methods 0.000 claims abstract description 18
- 238000011084 recovery Methods 0.000 claims abstract description 10
- 238000013500 data storage Methods 0.000 claims abstract description 8
- 230000008859 change Effects 0.000 claims abstract description 3
- 238000012937 correction Methods 0.000 claims description 9
- 238000013507 mapping Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 239000008187 granular material Substances 0.000 claims description 2
- 239000002245 particle Substances 0.000 claims description 2
- 238000012163 sequencing technique Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000005265 energy consumption Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a method for resisting hard failure errors of a resistance change symmetrical memory, which relates to the field of nonvolatile memories based on novel materials, and is based on two granularities irrelevant to a data storage direction, namely the minimum failure data block granularity and RC block granularity, and comprises mixed granularity remapping, failure word translation optimization and remapping information record optimization. The number of reads in the mixed granularity remapping and invalidation word translation optimization data recovery is limited to a maximum of two times, and the utilization rate of storage space is greatly improved by means of remapping information record optimization. The invention can prolong the service life of the resistive random access memory and enhance the reliability of the memory.
Description
Technical Field
The invention relates to the field of nonvolatile memories based on novel materials, in particular to a method for resisting hard failure errors of a resistive random access memory.
Background
At present, two main countermeasures are taken against hard failure errors of the resistive random access memory, one is page removal, namely an operating system directly invalidates a page of a hard failure device; the other is remapping, i.e. the page where the hard failing device is held, but the data block where the hard failure occurs is remapped to another address. However, these two methods are not applicable to resistive symmetrical memories.
The main problem of the page removal method is that the cost is too high and the effect is poor, because the resistive symmetric memory usually adopts the "jumbo page" technology to control the physical layout of the data in the memory array in a displaying way, and the removal of a whole "jumbo page" not only can quickly attenuate the service life of the memory, but also can cause the actual memory space to be greatly reduced, thereby seriously affecting the performance of the main memory. In addition, only a small number of hard failing locations may be present in the removed "jumbo page", and a large portion of the memory locations remain available, which also results in a significant degree of waste.
For the remapping method, the main problem is the directionality of the data remapping. The conventional remapping technology is aimed at a traditional unidirectional access resistance random access memory, and the remapping of data does not need to consider directionality, however, for the resistance random access memory, the access of data comprises two directions of rows and columns, and the remapping of data blocks in a single direction can influence the data blocks in the other direction, so that the problem of data missing occurs during memory access.
Accordingly, those skilled in the art have been working to develop a method for combating hard failure errors in resistive switching symmetrical memories to increase the useful life of the resistive switching symmetrical memories and to increase memory reliability.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to improving the service life of a resistive random access memory and enhancing the reliability of the memory.
To achieve the above object, the present invention provides a method for combating hard failure errors of a resistive random access memory, comprising the steps of: mixed granularity remapping, invalidation word translation optimization and remapping information record optimization;
The method for resisting hard failure errors of the resistance change symmetrical memory is based on two granularities irrelevant to the data storage direction, wherein the two granularities irrelevant to the data storage direction comprise a coarse granularity and a fine granularity; the fine granularity is the minimum invalid data block granularity, the coarse granularity is RC block granularity, the minimum invalid data block is an invalid word, the RC block is a data block surrounded by cache lines in two directions of rows and columns on a storage array, the invalid word is data positioned at the intersection of the rows and the columns of the storage array, and the size of the invalid word is one word (8 bytes);
In the mixed granularity remapping step, all the failed words within one RC block must be mapped into the same remapped RC block, all the failed words must remain in the same relative position in the RC block and the remapped RC block, multiple RC blocks are mapped into one remapped RC block;
In the step of translation optimization of the invalid words, if the relative positions of the invalid words in an original RC block conflict with the relative positions of the invalid words in the RC block to be remapped, adopting a translation scale, and simultaneously translating all the invalid words in the original RC block to the right by the translation scale and then mapping the translated words into the RC block to be remapped;
In the remapping information record optimizing step, when data is loaded into the cache, whether there is remapping of the data or remapping address information of the data is additionally recorded.
Further, the step of mixed particle size remapping includes: hard failure error detection, remapped address recovery, and hard failure error correction;
the hard failure error detection includes: for a 64-bit word, setting an 8-bit storage granule bit width, including a 7-bit SEC error correction code and a one-bit 'remapping flag'; in a read operation, if the "remap flag bit" is "0", the 7-bit SEC error correction code is directly used to recover the data, otherwise, the memory retrieves the correct data from the corresponding remap location.
Further, the remapping address retrieval includes: when the remapping address is extracted from a minimum invalid data block, only the remapping RC block address is stored, and the relative address of the invalid word represents the relative position of the relative address in the remapping RC block by adopting original address data; the remapped addresses are determined by both a coarse-grained remapped RC block address and a fine-grained relative address of the failed word.
Further, the hard failure error correction includes:
in the process of reading data, firstly reading line-wise or column-wise cache line data from a memory, checking the remapping flag bits of all words, if the remapped words exist in the cache line, recovering the remapped addresses of the remapped words from the invalid words, executing another reading operation on the remapped addresses, splicing correct data obtained in the two reading operations together to form complete line-wise or column-wise cache line data, and transmitting the complete line-wise or column-wise cache line data to a processor;
In the process of writing data, firstly checking a remapping flag bit, judging whether an additional writing operation to a remapping address is needed, and if not, writing the data into a destination address; otherwise, a mask is constructed according to the remapping flag bit and the data of the corresponding failure unit is written into the remapping address.
Further, the dead word shift optimization includes: the measurement of the translation scale, the storage of the translation scale and the determination of the translation scale.
Further, the measurement of the translation scale includes: the translation scale of 64 words is used to represent 64 movable positions present in an RC block containing 8 x 8 words, including its original position, and the translation scale of the 64 words is represented by a number from 0to 63, where 0 means not translated.
Further, the storing of the translation scale includes: storing the translation scale and the remapped address in the same invalid word, wherein the storing method comprises the following steps: putting the translation scale into a lossless segment of the invalidation word, and avoiding the segment storing the remapped address; setting a parity check bit for storing the section with the translation scale, so that the section where the parity check bit is positioned can pass through parity check;
Wherein, obtaining the remapped address of the invalid word with the translation scale comprises: firstly, a remapping address is extracted from a failure word through parity check, then a translation scale is extracted through parity check, a new relative position is calculated by utilizing the translation scale, and finally, the remapping address and the new relative position are combined, so that the accurate position of the failure word is determined.
Further, the remapping information record optimization includes a "known remapping" recording mode and a "known remapping address" recording mode;
Setting an extra 1-bit flag bit for each cache line in the cache, wherein the data of the flag bit marks whether the data of the cache line come from two physical addresses or not, and the two physical addresses comprise a destination address and a remapping address; if the flag bit is '0', directly accessing the destination address without pre-reading operation when the data is written back; if the flag bit is '1', performing a pre-reading operation and determining a remapping address when the data is written back;
the record mode of the 'remapping address is known', the position index of the invalid word in the cache line data and the corresponding remapping address are stored into the cache; when the data is written back, the processor issues a write instruction to the destination address and the remapped address according to the specific remapped condition.
Further, the remapping address retrieval includes: distribution of remapping information, recovery of remapping information;
the distribution of remapping information uses a minimum dead data block space to store its remapped addresses, storing only its remapped RC block addresses, including:
retrieving a portion representing the remapped RC block address from the complete remapped address;
Dividing the extracted remapped RC block address into 4 pieces by taking 7 bits as a unit;
Putting 4 pieces of the remapped RC block address division into failure words according to a preset rule; wherein the predetermined rule includes:
dividing the 8-byte storage space of the invalidation word into 8 segments, wherein each segment is 8 bits;
storing the 4 pieces of remapped RC block address division into 4 segments of the failure word respectively, and avoiding segments at most of which two failures are likely to occur;
Setting a parity bit of one bit in a segment storing the remapped RC address so that the bit can be combined with the 7-bit slice to pass the parity check;
setting a parity bit of one bit in the failed segment, so that the storage content of the failed segment cannot pass parity check;
The recovering of the remapping information includes: the method comprises the steps of obtaining an address of a remapped RC block by adopting a parity check method, directly obtaining a relative address of a failure word from an original address, combining the address of the remapped RC block with the relative address of the failure word, and finally obtaining the remapped address;
wherein the obtaining the address of the remapped RC block by the parity check method comprises the following steps: for the segment storing the remapped address in the failure word, reading the parity check bit of the segment, and reading the corresponding 7-bit slice in the segment after the parity check passes; for segments where there are failed cells, their parity bits are read and the parity does not pass through not reading their data.
Further, the determination of the translation scale includes: :
dividing a remapping page into 4 remapping RC blocks, wherein the remapping RC blocks have 16 word positions;
Calculating the allocation quantity of the positions of the words in the remapping RC block according to the condition that the words in the remapping page are allocated, so that a larger value represents the quantity of the invalid words of which the corresponding positions are allocated to other RC blocks, and taking the quantity as the weight of each remapping position;
When a new remapped RC block is allocated to an RC block, a weighted sum of remapped positions at all translation scales is calculated first, the weighted sum is ordered from low to high, translation scales corresponding to low weighted values are given higher priority, all translation scales are traversed from high priority until an available remapped RC block is found at a certain translation scale, and the translation scale is determined to be selected.
The technical scheme provided by the invention is tested by using a self-built simulator and a novel nonvolatile memory simulation tool NVMain, and the beneficial technical effects of the invention are embodied from the two aspects of memory life and access performance and energy consumption:
(1) Memory life: compared with a single granularity remapping method, the memory life under the mixed granularity remapping is improved by 61.1 percent, and the memory life can be further improved by 5 percent through a failure word translation optimization technology;
(2) Access performance and energy consumption: the memory life is obviously prolonged by the mixed granularity remapping method, the loss of access performance and the increase of energy consumption are respectively controlled within 5% and 7%, the access performance loss and the energy consumption increase can be further reduced by the remapping information recording optimization technology, and the access performance and the energy consumption are respectively improved by 8.6% and 24.2% for the 'remapping known' recording mode; for the recording mode with "remapped addresses known", the access performance and the power consumption are improved by 11.4% and 30.5%, respectively.
In the preferred embodiment of the invention, the solution to hard failure errors of the resistive random access memory based on mixed granularity remapping is adopted, so that the service life of the resistive random access memory is effectively prolonged, and the reliability of the memory is greatly enhanced.
The conception, specific structure, and technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, features, and effects of the present invention.
Drawings
FIG. 1 is a diagram of two remapping granularity independent of data storage direction according to a preferred embodiment of the present invention;
FIG. 2 is a diagram of a preferred embodiment of the present invention of a hybrid granularity-based remapping method;
FIG. 3 is a schematic diagram of an optimization technique for dead word translation in accordance with a preferred embodiment of the present invention;
FIG. 4 is a diagram of remapped address recovery according to a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a priority-based translation scale selection strategy in accordance with a preferred embodiment of the present invention.
Detailed Description
The following description refers to a preferred embodiment of the present invention, which will make its technical content more clear and easier to understand. The present invention may be embodied in many different forms of embodiments and the scope of the present invention is not limited to only the embodiments described herein.
In the drawings, like structural elements are referred to by like reference numerals and components having similar structure or function are referred to by like reference numerals. The dimensions and thickness of each component shown in the drawings are arbitrarily shown, and the present invention is not limited to the dimensions and thickness of each component. The thickness of the components is exaggerated in some places in the drawings for clarity of illustration.
As shown in FIG. 1, in a preferred embodiment of the present invention, two relatively real granularities independent of the data storage direction are used to solve the hard failure error of the resistive switching symmetric memory. Since resistive-switching symmetric memory supports bi-directional data access, it is necessary to consider blocks of data in both directions that contain hard failing cells at the same time when employing remapping techniques. In a resistive symmetric memory, there are two relatively practical granularities independent of the direction of data storage, one being the data at the memory array row and column intersection, one word (8 bytes) in size, which is the granularity of a single data transfer of a 64-bit memory bus, while also being the granularity of the smallest failed data block; another granularity, independent of data direction, is a data block surrounded by two cache lines in two directions of rows and columns on the storage array, the size is 512 bytes, and the data block is an RC block.
As shown in fig. 2, a hybrid granularity remapping method in a preferred embodiment of the present invention is described, which has three features, first, that all the failed words within one RC block must be mapped into the same remapped RC block; second, all the failed words must remain in the same relative position in the RC block and the remapped RC block; third, multiple RC blocks may be mapped into one remapped RC block. The mixed granularity remapping combines the advantages of two single granularity remaps. With the first two features, the number of reads at the time of data recovery is limited to a maximum of two times, while with the third feature, the utilization of the storage space is greatly improved.
As shown in FIG. 3, an optimization technique for dead word translation in a preferred embodiment of the present invention is described. Although remapping based on mixed granularity can greatly improve the utilization of remapped space, the requirement that the relative positions of the spent words in the RC block and the remapped RC block must be the same limits further increases in the utilization of remapped space. In fig. 3, two RC blocks cannot be mapped into the same remapped RC block due to the coincidence of the relative positions of the failed words, but as long as all the failed words in RC block 2 are shifted by two units to the right, the two RC blocks can still be mapped into the same remapped RC block. Through this simple translation, more multiple mapping possibilities can be created, increasing the utilization of the remapping space, and thus further increasing the lifetime of the memory.
As shown in FIG. 4, remapped address recovery in a preferred embodiment of the invention is described. Taking a 4GB memory as an example, since the bit width (32 bits) of an address is smaller than the bit width (64 bits) of the smallest failed data block, there is still enough space for one smallest failed data block to store its remapped address. Hybrid granularity remapping means that two addresses are needed to determine the final remapped address, one being the coarse granularity remapped RC block address and the other being the relative address of the fine granularity failed word. Since mixed granularity remapping requires that the relative positions of the failing word in the RC block and the remapped RC block be identical, the relative address of the failing word can be obtained directly from the original address without storing it additionally. A minimum invalid data block, i.e. a invalid word, has at most two invalid units, because the SEC error correction code can only correct one error, and when two invalid errors are detected, the remapping technique is enabled, and fig. 4 illustrates how the remapped addresses are recovered from the invalid word. Where fig. 4 (a) shows a complete remapped address, only the address of the remapped RC block needs to be stored in the failed word, according to the previous analysis. Thus, the part representing the remapped RC block address is first fetched from the complete remapped address (bolded italics); next, the extracted remapped RC block address is divided into 4 pieces in 7-bit units, as shown in fig. 4 (b); finally, the address is placed in the invalidation word with a certain rule, and as shown in fig. 4 (c), the invalidation word of 8 bytes is divided into 8 segments of 8 bits each. Here, assuming the worst case, i.e. two hard failing locations (underlined) are located in two separate segments (segment 2 and segment 4), respectively, to avoid these two failing segments, 4 slices of the remapped RC block are placed in segments 1,3,5 and 6 in the failing word, respectively, and to distinguish which segments in the failing word are used to recover the remapped address, parity is used here. For those segments storing remapped addresses, one parity bit would be combined with the corresponding 7-bit slice while ensuring that the parity can pass, while for those segments where a failed cell exists, the storage would be set to a form where the bit parity cannot pass. By the method, the address of the remapped RC block can be accurately recovered from the failure word, and finally the remapped address is obtained. It is worth noting that all the failing words within one RC block have the same remapped RC address.
As shown in FIG. 5, a priority-based translation scale selection strategy in a preferred embodiment of the present invention is described. Since there are 64 shift scales in an RC block, some reasonable strategy is required to select a relatively optimal shift scale for the failing word from these scales. The basic idea of the selection strategy is to maximize the utilization of the remapping space as much as possible. The technical scheme of the invention provides a translation scale selection strategy based on priority. In this strategy, the allocation of the locations of the individual words in the remapped RC block needs to be recorded. For example, in fig. 5 (a), 4 remapped RC blocks are included in one remapped page, and the remapped RC blocks have 16 word positions, and according to the case that the words are allocated in the figure, the allocation number of the positions of the respective words in the remapped RC blocks is as shown in fig. 5 (b), a larger value indicates that the positions have been allocated to more RC blocks, so that remapping of the failed word to the positions should be avoided. When a new remapped RC block is allocated for an RC block, it is first necessary to calculate a weighted sum of all remapped positions at all translation scales. For example, according to the distribution of dead words in fig. 5 (c), the weighted sum of all remapped positions with a translation scale of 0 is 1+1+1=3, while the weighted sum with a translation scale of 1 is 3+1+1=5, and the weighted sums of the remaining translation scales can be calculated in the same manner, as shown in fig. 5 (d); these weighted sums are then ranked from low to high, the ranking result being shown in fig. 5 (e). A low weighting value means that the corresponding translation scale has a higher priority, since the remapped positions at the translation scale are least allocated, thus having a higher probability of successful mapping; finally, these translation scales are traversed starting with high priority until the available remapped RC blocks are found at a certain translation scale. In fig. 5, at a translation scale of 6, the remapped RC block 1 meets the mapping requirement.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention without requiring creative effort by one of ordinary skill in the art. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.
Claims (2)
1. A method for combating hard failure errors in a resistive switching memory comprising the steps of: mixed granularity remapping, invalidation word translation optimization and remapping information record optimization;
The method for resisting hard failure errors of the resistance change symmetrical memory is based on two granularities irrelevant to the data storage direction, wherein the two granularities irrelevant to the data storage direction comprise a coarse granularity and a fine granularity; the fine granularity is the minimum invalid data block granularity, the coarse granularity is RC block granularity, the minimum invalid data block is an invalid word, the RC block is a data block surrounded by cache lines in two directions of rows and columns on a storage array, the invalid word is data positioned at the intersection of the rows and the columns of the storage array, the size of the invalid word is one word, and the word is 8 bytes;
In the mixed granularity remapping step, all the failed words within one RC block must be mapped into the same remapped RC block, all the failed words must remain in the same relative position in the RC block and the remapped RC block, multiple RC blocks are mapped into one remapped RC block; the step of remapping the mixed particle size comprises: hard failure error detection, remapped address recovery, and hard failure error correction;
the hard failure error detection includes: for a 64-bit word, setting an 8-bit storage granule bit width, including a 7-bit SEC error correction code and a one-bit 'remapping flag'; in a read operation, if the "remap flag bit" is "0", the 7-bit SEC error correction code is directly used to recover the data, otherwise, the memory retrieves the correct data from the corresponding remap location;
The remap address recovery includes: when the remapping address is extracted from a minimum invalid data block, only the remapping RC block address is stored, and the relative address of the invalid word represents the relative position of the relative address in the remapping RC block by adopting original address data; the remapped address is determined by both a coarse-grained remapped RC block address and a fine-grained relative address of the failed word; the remap address recovery includes: distribution of remapping information, recovery of remapping information;
The distribution of remapping information uses a minimum dead data block space to store its remapped addresses, storing only its remapped RC block addresses, including: retrieving a portion representing the remapped RC block address from the complete remapped address; dividing the extracted remapped RC block address into 4 pieces by taking 7 bits as a unit; putting 4 pieces of the remapped RC block address division into failure words according to a preset rule;
The recovering of the remapping information includes: the method comprises the steps of obtaining an address of a remapped RC block by adopting a parity check method, directly obtaining a relative address of a failure word from an original address, combining the address of the remapped RC block with the relative address of the failure word, and finally obtaining the remapped address;
The hard failure error correction includes: in the process of reading data, firstly reading line-wise or column-wise cache line data from a memory, checking the remapping flag bits of all words, if the remapped words exist in the cache line, recovering the remapped addresses of the remapped words from the invalid words, executing another reading operation on the remapped addresses, splicing correct data obtained in the two reading operations together to form complete line-wise or column-wise cache line data, and transmitting the complete line-wise or column-wise cache line data to a processor;
In the process of writing data, firstly checking a remapping flag bit, judging whether an additional writing operation to a remapping address is needed, and if not, writing the data into a destination address; otherwise, constructing a mask according to the remapping flag bit and writing the data of the corresponding failure unit into the remapping address;
In the step of translation optimization of the invalid words, if the relative positions of the invalid words in an original RC block conflict with the relative positions of the invalid words in the RC block to be remapped, adopting a translation scale, and simultaneously translating all the invalid words in the original RC block to the right by the translation scale and then mapping the translated words into the RC block to be remapped; the dead word shift optimization includes: the measurement of the translation scale, the storage of the translation scale and the determination of the translation scale;
the measurement of the translation scale includes: using the translation scale of 64 words to represent 64 movable positions in an RC block containing 8×8 words, including its original position, and using numbers from 0 to 63 to represent the translation scale of the 64 words, wherein 0 represents no translation;
The storing of the translation scale includes: storing the translation scale and the remapped address in the same invalid word, wherein the storing method comprises the following steps: putting the translation scale into a lossless segment of the invalidation word, and avoiding the segment storing the remapped address; setting a parity check bit for storing the section with the translation scale, so that the section where the parity check bit is positioned can pass through parity check; wherein, obtaining the remapped address of the invalid word with the translation scale comprises: firstly, extracting a remapping address from a failure word through parity check, extracting a translation scale through parity check, calculating a new relative position by utilizing the translation scale, and finally merging the remapping address and the new relative position to determine the accurate position of the failure word;
The determination of the translation scale includes: dividing a remapping page into 4 remapping RC blocks, wherein the remapping RC blocks have 16 word positions; calculating the allocation quantity of the positions of the words in the remapping RC block according to the condition that the words in the remapping page are allocated, so that a larger value represents the quantity of the invalid words of which the corresponding positions are allocated to other RC blocks, and taking the quantity as the weight of each remapping position; when a new remapped RC block is allocated to one RC block, firstly, calculating a weighted sum of remapped positions under all translation scales, sequencing the weighted sum from low to high, endowing the translation scales corresponding to low weighted values with higher priority, traversing all translation scales from the high priority until an available remapped RC block is searched under a certain translation scale, and determining to select the translation scale;
In the remapping information record optimizing step, when data is loaded into a cache, additionally recording whether the data has remapping or recording the remapping address information of the data; the remapping information record optimization includes a recording mode of "known remapping" and a recording mode of "known remapping address";
Setting an extra 1-bit flag bit for each cache line in the cache, wherein the data of the flag bit marks whether the data of the cache line come from two physical addresses or not, and the two physical addresses comprise a destination address and a remapping address; if the flag bit is '0', directly accessing the destination address without pre-reading operation when the data is written back; if the flag bit is '1', performing a pre-reading operation and determining a remapping address when the data is written back;
the record mode of the 'remapping address is known', the position index of the invalid word in the cache line data and the corresponding remapping address are stored into the cache; when the data is written back, the processor issues a write instruction to the destination address and the remapped address according to the specific remapped condition.
2. The method of combating resistive random access memory hard failure errors according to claim 1, wherein said predetermined rules in said distribution of remapping information include:
dividing the 8-byte storage space of the invalidation word into 8 segments, wherein each segment is 8 bits;
storing the 4 pieces of remapped RC block address division into 4 segments of the failure word respectively, and avoiding segments at most of which two failures are likely to occur;
Setting a parity bit of one bit in a segment storing the remapped RC address so that the bit can be combined with the 7-bit slice to pass the parity check;
setting a parity bit of one bit in the failed segment, so that the storage content of the failed segment cannot pass parity check;
The obtaining the address of the remapped RC block by the parity check method comprises the following steps: for the segment storing the remapped address in the failure word, reading the parity check bit of the segment, and reading the corresponding 7-bit slice in the segment after the parity check passes; for segments where there are failed cells, their parity bits are read and the parity does not pass through not reading their data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110776874.6A CN113450863B (en) | 2021-07-09 | 2021-07-09 | Method for resisting hard failure error of resistive random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110776874.6A CN113450863B (en) | 2021-07-09 | 2021-07-09 | Method for resisting hard failure error of resistive random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113450863A CN113450863A (en) | 2021-09-28 |
| CN113450863B true CN113450863B (en) | 2024-09-10 |
Family
ID=77815725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110776874.6A Active CN113450863B (en) | 2021-07-09 | 2021-07-09 | Method for resisting hard failure error of resistive random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113450863B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105005510A (en) * | 2015-07-02 | 2015-10-28 | 西安交通大学 | Error correction protection architecture and method applied to resistive random access memory cache of solid state disk |
| CN111913890A (en) * | 2020-08-13 | 2020-11-10 | 北京万协通信息技术有限公司 | Non-volatile memory random read-write method based on security module |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0409808A3 (en) * | 1989-07-19 | 1991-11-27 | International Business Machines Corporation | Method for ensuring map integrity in a system-managed store of a computer |
| US8069395B2 (en) * | 2007-03-01 | 2011-11-29 | Cisco Technology, Inc. | Three bit error detection using ECC codes |
| CN112306500B (en) * | 2020-11-30 | 2022-06-07 | 上海交通大学 | Compiling method for reducing multi-class access conflict aiming at coarse-grained reconfigurable structure |
-
2021
- 2021-07-09 CN CN202110776874.6A patent/CN113450863B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105005510A (en) * | 2015-07-02 | 2015-10-28 | 西安交通大学 | Error correction protection architecture and method applied to resistive random access memory cache of solid state disk |
| CN111913890A (en) * | 2020-08-13 | 2020-11-10 | 北京万协通信息技术有限公司 | Non-volatile memory random read-write method based on security module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113450863A (en) | 2021-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107391026B (en) | Flash memory device and flash memory management method | |
| CN107403646B (en) | Flash memory device and flash memory management method | |
| KR101459861B1 (en) | Stripe-based memory operation | |
| CN102163458B (en) | Semiconductor memory device | |
| CN104424040B (en) | Method for accessing storage unit in flash memory and device using the same | |
| CN102194527B (en) | Semiconductor memory device | |
| EP2612247B1 (en) | Stripe-based non-volatile multilevel memory operation | |
| CN104425019A (en) | Method for accessing storage unit in flash memory and device using the same | |
| CN104424127A (en) | Method for accessing storage unit in flash memory and device using the same | |
| KR20130088173A (en) | Transaction log recovery | |
| CN111710358B (en) | Flash memory device, flash memory controller and flash memory storage management method | |
| CN104425018B (en) | Method for accessing storage unit in flash memory and device using the same | |
| CN104425020A (en) | Method for accessing storage unit in flash memory and device using the same | |
| CN114730607A (en) | Memory fault repairing method and device | |
| CN111522684A (en) | Method and device for simultaneously correcting soft and hard errors of phase change memory | |
| CN113342577B (en) | Storage device and data recovery method thereof | |
| CN113450863B (en) | Method for resisting hard failure error of resistive random access memory | |
| US20240079073A1 (en) | Storage controller generating read voltages for soft decision decoding based on read information and decoding information, storage device including the same, and operating method thereof | |
| CN105027084A (en) | Apparatus and method for controlling memory in mobile communication system | |
| CN108108118B (en) | Data writing method and storage controller | |
| CN118689410B (en) | Method, device, equipment, storage medium and program product for detecting read interference | |
| CN113590038B (en) | Solid state disk management method and solid state disk | |
| EP4336507A1 (en) | Storage controller generating read voltages for soft decision decoding based on read information and decoding information, storage device including the same, and operating method thereof | |
| US20220283727A1 (en) | Solid state storage device with look-up tables providing improved reference voltages | |
| CN111679787A (en) | Flash memory device, flash memory controller and flash memory storage management method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |