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CN104681621B - 一种源极抬高电压使用的高压ldmos及其制造方法 - Google Patents

一种源极抬高电压使用的高压ldmos及其制造方法 Download PDF

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CN104681621B
CN104681621B CN201510080741.XA CN201510080741A CN104681621B CN 104681621 B CN104681621 B CN 104681621B CN 201510080741 A CN201510080741 A CN 201510080741A CN 104681621 B CN104681621 B CN 104681621B
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CN104681621A (zh
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乐薇
邢军军
杨文清
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本申请公开了一种源极抬高电压使用的高压LDMOS器件，在p型衬底与n型外延层的交界面具有n型埋层和p型埋层；n型埋层与p型埋层的侧面不接触，两者具有一定距离，从而提高了n型埋层与p型埋层之间的耐压；所述p型埋层与漏极在垂直方向上至少部分重叠，从而令p型埋层对漏极生成降低表面电场作用以提升漏极对源极的耐压；所述n型埋层在源极和体区引出端的正下方，从而对源极和体区引出端对p型衬底进行高压隔离。本申请通过结构优化可在相同的制造工艺和制程下提升高压LDMOS的击穿电压，从而可用于源极抬高电压的使用环境。

Description

一种源极抬高电压使用的高压LDMOS及其制造方法
技术领域
本申请涉及一种LDMOS(横向扩散金属氧化物半导体)器件。
背景技术
源极抬高电压使用(high side)的LDMOS器件是指LDMOS的源极接一电压，例如与漏极接同一电压；这与通常的LDMOS器件的源极接地有着显著区别。
请参阅图1，这是一种现有的源极抬高电压使用的n型LDMOS器件。在p型衬底中具有n型埋层，n型埋层之上具有n型外延层。n型埋层的侧壁与一圈p型埋层相接触，p型埋层之上为p阱一，p阱一中有p型重掺杂的衬底引出端。由p阱一、p型埋层和n型埋层形成了一个碗状的隔离环(isolating ring)，将n型外延层和p型衬底相隔离。在n型外延层中具有p阱二和n阱。在p阱二的表面具有n型重掺杂的源区和p型重掺杂的体区引出端。在n型外延层中且在n阱之上为n型漂移区。在n型漂移区的表面具有n型重掺杂的漏极。在n型外延层的表面和n型漂移区的表面具有多个隔离结构，用来隔离衬底引出端和漏极、以及隔离漏极和栅极。在源极的外侧且在p阱二之上、n型外延层之上、n型漂移区之上具有栅氧化层和栅极，栅极还部分地位于漂移区之上的隔离结构之上。
图1所示的LDMOS器件可以采用BCD(bipolar-CMOS-DMOS)工艺制造，制程例如为0.35μm。该LDMOS器件的击穿电压受限于两个方面：首先是隔离环结构中n型埋层与p型埋层之间的击穿电压，其次是漏极与源极之间的击穿电压。该LDMOS器件由于n型外延层的厚度较薄(厚度仅为4.5μm)，且n型外延层下方具有n型埋层，使得器件耐压无法提升到70V以上。即便增加n型漂移区的长度，该LDMOS的耐压通常仅可达到50V，因此该LDMOS通常只能用作40V耐压的源极抬高电压使用的功率器件。
发明内容
本申请所要解决的技术问题是提供一种新型结构的源极抬高电压使用的高压LDMOS，通过优化结构来提升器件耐压。
为解决上述技术问题，本申请源极抬高电压使用的高压LDMOS器件被一个碗状的隔离环所包围；所述隔离环包括在p型衬底与n型外延层的交界面的n型埋层和p型埋层、p型埋层上方的p阱；n型埋层与p型埋层的侧面不接触，两者具有一定距离，从而提高了n型埋层与p型埋层之间的耐压；所述p型埋层与漏极在垂直方向上至少部分重叠，从而令p型埋层对漏极生成降低表面电场作用以提升漏极对源极的耐压；所述n型埋层在源极和体区引出端的正下方，从而对源极和体区引出端对p型衬底进行高压隔离。
本申请源极抬高电压使用的高压LDMOS器件的制造方法包括如下步骤：
第1步，在p型衬底中离子注入形成n型注入区；
第2步，在p型衬底中离子注入形成p型注入区；p型注入区与n型注入区的侧面不接触，两者之间具有一定距离；
第3步，在p型衬底之上形成n型外延层；p型注入区变为p型埋层，n型注入区变为n型埋层；p型埋层和n型埋层均在p型衬底和n型外延层的交界面处；
第4步，在n型外延层表面热氧化生长出第一氧化硅，并淀积氮化硅，再采用光刻和刻蚀工艺去除部分位置的氮化硅和第一氧化硅；接着在暴露的n型外延层表面热氧化生长出第二氧化硅作为隔离结构；最后采用湿法腐蚀工艺去除氮化硅；
第5步，在n型外延层中离子注入形成n阱；
第6步，在n阱上形成n型漂移区；
第7步，在n型外延层中形成p阱一和p阱二；p阱一、p型埋层和n型埋层构成了包围LDMOS的隔离环；
第8步，在n型外延层上热氧化生长出第三氧化硅，并淀积多晶硅，再形成多晶硅栅极及其下方的栅氧化层；
第9步，离子注入以在p阱一中形成衬底引出端，在漂移区中形成漏极，在p阱二中形成源极和体区引出端；漏极与p型埋层在垂直方向上至少部分重叠；源极和体区引出端在n型埋层的正上方。
本申请通过结构优化可在相同的制造工艺和制程下提升源极抬高电压使用的高压LDMOS的击穿电压，从而可用于高耐压的源极抬高电压的使用环境。
附图说明
图1是一种现有的源极抬高电压使用的n型LDMOS器件的结构示意图；
图2是本申请的源极抬高电压使用的n型LDMOS器件的结构示意图；
图3是现有的源极抬高电压使用的LDMOS器件的BVoff(off-state breakdownvoltage，关断状态击穿电压)示意图；
图4是现有的源极抬高电压使用的LDMOS器件的BVon(on-state breakdownvoltage，导通状态击穿电压)示意图；
图5是本申请的源极抬高电压使用的LDMOS器件的BVoff示意图；
图6是本申请的源极抬高电压使用的LDMOS器件的BVon示意图。
具体实施方式
请参阅图2，这是本申请的源极抬高电压使用的n型LDMOS器件。在p型衬底中具有n型外延层。在p型衬底与n型外延层的交界面具有n型埋层和p型埋层。n型埋层与p型埋层的侧面不接触，两者具有一定距离。在p型埋层之上为p阱一，p阱一中有p型重掺杂的衬底引出端。在n型外延层中具有p阱二和n阱，p阱二在n型埋层的正上方。在p阱二的表面具有n型重掺杂的源区和p型重掺杂的体区引出端。在n型外延层中且在n阱之上为n型漂移区。在n型漂移区的表面具有n型重掺杂的漏极。漏极与p型埋层在垂直方向上至少部分重叠(overlap)。在n型外延层的表面和n型漂移区的表面具有多个隔离结构，用来隔离衬底引出端和漏极、以及隔离漏极和栅极。在源极的外侧且在p阱二之上、n型外延层之上、n型漂移区之上具有栅氧化层和栅极，栅极还部分地位于漂移区的隔离结构之上。
与现有的源极抬高电压使用的高压LDMOS器件相比，本申请的源极抬高电压使用的高压LDMOS器件具有如下改进：
其一，原本的p型埋层与n型埋层在侧面相接触，而完全隔离n型外延层和p型衬底。本申请通过版图设计使得p型埋层与n型埋层在侧面不接触，两者之间具有一定间距，从而提高了p型埋层与n型埋层之间的击穿电压。
其二，由于n型外延层的厚度较薄，本申请使得漏极与p型埋层在垂直方向上重叠，此时p型埋层对漏极起到了Resurf(降低表面电场)的作用，从而提高了源极与漏极之间的耐压。
其三，n型埋层仍然在p阱二的正下方，因此还能确保源极和体区引出端对p型衬底的高压隔离，该LDMOS器件仍能用作源极抬高电压使用的功率器件。
请参阅图3和图4，图1所示的现有LDMOS的BVoff约为48V，BVon约为50V，通常只能用作40V耐压的源极抬高电压使用的功率器件。
请参阅图5和图6，图2所示的本申请LDMOS的BVoff约为85V，BVon约为77V，可用作70V耐压的源极抬高电压使用的功率器件。
本申请的LDMOS仍采用现有的BCD工艺和0.35μm制程，也不需要额外的光刻掩模版，就能将器件耐压提升60％以上(以48V与77V进行比较)，极大地扩展了应用环境。
本申请的源极抬高电压使用的高压LDMOS器件的制造方法包括如下步骤：
第1步，采用光刻和离子注入工艺在p型衬底中形成n型注入区。离子注入的n型杂质例如为锑(Sb)，离子注入后通常还有高温退火步骤。
第2步，采用光刻和离子注入工艺在p型衬底中形成p型注入区。离子注入的p型杂质例如为硼(B)，离子注入后通常还有快速热退火(RTA)步骤。
此时，p型注入区与n型注入区的侧面不接触，两者之间具有一定距离。
第3步，在p型衬底之上采用外延生长工艺形成n型外延层。
此时，p型注入区变为p型埋层，n型注入区变为n型埋层。p型埋层和n型埋层均在p型衬底和n型外延层的交界面处。
第4步，在n型外延层表面采用热氧化生长工艺形成氧化硅(称为第一氧化硅)，并淀积氮化硅，再采用光刻和刻蚀工艺去除部分氮化硅和第一氧化硅。接着在暴露的n型外延层表面采用热氧化生长工艺再形成氧化硅(称为第二氧化硅)作为隔离结构。最后采用湿法腐蚀工艺去除氮化硅。
第5步，采用光刻和离子注入工艺在n型外延层中形成n阱。其中的离子注入例如采用三步注入实现，即将n阱分为上、中、下三部分；先对n阱下部进行离子注入，再对n阱中部进行离子注入，最后对n阱上部进行离子注入。
第6步，采用光刻和离子注入工艺在n阱上形成n型漂移区。离子注入的n型杂质例如为磷(P)。
第7步，采用光刻和离子注入工艺在n型外延层中形成p阱一和p阱二。其中的离子注入例如采用三步注入实现，即将p阱分为上、中、下三部分；先对p阱下部进行离子注入，再对p阱中部进行离子注入，最后对p阱上部进行离子注入。
第8步，在n型外延层上采用热氧化生长工艺形成氧化硅(称为第三氧化硅)，并淀积多晶硅，再采用光刻和刻蚀工艺形成多晶硅栅极及其下方的栅氧化层。
此时，栅极的一部分在p阱二之上、n型外延层之上和n型漂移区之上，栅极的另一部分在漂移区隔离结构之上。
第9步，采用光刻和离子注入工艺在p阱一中形成衬底引出端，在漂移区中形成漏极，在p阱二中形成源极和体区引出端。
最后进行后端工艺，采用刻蚀接触孔、填充金属、连线、钝化层等工艺将电极引出。
以上仅为本申请的优选实施例，并不用于限定本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (9)

1.一种源极抬高电压使用的高压LDMOS器件，其特征是，所述LDMOS被一个碗状的隔离环所包围；所述隔离环包括在p型衬底与n型外延层的交界面的n型埋层和p型埋层、p型埋层上方的p阱；n型埋层与p型埋层的侧面不接触，两者具有一定距离，从而提高了n型埋层与p型埋层之间的耐压；所述p型埋层与漏极在垂直方向上至少部分重叠，从而令p型埋层对漏极生成降低表面电场作用以提升漏极对源极的耐压；所述n型埋层在源极和体区引出端的正下方，从而对源极和体区引出端对p型衬底进行高压隔离。
2.根据权利要求1所述的源极抬高电压使用的高压LDMOS器件，其特征是，在p型衬底中具有n型外延层；在p型埋层之上为p阱一，p阱一中有p型重掺杂的衬底引出端；在n型外延层中具有p阱二和n阱，p阱二在n型埋层的正上方；在p阱二的表面具有n型重掺杂的源区和p型重掺杂的体区引出端；在n型外延层中且在n阱之上为n型漂移区；在n型漂移区的表面具有n型重掺杂的漏极；在n型外延层的表面和n型漂移区的表面具有多个隔离结构，用来隔离衬底引出端和漏极、以及隔离漏极和栅极；在源极的外侧且在p阱二之上、n型外延层之上、n型漂移区之上具有栅氧化层和栅极，栅极还部分地位于漂移区的隔离结构之上。
3.一种源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，包括如下步骤：
第1步，在p型衬底中离子注入形成n型注入区；
第2步，在p型衬底中离子注入形成p型注入区；p型注入区与n型注入区的侧面不接触，两者之间具有一定距离；
第3步，在p型衬底之上形成n型外延层；p型注入区变为p型埋层，n型注入区变为n型埋层；p型埋层和n型埋层均在p型衬底和n型外延层的交界面处；
第4步，在n型外延层表面热氧化生长出第一氧化硅，并淀积氮化硅，再采用光刻和刻蚀工艺去除部分位置的氮化硅和第一氧化硅；接着在暴露的n型外延层表面热氧化生长出第二氧化硅作为隔离结构；最后采用湿法腐蚀工艺去除氮化硅；
第5步，在n型外延层中离子注入形成n阱；
第6步，在n阱上形成n型漂移区；
第7步，在n型外延层中形成p阱一和p阱二；p阱一、p型埋层和n型埋层构成了包围LDMOS的隔离环；
第8步，在n型外延层上热氧化生长出第三氧化硅，并淀积多晶硅，再形成多晶硅栅极及其下方的栅氧化层；
第9步，离子注入以在p阱一中形成衬底引出端，在漂移区中形成漏极，在p阱二中形成源极和体区引出端；漏极与p型埋层在垂直方向上至少部分重叠；源极和体区引出端在n型埋层的正上方。
4.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第1步中，离子注入的n型杂质为锑，离子注入后还有高温退火步骤。
5.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第2步中，离子注入的p型杂质为硼，离子注入后还有快速热退火步骤。
6.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第5步中，离子注入采用三步注入实现，即将n阱分为上、中、下三部分；先对n阱下部进行离子注入，再对n阱中部进行离子注入，最后对n阱上部进行离子注入。
7.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第6步中，离子注入的n型杂质为磷。
8.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第7步中，离子注入采用三步注入实现，即将p阱分为上、中、下三部分；先对p阱下部进行离子注入，再对p阱中部进行离子注入，最后对p阱上部进行离子注入。
9.根据权利要求3所述的源极抬高电压使用的高压LDMOS器件的制造方法，其特征是，所述方法第8步中，栅极的一部分在p阱二之上、n型外延层之上和n型漂移区之上，栅极的另一部分在漂移区隔离结构之上。
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