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TWI654756B - 高壓半導體裝置 - Google Patents

高壓半導體裝置

Info

Publication number
TWI654756B
TWI654756B TW107114008A TW107114008A TWI654756B TW I654756 B TWI654756 B TW I654756B TW 107114008 A TW107114008 A TW 107114008A TW 107114008 A TW107114008 A TW 107114008A TW I654756 B TWI654756 B TW I654756B
Authority
TW
Taiwan
Prior art keywords
region
conductivity type
well region
isolation structure
buried layer
Prior art date
Application number
TW107114008A
Other languages
English (en)
Other versions
TW201946277A (zh
Inventor
維克 韋
魯夫 陳
陳柏安
Original Assignee
新唐科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司 filed Critical 新唐科技股份有限公司
Priority to TW107114008A priority Critical patent/TWI654756B/zh
Priority to CN201910187396.8A priority patent/CN110400842B/zh
Application granted granted Critical
Publication of TWI654756B publication Critical patent/TWI654756B/zh
Priority to US16/378,651 priority patent/US10784369B2/en
Publication of TW201946277A publication Critical patent/TW201946277A/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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Abstract

高壓半導體裝置包含半導體基底，具有第一導電類型，源極區和汲極區設置於半導體基底上，其中汲極區具有與第一導電類型相反的第二導電類型，且源極區包含分別具有第一導電類型和第二導電型的兩個部分，第一隔離結構和第二隔離結構分別設置於汲極區的相對兩側，其中第一隔離結構在源極區與汲極區之間，第一井區設置於第二隔離結構下且具有第一導電類型，其中第一井區的頂面鄰接第二隔離結構的底面，以及第一埋層設置於半導體基底內且具有第一導電類型，其中第一埋層與第一井區重疊。

Description

高壓半導體裝置
本發明是關於半導體裝置，特別是關於高壓半導體裝置。
高壓半導體裝置技術適用於高電壓與高功率的積體電路領域。傳統高壓半導體裝置，例如垂直式擴散金氧半導體(vertically diffused metal oxide semiconductor,VDMOS)電晶體及水平擴散金氧半導體(laterally diffused metal oxide semiconductor,LDMOS)電晶體，主要用於12V以上的元件應用領域。高壓裝置技術的優點在於符合成本效益，且易相容於其它製程，已廣泛應用於顯示器驅動IC元件、電源供應器、電力管理、通訊、車用電子或工業控制等領域中。
雖然現存的高壓半導體裝置已逐步滿足它們既定的用途，但它們仍未在各方面皆徹底的符合要求。因此，關於高壓半導體裝置和製造技術仍有一些問題需要克服。
本發明提供了高壓半導體裝置的實施例，特別是水平擴散金氧半導體(LDMOS)電晶體的實施例。通常藉由在製程中調整水平擴散金氧半導體之井區的摻雜濃度，使得水平擴散金氧半導體產生特定的崩潰電壓，以符合不同產品應用的需 求。然而，在實際的製程，例如整合式的雙載子-互補式金氧半導體-擴散金氧半導體(bipolar-CMOS-DMOS，BCD)的製程中，調整井區的摻雜濃度將會需要在製程中添加額外的光罩，使得整體的製程成本也跟著提高。
為了提高水平擴散金氧半導體電晶體的崩潰電壓，本發明的一些實施例在水平擴散金氧半導體電晶體中，在汲極區相對於源極區的另一側設置具有與汲極區相反導電類型的第一井區和第一埋層，第一井區和第一埋層相連形成L形的結構，且L形的水平部分係朝向源極區的方向延伸。藉由L形結構的設置，當對水平擴散金氧半導體電晶體的汲極端施加反向電壓時，可增加空乏區的大小，進而提升裝置的崩潰電壓。擁有高崩潰電壓的水平擴散金氧半導體電晶體可被廣泛地應用於電位轉換器(level shifter)及高壓積體電路(high voltage integrated circuit，HVIC)晶片中。
根據一些實施例，提供高壓半導體裝置。高壓半導體裝置包含半導體基底，具有第一導電類型，以及源極區和汲極區設置於半導體基底上，其中汲極區具有與第一導電類型相反的第二導電類型，且源極區包含分別具有第一導電類型和第二導電型的兩個部分。高壓半導體裝置也包含第一隔離結構和第二隔離結構，分別設置於汲極區的相對兩側，以及第一井區設置於第二隔離結構下且具有第一導電類型，其中第一井區的頂面鄰接第二隔離結構的底面。半導體裝置更包含第一埋層，設置於半導體基底內且具有第一導電類型，其中第一埋層與第一井區重疊。
根據一些實施例，提供高壓半導體裝置。高壓半導體裝置包含半導體基底，具有第一導電類型，以及磊晶層設置於半導體基底上。高壓半導體裝置也包含源極區和第一汲極區設置於磊晶層內，其中第一汲極區具有與第一導電類型相反的第二導電類型，且源極區包含分別具有第一導電類型和第二導電型的兩個部分，以及第一隔離結構和第二隔離結構設置於磊晶層上，其中第一汲極區位於第一隔離結構與第二隔離結構之間，且第一隔離結構在源極區與第一汲極區之間。高壓半導體裝置更包含第一井區，設置於磊晶層內和第二隔離結構下，其中第一井區具有第一導電類型且由第二隔離結構完全覆蓋，以及第一埋層設置於第一井區下且具有第一導電類型，其中第一埋層接觸第一井區，且第一埋層延伸至第一汲極區的正下方。
本發明的半導體裝置可應用於多種類型的半導體裝置，為讓本發明之特徵和優點能更明顯易懂，下文特舉出應用於水平擴散金氧半導體電晶體之實施例，並配合所附圖式，作詳細說明如下。
100、200、300、400‧‧‧高壓半導體裝置
101‧‧‧半導體基底
103、103’‧‧‧第二埋層
105、205、305‧‧‧第一埋層
107‧‧‧磊晶層
109、109’、111、111’、113、113’、115、115’‧‧‧高壓井區
117、123、123’、125、125’‧‧‧井區
119a、119a’、119b、119b’、119c、119c’、119d‧‧‧隔離結構
121、121’‧‧‧閘極結構
127、127’、129、129’、131、131’、133、133’‧‧‧摻雜區
135‧‧‧介電層
137a、137a’、137b、137b’、137c、137c’、137d、137d’‧‧‧導孔
139、139’‧‧‧基底電極
141、141’‧‧‧源極電極
143‧‧‧汲極電極
305a、305b、305c、305d‧‧‧區段
306a、306b‧‧‧連接部
L1、L2、L3、L4‧‧‧長度
D1、D2‧‧‧距離
藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的觀點。值得注意的是，根據工業上的標準慣例，一些部件(feature)可能沒有按照比例繪製。事實上，為了能清楚地討論，不同部件的尺寸可能被增加或減少。
第1圖是根據本發明的一些實施例，顯示高壓半導體裝置的剖面示意圖； 第2圖是根據本發明的一些實施例，顯示高壓半導體裝置的剖面示意圖；第3圖是根據本發明的一些實施例，顯示高壓半導體裝置的剖面示意圖；以及第4圖是根據本發明的一些實施例，顯示高壓半導體裝置的剖面示意圖。
以下揭露提供了很多不同的實施例或範例，用於實施所提供的高壓半導體裝置之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例及/或形態之間的關係。
以下描述實施例的一些變化。在不同圖式和說明的實施例中，相似的參考數字被用來標明相似的元件。可以理解的是，在方法的前、中、後可以提供額外的操作，且一些敘述的操作可為了該方法的其他實施例被取代或刪除。
第1圖是根據本發明的一些實施例，顯示高壓半導體裝置100的剖面示意圖。高壓半導體裝置100包含半導體基底101。半導體基底101可由矽或其他半導體材料製成，或 者，半導體基底101可包含其他元素半導體材料，例如鍺(Ge)。一些實施例中，半導體基底101由化合物半導體製成，例如碳化矽、氮化鎵、砷化鎵、砷化銦或磷化銦。一些實施例中，半導體基底101由合金半導體製成，例如矽鍺、碳化矽鍺、磷化砷鎵或磷化銦鎵。
此外，半導體基底101可包含絕緣層上覆矽(silicon-on-insulator，SOI)基底。一些實施例中，半導體基底101可為輕摻雜之P型或N型基底。在本實施例中，半導體基底101為P型，其內部具有P型摻質(例如硼(B))，且後續於半導體基底101上形成的高壓半導體裝置100可包含N型的水平擴散金氧半導體電晶體。
高壓半導體裝置100可包含設置於半導體基底101上的磊晶層107。一些實施例中，磊晶層107可為N型或P型。磊晶層107可藉由金屬有機物化學氣相沉積法(metal organic chemical vapor deposition，MOCVD)、電漿增強化學氣相沉積法(plasma-enhanced CVD，PECVD)、分子束磊晶法(molecular beam epitaxy，MBE)、氫化物氣相磊晶法(hydride vapour phase epitaxy，HVPE)、液相磊晶法(liquid phase epitaxy，LPE)、氯化物氣相磊晶法(chloride-vapor phase epitaxy，Cl-VPE)、其他相似的製程方法或前述之組合以形成。在其他實施例中，高壓半導體裝置100可不包含磊晶層107，後續形成於磊晶層107內的高壓井區、井區、摻雜區可直接形成於半導體基底101內(即靠近半導體基底101之頂面的位置)。
此外，如第1圖所示，高壓半導體裝置100包含 設置在半導體基底101內和磊晶層107內的第一埋層105和第二埋層103。第一埋層105和第二埋層103具有相反的導電類型，在本實施例中，第一埋層105為P型，且第二埋層103為N型。此外，第一埋層105和第二埋層103的摻雜濃度在約1x1016原子/cm3至約1x1019原子/cm3的範圍內。
第一埋層105和第二埋層103的形成方法包含在形成磊晶層107之前，在半導體基底101內離子植入P型摻質(例如硼(B))或N型摻質(例如磷(P)或砷(As))，實施熱處理將植入的離子驅入(drive in)半導體基底101內，然後在半導體基底101上形成磊晶層107。一些實施例中，由於磊晶層107係在高溫的條件下形成，故植入的離子會擴散進入磊晶層107內，如第1圖所示，第一埋層105和第二埋層103位於半導體基底101和磊晶層107的界面附近，且分別具有一部份在半導體基底101內，以及另一部分在磊晶層107內。
接續前述，高壓半導體裝置100包含位於磊晶層107內的井區117(又稱為第一井區)、高壓井區115(又稱為第一高壓井區)、高壓井區113(又稱為第二高壓井區)、高壓井區111和高壓井區109(又稱為第三高壓井區)。高壓井區109、高壓井區113和井區117具有相同於第一埋層105的導電類型，而高壓井區111和高壓井區115具有相同於第二埋層103的導電類型。在本實施例中，高壓井區109和113以及井區117為P型，而高壓井區111和115為N型。
此外，高壓井區109、111、113和115以及井區117的形成方法包含離子植入製程和熱驅入(drive in)製程。一 些實施例中，井區117的摻雜濃度大於或等於高壓井區109、111、113和115。舉例而言，高壓井區109、111、113和115的摻雜濃度在約1x1015原子/cm3至約5x1017原子/cm3的範圍內，且井區117的摻雜濃度在約5x1015原子/cm3至約1x1018原子/cm3的範圍內。
在形成高壓井區109、111、113和115以及井區117之後，在高壓井區115內形成井區125(又稱為第二井區或漂移(drift)區)，且在高壓井區113內形成井區123(又稱為第三井區或基體(body)區)。井區123和125具有相反的導電類型。明確而言，井區123具有相同於高壓井區113的導電類型，而井區125具有相同於高壓井區115的導電類型。在本實施例中，井區123為P型，且井區125為N型。用於形成井區123和125的製程相同或相似於井區117的製程，在此便不重複敘述。一些實施例中，井區123和125的摻雜濃度大於井區117的摻雜濃度，在約5x1016原子/cm3至約5x1018原子/cm3的範圍內。
根據一些實施例，如第1圖所示，高壓半導體裝置100包含設置於磊晶層107上的隔離結構119a、隔離結構119b(又稱為第三隔離結構)、隔離結構119c(又稱為第一隔離結構)和隔離結構119d(又稱為第二隔離結構)。明確而言，隔離結構119a、119b、119c和119d的一部分係嵌入磊晶層107內。一些實施例中，隔離結構119a、119b、119c和119d由氧化矽製成，且為藉由熱氧化法所形成的矽局部氧化(local oxidation of silicon，LOCOS)隔離結構。在其他實施例中，隔離結構 119a、119b、119c和119d可以是藉由蝕刻和沉積製程所形成的淺溝槽隔離(shallow trench isolation，STI)結構。
一些實施例中，在形成隔離結構119a、119b、119c和119d之後，在磊晶層107上形成閘極結構121。如第1圖所示，閘極結構121自井區123延伸至隔離結構119c上，且閘極結構121覆蓋井區123的一部分、高壓井區113的一部分和高壓井區115的一部分。
閘極結構121包含閘極介電層(未繪示)以及設置於其上的閘極電極(未繪示)。可先依序毯覆性沈積介電材料層(用以形成閘極介電層)及位於其上之導電材料層(用以形成閘極電極)於磊晶層107上，再藉由微影製程與蝕刻製程將介電材料層及導電材料層分別圖案化以形成包含閘極介電層及閘極電極的閘極結構121。
上述介電材料層之材料(即閘極介電層之材料)可包含氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)的介電材料、前述之組合或其它合適之介電材料。一些實施例中，介電材料層可藉由化學氣相沉積法(chemical vapor deposition，CVD)或旋轉塗佈(spin coating)以形成。上述導電材料層之材料(即閘極電極之材料)可為非晶矽、多晶矽、一或多種金屬、金屬氮化物、導電金屬氧化物、前述之組合或其他合適之導電材料。導電材料層之材料可藉由化學氣相沉積法(CVD)、濺鍍(sputtering)、電阻加熱蒸鍍法、電子束蒸鍍法、或其它合適的沈積方式形成。另外，閘極結構121可包含設置於閘極結構121之兩側側壁上的絕緣間隙物(未繪示)。
如第1圖所示，高壓半導體裝置100包含摻雜區127、摻雜區129、摻雜區131和摻雜區133。摻雜區127位於隔離結構119a與隔離結構119b之間。摻雜區129鄰接於摻雜區131，且摻雜區129和131位於隔離結構119b與閘極結構121之間。摻雜區133位於隔離結構119c與隔離結構119d之間。一些實施例中，在形成閘極結構121之後，形成摻雜區127、129、131和133。
在本實施例中，摻雜區127和129為P型，且摻雜區131和133為N型。摻雜區127、129、131和133的摻雜濃度高於井區117、123和125的摻雜濃度，一些實施例中，摻雜區127、129、131和133的摻雜濃度在約1x1019原子/cm3至約5x1020原子/cm3的範圍內。值得注意的是，摻雜區129和131可作為高壓半導體裝置100的源極區，且摻雜區133可作為高壓半導體裝置100的汲極區。
接續前述，高壓半導體裝置100包含設置於磊晶層107上的介電層135。介電層135包含由多個介電材料所形成的多層結構，如氧化矽、氮化矽、氮氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)、低介電常數(low-k)介電材料或其他合適的介電材料。
再者，如第1圖所示，高壓半導體裝置100包含設置於磊晶層107上和介電層135內的導孔(hole)137a、137b、137c和137d。此外，高壓半導體裝置100也包含設置於導孔137a上的基底電極139，設置於導孔137b和137c上的源極電 極141，以及設置於導孔137d上的汲極電極143。一些實施例中，導孔137a、137b、137c、137d、基底電極139、源極電極141以及汲極電極143的材料可包含鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、碳化鉭(TaC)、矽氮化鉭(TaSiN)、碳氮化鉭(TaCN)、鋁化鈦(TiAl)，鋁氮化鈦(TiAlN)、前述之組合或其他合適的導電材料。
明確而言，基底電極139藉由導孔137a與摻雜區127電性連接，源極電極141藉由導孔137b和137c與摻雜區129和131(即源極區)電性連接，汲極電極143藉由導孔137d與摻雜區133(即汲極區)電性連接。
根據一些實施例，如第1圖所示，在形成基底電極139、源極電極141和汲極電極143之後，完成高壓半導體裝置100。一些實施例中，第一埋層105的長度L1在約4μm至約30μm的範圍內，第一井區117的長度L2在約3μm至約15μm的範圍內，且第一井區117與井區125之間的距離D1在約2μm至約20μm的範圍內。
一些實施例中，第一井區117的頂面鄰接隔離結構119d的底面。一些實施例中，第一井區117由隔離結構119d所完全覆蓋。換言之，第一井區117在半導體基底101之頂面上的投影範圍在隔離結構119d在半導體基底101之頂面上的投影範圍內。再者，第一埋層105與第一井區117重疊。一些實施例中，如第1圖所示，第一埋層105接觸第一井區117且延伸至汲極區133、井區125和隔離結構119c的正下方。在其 他實施例中，第一埋層105可不延伸至隔離結構119c的正下方，或者，第一埋層105可不延伸至汲極區133的正下方。
為了提高高壓半導體裝置100的崩潰電壓，本發明的一些實施例藉由在汲極區133相對於源極區129和131的另一側設置具有與汲極區133相反導電類型的第一井區117和第一埋層105，第一井區117和第一埋層105相連形成L形的結構，且L形的水平部分係朝向源極區129和131的方向延伸。藉由L形結構的設置，當對水平擴散金氧半導體電晶體的汲極端施加反向電壓時，可增加空乏區的大小，進而提升裝置的崩潰電壓。擁有高崩潰電壓的水平擴散金氧半導體電晶體可被廣泛地應用於電位轉換器(level shifter)及高壓積體電路(high voltage integrated circuit，HVIC)晶片中。
第2圖是根據本發明的一些實施例，顯示高壓半導體裝置200的剖面示意圖。高壓半導體裝置200與高壓半導體裝置100之差異在於第一埋層205的形狀，高壓半導體裝置200之其他元件的製程和材料相同或相似於高壓半導體裝置100，在此便不重複敘述。如第2圖所示，高壓半導體裝置200的第一埋層205之厚度可沿著隔離結構119d往隔離結構119c的方向遞增。
第3圖是根據本發明的一些實施例，顯示高壓半導體裝置300的剖面示意圖。高壓半導體裝置300與高壓半導體裝置100之差異在於第一埋層305的形狀，高壓半導體裝置300之其他元件的製程和材料相同或相似於高壓半導體裝置100，在此便不重複敘述。
如第3圖所示，高壓半導體裝置300的第一埋層305可包含多個區段，例如區段305a、305b、305c和305d，且區段305a、305b、305c和305d之間藉由連接部306a、306b彼此連接。一些實施例中，第一埋層305的形成方法包含藉由圖案化的光阻實施離子蝕刻製程，以在半導體基底101內形成多個不連續的摻雜區段(未繪示)，然後，實施熱處理(即驅入)製程使得摻雜區段內的離子向外擴散以彼此連接。
如第3圖所示，區段305a藉由連接部306a與區段305b連接，區段305c藉由連接部306b與區段305d連接。在其他實施例中，區段305a、305b、305c和305d可藉由連接部完全連接，彼此之間不分離。值得注意的是，藉由形成多個不連續的摻雜區段以形成第一埋層305的方法可調整各個摻雜區段的摻雜濃度，使得形成的高壓半導體裝置300的特性可由製程上進行更深入地調控，第一埋層305空乏的情況會有所不同，藉此調整元件可承受的崩潰電壓。
第4圖是根據本發明的一些實施例，顯示高壓半導體裝置400的剖面示意圖。高壓半導體裝置400在第4圖的剖面中以第一埋層105和第一井區117的中心線為對稱軸具有兩側對稱的形狀。換言之，高壓半導體裝置400的左半側即為高壓半導體裝置100，且其右半側即為高壓半導體裝置100的鏡像。
值得注意的是，高壓半導體裝置400為以汲極電極143為中心的結構，由左至右依序為基底電極139、源極電極141、汲極電極143、源極電極141’和基底電極139’。隔離 結構119d兩側的汲極區133和133’分別藉由導孔137d和137d’電性連接於汲極電極143。
相似於高壓半導體裝置400的左側結構，高壓半導體裝置400的右側結構包含導孔137c’、137b’和137a’、隔離結構119c’、119b’和119a’、閘極結構121’、摻雜區131’和129’(又稱為源極區)、摻雜區127’、井區125’和123’、高壓井區115’、113’、111’和109’，以及第一埋層103’。上述高壓半導體裝置400之元件的製程和材料相同或相似於高壓半導體裝置100，在此便不重複敘述。
根據一些實施例，如第4圖所示，第一埋層105的長度L3在約10μm至約60μm的範圍內，第一井區117的長度L4在約6μm至約30μm的範圍內。此外，相似於第1圖的高壓半導體裝置100，高壓半導體裝置400的第一井區117與井區125之間的距離D1在約2μm至約20μm的範圍內，而第一井區117與另一側的井區125’之間的距離D2也在約2μm至約20μm的範圍內。
以上概述數個實施例，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。

Claims (10)

  1. 一種高壓半導體裝置，包括：一半導體基底，具有一第一導電類型；一源極區和一汲極區，設置於該半導體基底上，其中該汲極區具有與該第一導電類型相反的一第二導電類型，且該源極區包括分別具有該第一導電類型和該第二導電型的兩個部分；一第一隔離結構和一第二隔離結構，分別設置於該汲極區的相對兩側，其中該第一隔離結構在該源極區與該汲極區之間；一第一井區，設置於該第二隔離結構下且具有該第一導電類型，其中該第一井區的頂面鄰接該第二隔離結構的底面；一第一埋層，設置於該半導體基底內且具有該第一導電類型，其中該第一埋層與該第一井區重疊；以及一第二埋層，設置於該半導體基底內且具有該第二導電類型，其中該第二埋層位於該源極區下，且該第一埋層與該第二埋層彼此分隔開來。
  2. 如申請專利範圍第1項所述之高壓半導體裝置，其中該第一埋層的長度大於該第一井區的長度和該第二隔離結構的長度。
  3. 如申請專利範圍第1項所述之高壓半導體裝置，更包括：一第一高壓井區，設置於該第一埋層上且具有該第二導電類型，其中該第一高壓井區鄰接該第一井區和該第一埋層；以及一第二井區，設置於該第一高壓井區內且具有該第二導電類型，其中該第二井區位於該第一隔離結構與該第二隔離結構之間，且該汲極區位於該第二井區內。
  4. 如申請專利範圍第3項所述之高壓半導體裝置，更包括：一第二高壓井區，鄰接該第一高壓井區且具有該第一導電類型，其中該第二埋層位於該第二高壓井區下；一第三井區，設置於該第二高壓井區內且具有該第一導電類型，其中該源極區位於該第三井區內；以及一閘極結構，設置於該半導體基底上且自該第三井區延伸至該第一隔離結構上。
  5. 如申請專利範圍第1項所述之高壓半導體裝置，更包括：一第三隔離結構，設置於該半導體基底上，其中該源極區位於該第一隔離結構和該第三隔離結構之間；以及一第三高壓井區和一摻雜區，設置於該半導體基底上且具有該第一導電類型，其中該摻雜區位於該第三高壓井區內，該第三隔離結構位於該摻雜區與該源極區之間，且該摻雜區與該半導體基底電性連接。
  6. 一種高壓半導體裝置，包括：一半導體基底，具有一第一導電類型；一磊晶層，設置於該半導體基底上；一源極區和一第一汲極區，設置於該磊晶層內，其中該第一汲極區具有與該第一導電類型相反的一第二導電類型，且該源極區包括分別具有該第一導電類型和該第二導電型的兩個部分；一第一隔離結構和一第二隔離結構，設置於該磊晶層上，其中該第一汲極區位於該第一隔離結構與該第二隔離結構之間，且該第一隔離結構在該源極區與該第一汲極區之間；一第一井區，設置於該磊晶層內和該第二隔離結構下，其中該第一井區具有該第一導電類型且由該第二隔離結構完全覆蓋；以及一第一埋層，設置於該第一井區下且具有該第一導電類型，其中該第一埋層接觸該第一井區，且該第一埋層延伸至該第一汲極區的正下方；以及一第二埋層，設置於該半導體基底內且具有該第二導電類型，其中該第二埋層位於該源極區下，且該第一埋層與該第二埋層彼此分隔開來。
  7. 如申請專利範圍第6項所述之高壓半導體裝置，更包括：一第一高壓井區、一第二高壓井區和一第三高壓井區設置於該磊晶層內，其中該第二高壓井區位於該第一高壓井區和該第三高壓井區之間，該第一汲極區設置於該第一高壓井區內，該源極區設置於該第二高壓井區內，且該第一高壓井區具有該第二導電類型，該第二高壓井區和該第三高壓井區具有該第一導電類型；以及一摻雜區，設置於該第三高壓井區內且具有該第一導電類型，其中該摻雜區與該半導體基底電性連接。
  8. 如申請專利範圍第6項所述之高壓半導體裝置，其中該第一埋層的厚度沿著該第二隔離結構往該第一隔離結構的方向遞增。
  9. 如申請專利範圍第6項所述之高壓半導體裝置，其中該第一埋層包括複數個區段，該些區段藉由一連接部相連，且該連接部的厚度小於該些區段的厚度。
  10. 如申請專利範圍第6項所述之高壓半導體裝置，更包括：一第二汲極區，設置於該磊晶層內且具有該第二導電類型，其中該第一井區和該第二隔離結構位於該第一汲極區與該第二汲極區之間，且該第一埋層延伸至該第二汲極區的正下方。
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