CN104485334B - 阵列基板及其制作方法、显示装置 - Google Patents
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Abstract
本发明提供了一种阵列基板及其制作方法、显示装置,该阵列基板包括衬底基板,所述衬底基板上设置有栅极、栅极绝缘层、有源层和源漏极,所述衬底基板上还设置有用于接收和/或发送无线信号的天线。本发明通过将天线设置在阵列基板的衬底基板上,从而将天线直接集成在显示面板中,不但能够减小显示装置中PCB电路板的面积,还能充分利用阵列基板中的空余面积,从而提高显示装置的集成度,缩小显示装置的整体体积,此外,将天线制备于玻璃基板上,由于玻璃基板的绝缘性质使得天线的衬底损耗非常小,从而提高了天线的品质。
Description
技术领域
本发明涉及显示领域,尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着微电子技术的发展,各种传感器都可以通过微电子工艺进行集成,其中以硅基微机电技术为代表的集成器件尤为突出,但是传统的硅基器件在系统级设计中依然是一个独立的物理模块,这对提高整机系统的集成度,缩小体积依然会造成影响。
目前微电子领域中跟随着摩尔定律,器件的特征尺寸已经进入了14纳米的时代,但是一些无源器件的集成却不如有源器件那样简单,天线作为无源器件是电子电路领域不可或缺的组成部分,对于无线通讯终端,天线通常集成在其中PCB电路板的硅基衬底上,但是,由于硅衬底的半导体性质导致天线工作时会有衬底损耗,且天线所占硅片面积较大,不利于无线通讯终端向轻薄的方向发展,从而在一定程度上限制了硅基片上天线的使用。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是提供一种阵列基板及其制作方法、显示装置,能够减小显示装置的体积。
(二)技术方案
为解决上述技术问题,本发明的技术方案提供了一种阵列基板,包括衬底基板,所述衬底基板上设置有栅极、栅极绝缘层、有源层和源漏极,所述衬底基板上还设置有用于接收和/或发送无线信号的天线。
进一步地,所述天线与所述栅极同层设置。
进一步地,还包括位于所述天线上的第一绝缘层以及位于所述第一绝缘层上的信号线,所述第一绝缘层上设置有通孔,所述信号线通过所述通孔与所述天线相连。
进一步地,所述第一绝缘层与所述栅极绝缘层同层设置,所述信号线与所述源漏极同层设置。
进一步地,所述通孔中还设置有连接层,所述信号线通过所述连接层与所述天线相连,所述连接层与所述阵列基板中源漏极与有源层之间的缓冲金属层同层设置。
进一步地,所述天线的图形形状为螺旋状。
为解决上述技术问题,本发明还提供了一种显示装置,包括上述任一的阵列基板。
为解决上述技术问题,本发明还提供了一种阵列基板的制作方法,包括在衬底基板上形成栅极的图形、栅极绝缘层的图形、有源层和源漏极的图形,还包括在所述衬底基板上形成用于接收和/或发送无线信号的天线的图形。
进一步地,在所述衬底基板上形成天线的图形包括:
在所述衬底基板上形成第一金属薄膜;
对所述第一金属薄膜进行图案化处理,以在所述衬底基板的显示区域上形成所述栅极的图形,在所述衬底基板的非显示区域上形成所述天线的图形。
进一步地,在所述衬底基板上形成天线的图形之后还包括:
在所述天线的图形上形成第一绝缘层;
在所述第一绝缘层上形成通孔;
形成第二金属薄膜;
对所述第二金属薄膜图案化处理以形成信号线的图形,所述信号线通过所述通孔与所述天线相连。
进一步地,所述第一绝缘层与所述栅极绝缘层同层形成,所述第二金属薄膜还用于形成阵列基板的源漏极的图形。
进一步地,在所述第一绝缘层上形成通孔之后,且在形成第二金属薄膜之前还包括:
在所述栅极绝缘层上形成所述有源层;
形成第三金属薄膜;
对所述第三金属薄膜进行图案化处理,以在所述有源层的源漏区域上形成缓冲金属层,在所述通孔中形成连接层,所述信号线通过所述连接层与所述天线相连。
(三)有益效果
本发明通过将天线设置在阵列基板的衬底基板上,从而将天线直接集成在显示面板中,不但能够减小显示装置中PCB电路板的面积,还能充分利用阵列基板中的空余面积,从而提高显示装置的集成度,缩小显示装置的整体体积,此外,将天线制备于玻璃基板上,由于玻璃基板的绝缘性质使得天线的衬底损耗非常小,从而提高了天线的品质。
附图说明
图1是本发明实施方式提供的一种阵列基板的示意图;
图2是本发明实施方式提供的一种天线的结构示意图;
图3是本发明实施方式提供的在阵列基板中形成天线的图形的流程图;
图4是本发明实施方式提供的制作阵列基板的流程图;
图5-11是本发明实施方式提供的制作阵列基板的示意图。
具体实施方式
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
本发明实施方式提供了一种阵列基板,该阵列基板包括衬底基板,所述衬底基板上设置有栅极、栅极绝缘层、有源层和源漏极,此外,所述衬底基板上还设置有用于接收和/或发送无线信号的天线。
图1是本发明实施方式提供的一种阵列基板的示意图,该阵列基板包括衬底基板1,所述衬底基板1的显示区域上依次设置有栅极2a、栅极绝缘层3a、有源层4、源漏极6a以及有源层4与源漏极6a之间的缓冲金属层5a,衬底基板1的非显示区域上依次设置有天线2b、第一绝缘层3b和信号线6b,其中,信号线6b通过第一绝缘层3b上的通孔与天线2b相连。
其中,上述的衬底基板1可以为玻璃基板,天线的形状可以为任意形状,优选地,为了提高空间利用率并增强天线的信号接收效果,所述天线2b的图形形状为如图2所示的螺旋状。
本发明实施方式提供的阵列基板,通过将天线设置在阵列基板的衬底基板上,从而将天线直接集成在显示面板中,不但能够减小显示装置中PCB电路板的面积,还能充分利用阵列基板中的空余面积,从而提高显示装置的集成度,缩小显示装置的整体体积,此外,将天线制备于玻璃基板上,由于玻璃基板的绝缘性质使得天线的衬底损耗非常小,从而提高了天线的品质。
优选地,在上述实施方式中,所述天线与所述栅极可同层设置,即天线2b与栅极2a为相同材料且在一次构图工艺中形成。
优选地,在上述实施方式中,所述第一绝缘层与所述栅绝缘层同层设置,所述信号线与所述源漏极同层设置,即栅极绝缘层3a与第一绝缘层3b采用相同材料且在一次构图工艺中形成,信号线6b与源漏极6a为相同材料且在一次构图工艺中形成。
优选地,为了提高信号线6b与天线2b之间的贴附性和导电性,第一绝缘层3b的通孔中还设置有连接层5b,所述信号线6b通过所述连接层5b与所述天线2b相连,优选地,所述连接层5b与缓冲金属层5a同层设置,即连接层5b与缓冲金属层5a为相同材料且在一次构图工艺中形成。
此外,本发明实施方式还提供了一种显示装置,包括上述的阵列基板。本发明实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本发明实施方式还提供了一种阵列基板的制作方法,该阵列基板的制作方法包括在衬底基板上形成栅极的图形、栅极绝缘层的图形、有源层和源漏极的图形,此外,还包括在所述衬底基板上形成用于接收和/或发送无线信号的天线的图形。
其中,上述的衬底基板可以为玻璃基板,天线的形成可通过在衬底基板上形成图案化的金属层实现。
具体地,参见图3,图3是本发明实施方式提供的在阵列基板中形成天线的图形的流程图,包括:
S11:在所述衬底基板上形成第一金属薄膜;
S12:对所述第一金属薄膜进行图案化处理,以在所述衬底基板的显示区域上形成所述栅极的图形,在所述衬底基板的非显示区域上形成所述天线的图形。对于显示装置,由于其中的阵列基板上空余面积较硅基集成电路相比大很多,因此,上述的天线可形成在阵列基板中显示区域之外的空余区域,不但能够降低制作成本,并使制作的产品更加轻薄,还能避免对阵列基板的显示造成影响。
本发明实施方式提供的阵列基板的制作方法,通过在阵列基板的衬底基板上形成天线,从而将天线直接集成在显示面板中,不但能够减小显示装置中PCB电路板的面积,还能充分利用阵列基板中的空余面积,从而提高显示装置的集成度,缩小显示装置的整体体积,此外,将天线制备于玻璃基板上,由于玻璃基板的绝缘性质使得天线的衬底损耗非常小,从而提高了天线的品质。
其中,上述的天线可在制作阵列基板的4MASK或5MASK工艺中同时形成,能够减少天线对制作阵列基板构图次数的增加,降低制作成本。具体地,参见图4,图4是本发明实施方式提供的制作阵列基板的流程图,该方法包括:
S21:在衬底基板上形成第一金属薄膜,其中,该第一金属薄膜覆盖在阵列基板的显示区域以及位于显示区域之外的非显示区域,具体地,参见图5,可在清洗后的透明玻璃基板1上通过真空溅射淀积铜(Cu)材料形成第一金属薄膜2,;
S22:采用构图工艺对第一金属薄膜进行图案化处理,在显示区域形成栅极的图形,在非显示区域形成天线的图形,优选地,天线的图形可以为螺旋状,从而可以尽可能的提高阵列基板中非显示区域的空间利用率,具体地,参见图6,可采用第一块MASK进行曝光、显影、刻蚀同时形成栅极2a的图形和天线2b的图形;
S23:形成绝缘薄膜,该绝缘薄膜不但位于衬底基板的显示区域上方,还位于其非显示区域上方,其中,位于非显示区域覆盖在天线上方的绝缘薄膜为第一绝缘层,位于显示区域的绝缘薄膜为栅极绝缘层,具体地,参见图7,可将氮化硅(SiNx)材料使用PECVD淀积在栅极和天线的图形上形成绝缘薄膜3,得到第一绝缘层和栅极绝缘层;
S24:采用构图工艺对位于非显示区域的第一绝缘层进行刻蚀,形成通孔,具体地,参见图8,使用负性光刻胶和第二块MASK通过曝光、显影,并刻蚀位于非显示区域的氮化硅,形成通孔3c,通孔的位置可位于天线的正上方;
S25:在栅极绝缘层上形成所述有源层,而后在显示区域和非显示区域上形成第三金属薄膜,该第三金属薄膜用于提高相邻两层结构之间贴附性和导电性,具体地,参见图9,在形成有源层4之后,使用离子溅射或蒸镀的方法形成第三金属薄膜5,该第三金属薄膜可采用Cr材料,也可使用Mo、ALNd、MoW、Ti、Ta或Cu材料;
S26:采用构图工艺对第三金属薄膜进行图案化处理,以在所述有源层的源漏区域上形成缓冲金属层,在所述通孔中形成连接层,所述信号线通过所述连接层与所述天线相连,通过上述的缓冲金属层能够提高有源层与源漏极之间的贴附性和导电性,通过连接层能够提高天线与信号线之间的贴附性和导电性,具体地,参见图10,使用第三块MASK以正胶通过曝光、显影、刻蚀,在显示区域形成缓冲金属5a的图形,在非显示区域的通孔3c中形成连接层5b的图形;
S27:在显示区域和非显示区域上形成第二金属薄膜,第二金属薄膜通过上述的连接层与天线相连,具体地,参见图11,可采用蒸镀或使用离子溅射形成第二金属薄膜6;
S28:采用构图工艺对第二金属薄膜进行图案化处理,在显示区域形成源漏极的图形,在非显示区域形成信号线的图形,具体地,使用第四块MASK通过曝光、显影、刻蚀形成的第二金属薄膜层,在显示区域形成源漏极的图形,在非显示区域形成信号线的图形,最终得到如图1和图2所示的天线结构。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明的范畴,本发明的专利保护范围应由权利要求限定。
Claims (8)
1.一种阵列基板,包括衬底基板,所述衬底基板上设置有栅极、栅极绝缘层、有源层和源漏极,其特征在于,所述衬底基板上还设置有用于接收和/或发送无线信号的天线,
所述阵列基板还包括位于所述天线上的第一绝缘层以及位于所述第一绝缘层上的信号线,所述第一绝缘层上设置有通孔,所述信号线通过所述通孔与所述天线相连,
其中,所述信号线与所述源漏极同层设置,所述有源层和所述源漏极之间设置有缓冲金属层,
所述通孔中还设置有连接层,所述信号线通过所述连接层与所述天线相连,所述连接层与所述阵列基板中源漏极与有源层之间的缓冲金属层同层设置。
2.根据权利要求1所述的阵列基板,其特征在于,所述天线与所述栅极同层设置。
3.根据权利要求2所述的阵列基板,其特征在于,所述第一绝缘层与所述栅极绝缘层同层设置,
所述衬底基板为玻璃基板。
4.根据权利要求1-3任一所述的阵列基板,其特征在于,所述天线的图形形状为螺旋状。
5.一种显示装置,其特征在于,包括如权利要求1-4任一所述的阵列基板。
6.一种阵列基板的制作方法,包括在衬底基板上形成栅极的图形、栅极绝缘层的图形、有源层和源漏极的图形,其特征在于,还包括:
在所述衬底基板上形成用于接收和/或发送无线信号的天线的图形,
在所述天线的图形上形成第一绝缘层;
在所述第一绝缘层上形成通孔;
在所述栅极绝缘层上形成所述有源层;
形成第三金属薄膜;
对所述第三金属薄膜进行图案化处理,以在所述有源层的源漏区域上形成缓冲金属层,在所述通孔中形成连接层,所述信号线通过所述连接层与所述天线相连;
形成第二金属薄膜;
对所述第二金属薄膜图案化处理以形成信号线的图形和所述阵列基板的源漏极的图形,所述信号线通过所述通孔与所述天线相连,
所述连接层与所述缓冲金属层同层设置。
7.根据所述权利要求6所述的阵列基板的制作方法,其特征在于,在所述衬底基板上形成天线的图形包括:
在所述衬底基板上形成第一金属薄膜;
对所述第一金属薄膜进行图案化处理,以在所述衬底基板的显示区域上形成所述栅极的图形,在所述衬底基板的非显示区域上形成所述天线的图形。
8.根据所述权利要求6所述的阵列基板的制作方法,其特征在于,所述第一绝缘层与所述栅极绝缘层同层形成。
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US8031312B2 (en) * | 2006-11-28 | 2011-10-04 | Lg Display Co., Ltd. | Array substrate for liquid crystal display device and method of manufacturing the same |
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