AU2021107274A4 - A FDSOI-MOSFET USING HIGH k MATERIAL FOR NANO SCALED CIRCUITS - Google Patents
A FDSOI-MOSFET USING HIGH k MATERIAL FOR NANO SCALED CIRCUITS Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000012212 insulator Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003466 anti-cipated effect Effects 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 11
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 239000010410 layer Substances 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002918 waste heat Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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Abstract
A FDSOI-MOSFET USING HIGH K MATERIAL FOR NANO SCALED CIRCUITS
The present invention relates to a FDSOI-MOSFET using high k material for nano scaled
circuits. In the present invention planar fully depleted silicon on insulator (FD-SOI)
technology relies on an ultra-thin layer of silicon over a buried oxide. To achieve an SOI
structure, a BOX is kept on the substrate material and an active layer is kept on the BOX.
The BOX includes layer of material with a dielectric constant of SiO 2 and a thickness.
The layer of material is positioned between the substrate material and the active layer.
This structure is excellent and most useful for channel regions of 18nm long. Following
invention is described in detail with the help of Figure 1 of sheet 1 showing FDSOI
region of the device.
ilif
204
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Figure 1
209 22 201 210
203 204
207
208
Figure 2
Description
ilif
204
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Figure 1 209 22 201 210 203 204
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Figure 2
A FDSOI-MOSFET USING HIGH k MATERIAL FOR NANO SCALED CIRCUITS
Technical field of invention:
Present invention, in general, relates to a FDSOI-MOSFET using high k material for Nano scaled circuits.
Background of the invention:
The background information herein below relates to the present disclosure but is not necessarily prior art.
Present silicon (Si) nanometer (nm) scale electronic devices are constructed using planar FET topologies. The Field effect transistor gate control gate is composed of a gate dielectric (an oxide and named as a 'gate-oxide') and is typically composed of silicon dioxide (SiO2) or silicon oxy-nitride (SiOxNy) dielectric materials disposed upon a single crystal silicon active layer and/or substrate. Modern logic design is based on complementary-metal-oxide-semiconductors (CMOS) employing charge carrier transport exhibiting both n-type and p-type CMOSFETs
As the planar transistor geometry shrinks in accordance with new fabrication generations or technology nodes, all the CMOSFET dimensions must scale. For example, the gate oxide thickness and gate length must also be scaled in accordance with scaling rules of device. The primary advantage of Complementary MOS logic gates is the logic elements (composed of many nMOS and pMOS transistors) only draw significant current between logic state transitions, which allowing power consumption to be greatly minimized due to negligible dissipation in the off-state. This is an advantage for very high densities of logic elements in ultra-large-scale integrated circuits (ULSICs), such as, microprocessors and mobile and/or portable devices.
Increasing CMOSFET density and circuit function per unit area resulting in CMOSFET sub-threshold leakage current increasing continuously from several nanoamperes per micrometer (nA/ m) at the 130 nm technology node, to currently hundreds of nA/ m at the 45 nm technology node. There are two types of leakage power in ultra-large-scale integrated circuits: dynamic leakage power and static leakage power. Dynamic leakage power is defined as leakage power consumed by a nanoscale CMOS system while doing useful work and static leakage power is leakage power consumed when the system is idle. As the technology node reduces to 32 nm, it has seen leakage power increase to as much as 40% of the total on-chip power consumed. As transistor is scaling down to 18nm and below, the waste heat and power dissipation degrades the VT performance further.
In the current state of the art, the demand for interface standards in high voltage devices/transistors has reached as high as 5V. Partially depleted (PD) silicon oninsulator (SOI) currently used in the fabrication of metal oxide semiconductor field effect transistor (MOSFET) is not able to attain interfaces of this voltage range. The limiting factor lies with the floating body in the PD SOI, which with high voltage behaves like a bipolar transistor. When a bipolar transistor turns on, parasitic bipolar currents lead to breakdown at a high voltage, particularly in an n-type FET (NFET). To overcome this limitation, a source-body tie in the PDSOI FET is used to increase the breakdown voltage. However, the increment of the breakdown voltage is by only a few tenths of a volt, which is too low to meet the demand for high performance interfaces and stacking of FETs. In view of the foregoing, it is desirable to develop an alternative method for fabricating a high voltage SOI FET.
Planar Fully Depleted Silicon on Insulator (FD-SOI) technology relies on an ultra-thin layer of silicon over a Buried Oxide (known as BOX). Ultra-Thin Body devices which are built into this top silicon layer have unique and extremely attractive characteristics. FD-SOI are the promising devices which solves a problem like scaling, leakage and variability issues at the 28nm and below and even process complexity is also less.
There exist many drawbacks in the existing unit or system. Hence the present invention provides a FDSOI-MOSFET using high k material for nano scaled circuits.
Objective of the invention
An objective of the present invention is to attempt to overcome the problems of prior art and provide a FDSOI-MOSFET using high k material for nano scaled circuits.
In a preferred embodiment, the present invention provides direct application that is disclosed for planar single gate FDSOI FETs approaching the 18 nm technology node.
An object of the present invention is to provide FD-SOI device that solves issues like process complexity, scaling down design, leakage power and variability to further shrink CMOS technology beyond 28nm.
Yet another object of the present invention is to reduce the random dopant fluctuation (RDF) which reduces threshold (VT) variability of transistor.
Yet another object of the present invention is to provide a process which is fully compatible with a Bulk process in terms of CMOS fabrication tooling, difficult and exotic process steps and is expected to be simpler than a Bulk process.
These and other objects and characteristics of the present invention will become apparent from the further disclosure to be made in the detailed description given below.
Summary of the invention:
Accordingly, the following invention provides a planar field-effect-transistors (FETs) utilizing fully-depleted semiconductor-on-insulator (FDSOI) substrates using high k material with aluminium metal gate for Nano scaled circuits. Planar fully depleted silicon on insulator (FD-SOI) technology relies on an ultra-thin layer of silicon over a
Buried Oxide (commonly called BOx). To achieve an SOI structure, a BOX is kept on the substrate material and an active layer is kept on the BOX. The BOX includes layer of material with a dielectric constant of SiO 2 and a thickness. The layer of material is positioned between the substrate material and the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is present on the gate insulating region of HfO2 . This structure is excellent and most useful for channel regions of18nm long.
Brief description of drawing:
[001] This invention is described by way of example with reference to the following drawing where,
[002] Figure 1 of sheet 1 illustrates FDSOI region of the device. Where, 101denotes metal gate contact, 102 denotes gate oxide, 103 denotes drain metal contact, 104 denotes drain doping region, 105 denotes source metal contact, 106 denotes source doping region, 107 denotes BOX, 108 denotes substrate, 109 denotes drain to active channel spacer region, 110 denotes source to active channel spacer region, 111 denotes active channel region,
Figure 2 of sheet 1 illustrate short channel thin box FDSOI with ground plane. Where, 201 denote aluminum metal, 202 denotes HfO2, 203 denotes aluminum metal, 204 denotes n+ doping region,
205 denotes aluminum metal, 206 denotes n+ doping region, 207 denotes BOX SiO2, 208 denotes substrate, 209 denotes drain to active channel spacer region,
Figure 3 of sheet 2 illustrate electron density FDSOI device.
Figure 4 of sheet 2 illustrate net doping of FDSOI device.
Figure 5-a of sheet 3 illustrate a graph of a typical drain current ID versus gate voltage VG transfer curve for a single gate FDSOI MOSFET,
Figure 5-b of sheet 3 illustrate a graph of a typical log of drain current ID versus gate voltage VG transfer curve for a single gate FDSOI MOSFET,
Figure 6 of sheet 4 illustrate a graph of a typical drain current ID versus drain voltage VDD curve for a single gate FDSOI MOSFET,
Figure 7 of sheet 4 illustrate a graph of the capacitance of FDSOI,
Figure 8 of sheet 5 illustrate the capacitance model of single gate planner of FDSOI,
Figure 9 of sheet 5 illustrate a graph of the ECEV at VDD=0.45V FDSOI,
Figure 10 of sheet 6 illustrate a graph of the ECEV at VDD=1V FDSOI.
In order that the manner in which the above-cited and other advantages and objects of the invention are obtained, a more particular description of the invention briefly described above will be referred, which are illustrated in the appended drawing. Understanding that these drawing depict only typical embodiment of the invention and therefore not to be considered limiting on its scope, the invention will be described with additional specificity and details through the use of the accompanying drawing.
Detailed description of the invention:
The present invention relates relates to a FDSOI-MOSFET using high k material for nano scaled circuits. Proposed invention provides direct application that is disclosed for planar single gate FDSOI FETs approaching the 18 nm technology node
. In the preferred embodiment, dielectric constant is a measure of how much charge a material can hold and it is commonly known as "High k" (high dielectric constant). Similarly different materials have different abilities to hold charge. The higher "k" increases the transistor capacitance so that the transistor can switch properly between "ON" and "OFF" states, with very low current in OFF state and very high current in ON. High-k gate dielectrics are several times thicker and they reduce gate leakage current more than 100 times. High-k material is incompatible with polysilicon as it introduces threshold voltage pinning and phonon scattering. To reduce this effect, we are using GATE with aluminium having work function 4.7 eV As a result, these devices run without much more heating. If silicon dioxide gate dielectric is replaced with a high-k material, it allows increased gate capacitance without the increasing leakage effects. c = koA / tx
Where, A- capacitance area, k-relative dielectric constant of the material, tx is the dielectric thickness and F0 is the permittivity of free space. This means higher 'k' gives higher capacitance value.
The proposed device is fully depleted silicon interface MOSFET with gate length Lg of 18nm, gate oxide thickness of 0.98nm, metal gate with work function explicitly set to 4.7 eV, heavily n-doped (ND=le+20 CM- 3) source and drain region, Si is the channel material (NA=4.9e+18 CM- 3) and HfO2 is the gate dielectric.
Planar fully depleted silicon on insulator (FD-SOI) technology relies on an ultra-thin layer of silicon over a buried oxide (known as BOX). Ultra-Thin body devices which are built into this top silicon layer have unique and extremely attractive characteristics. Two techniques of buried oxide can be used: standard thickness (PD SOI digital chips today uses typically 145nm thick in volume production), or ultra thin BOx, (10nm or 25nm UT Box, Ultra-Thin buried oxide).
From a physical point of view, the very thin silicon layer enables the silicon under the transistor gate (the body of the transistor) to be fully depleted of charges till next buried oxide. Due to this the gate can now very tightly control the full volume of the transistor active silicon body. This device have much better behaved than a Bulk CMOS transistor, especially as supply voltage (hence gate voltage) gets lower and transistor dimensions reduces. In addition, FD-SOI does not require doping in the channel or lightly doping.
To design a FDSOI transistor, NCH must be low enough so that the gate depletion region extends throughout the entire thickness of the silicon active layer. When the silicon surface layer in the SOI CMOS is thicker than about 50 nm (Lsi>50 nm), the transistor will typically be partially depleted, unless NCH is reduced to such low values that VTH is too low for practical CMOS applications. If the silicon layer thickness is reduced to Lsi<50 nm, the transistor will be fully depleted, even when NCH is increased to produce VTH considerably higher than bulk and PDSOI devices. If the silicon layer thickness is reduced further toward and below Lsi<20 nm, the transistor will remain fully depleted even if NCH is increased considerably to produce even higher threshold voltages (e.g., VTH~700 mV).
In accordance with figure 1 of sheet 1 which illustrates FDSOI region of the device, in the preferred embodiment The proposed device is fully depleted silicon interface MOSFET with gate length Lg of 18nm, gate oxide thickness of 0.98nm, metal gate with work function explicitly set to 4.7 eV, heavily n-doped (ND=le+20 CM-3) source and drain region, Si is the channel material (NA=4.9e+18 CM-3) and HfO 2 is the gate dielectric.
Figure 2 of sheet 1 which illustrates short channel thin box FDSOI with ground plane. The present invention discloses methods and apparatus for performance optimization of short channel and/or short gate length metal-oxide-semiconductor field effect transistors (MOSFETs) on fully depleted semiconductor-on-insulator (FDSOI) substrates via simultaneously optimizing the semiconductor active layer thickness (Lsi), the channel doping concentration (NCH), the buried oxide thickness (LBOX), and the BOX dielectric constant (KBOX). Throughout this disclosure the term "BOX" is used to indicate a buried insulating structure including one layers of material that forms a part of a semiconductor-on-insulator substrate hereinafter designated SOI. Also, while the substrate is usually composed of single crystal material, such as silicon, other materials may be used and, accordingly, the region on which the BOX is situated is referred to herein as "substrate material" and may include anything that operates as a support for the BOX. It will be understood that channel layers described herein are formed of single crystal semiconductor material such as silicon.
In figure 5-a, a typical drain current (ID) versus gate voltage (VG) transfer curve is illustrated for a planar single gate FDSOI MOSFET. To generate IDS versus VGS characteristics curve, it is done by obtaining solutions at each step bias points first and then solving over the swept bias variable at each stepped point. The drain voltage
(VDS) is set to 0.1V to 0.5V, while gate voltage (VGS) isramped from 0 V to 1.0 V by a voltage step of 0.1V. Finally, one IDS - VGS curves are plotted as shown in figure 5a for FDSOI, VDS = 0.1V to 0.5V was chosen to see the current at conduction (inversion layer exists), but at low electric field. An important parameter characterizing FDSOI devices is the sub threshold slope or swing (SS), calculated from the inverse slope of the subthresholdlog drain current (ID) versus gate voltage (VG), given by: SS=d[VG]/d[lOg(ID)]. In figure 5-b, the subthreshold slope is defined as the slope of the curve below the threshold voltage. It can be shown that the subthreshold slope is well approximated by the relation:
SS= kBTq 1ln(10){1a-F/ 1}: Where, a=1+(Csc+Cso1)/CGOX; p=1+(Csc2+CsO1)/CBOX; F=Cso1(CGOXCBOX)
. To generate families of IDS versus VDS curves as shown in figure 6 for FDSOI, gate voltage (VGS) is set OV, 0.1V, 0.15V & 0.2V while drain voltage (VDS) is ramped from 0 V to 1.0 V by a voltage step of 0.1 V.
Figure8 depicts schematically the capacitance model of a FDSOI structure, and can be approximated in terms of gate capacitance CGoX, channel capacitance Cso1, and BOX capacitance CBOX. The surface charges at the gate oxide and Si channel interface, and the surface charges at the Si channel and the BOX interface are denoted as Csci and
Csc 2 , respectively.
The many features and advantages of the invention are apparent from the detailed specification, and thus, it is intended by the appended claims to cover all such features and advantages of the invention which fall within the true spirit and scope of the invention. Further, since numerous modifications and variations will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.
Claims (9)
1. A fully depleted MOSFET having a semiconductor-on-insulator substrate that includes a substrate material, a BOX kept on the substrate material, and an active layer kept on the BOX which includes layer of material with a dielectric constant and a thickness and the layer of material is positioned between the substrate material and the active layer and drain and source regions are formed in the active layer so as to be fully depleted wherein the drain and source regions are separated by a channel region in the active layer and gate insulating layer overlies the channel region of dielectric constant HfO2 and a gate stack with aluminum metal is positioned on the gate insulating region and it is anticipated that the structure is most useful for channel regions of 18nm long.
2. The fully depleted MOSFET as claimed in claim 1 wherein the channel region is equal to 18 nm long.
3. The fully depleted MOSFET as claimed in claim 1 wherein the dielectric constant is SiO2.
4. The fully depleted MOSFET as claimed in claim 3 wherein the thickness of the layer of material fixed.
5. The fully depleted MOSFET as claimed in claim 1 wherein the single crystal substrate material includes silicon but may also be constructed using other suitable material.
6. In the device as claimed in claim 1 two techniques of buried oxide can be used: standard thickness (PD-SOI digital chips today uses typically 145nm thick in volume production), or ultra-thin BOx, (10nm or 25nm UT BOx, Ultra-Thin Buried Oxide).
7. In the device as claimed in claim 1 "BOX" is used to indicate a buried insulating structure including one layers of material that forms a part of a semiconductor-on- insulator substrate hereinafter designated SOI wherein the substrate is usually composed of single crystal material, such as silicon, other materials may be used.
8. In the device as claimed in claim 1 the region on which the BOX is situated is referred to herein as "substrate material" and may include anything that operates as a support for the BOX.
9. Channel layers described in the invention as claimed in claim 1 are formed of single crystal semiconductor material such as silicon.
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