AU2001232248A1 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- AU2001232248A1 AU2001232248A1 AU2001232248A AU3224801A AU2001232248A1 AU 2001232248 A1 AU2001232248 A1 AU 2001232248A1 AU 2001232248 A AU2001232248 A AU 2001232248A AU 3224801 A AU3224801 A AU 3224801A AU 2001232248 A1 AU2001232248 A1 AU 2001232248A1
- Authority
- AU
- Australia
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- semiconductor
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B28/00—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements
- C04B28/02—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing hydraulic cements other than calcium sulfates
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
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- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
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- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Nanotechnology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Inorganic Chemistry (AREA)
- Mathematical Physics (AREA)
- Materials Engineering (AREA)
- Structural Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000038167A JP4191355B2 (en) | 2000-02-10 | 2000-02-10 | Semiconductor integrated circuit device |
JP2000-038167 | 2000-02-10 | ||
PCT/JP2001/000887 WO2001059789A1 (en) | 2000-02-10 | 2001-02-08 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
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AU2001232248A1 true AU2001232248A1 (en) | 2001-08-20 |
Family
ID=18561945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001232248A Abandoned AU2001232248A1 (en) | 2000-02-10 | 2001-02-08 | Semiconductor integrated circuit device |
Country Status (9)
Country | Link |
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US (3) | US6611458B2 (en) |
EP (1) | EP1262996B1 (en) |
JP (1) | JP4191355B2 (en) |
KR (2) | KR100817343B1 (en) |
CN (2) | CN100590739C (en) |
AU (1) | AU2001232248A1 (en) |
DE (1) | DE60143643D1 (en) |
TW (1) | TW506135B (en) |
WO (1) | WO2001059789A1 (en) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1042853A2 (en) * | 1997-11-28 | 2000-10-11 | Abb Ab | Method and device for controlling the magnetic flux with an auxiliary winding in a rotating high voltage electric alternating current machine |
US6829737B1 (en) * | 2000-08-30 | 2004-12-07 | Micron Technology, Inc. | Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results |
JP4043703B2 (en) * | 2000-09-04 | 2008-02-06 | 株式会社ルネサステクノロジ | Semiconductor device, microcomputer, and flash memory |
DE10120670B4 (en) * | 2001-04-27 | 2008-08-21 | Qimonda Ag | Method for repairing hardware faults in memory chips |
US7075829B2 (en) * | 2001-08-30 | 2006-07-11 | Micron Technology, Inc. | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US7087954B2 (en) * | 2001-08-30 | 2006-08-08 | Micron Technology, Inc. | In service programmable logic arrays with low tunnel barrier interpoly insulators |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US6963103B2 (en) * | 2001-08-30 | 2005-11-08 | Micron Technology, Inc. | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7135734B2 (en) * | 2001-08-30 | 2006-11-14 | Micron Technology, Inc. | Graded composition metal oxide tunnel barrier interpoly insulators |
JP3821697B2 (en) | 2001-12-07 | 2006-09-13 | エルピーダメモリ株式会社 | Method for verifying semiconductor integrated circuit device and semiconductor integrated circuit device |
US6943575B2 (en) * | 2002-07-29 | 2005-09-13 | Micron Technology, Inc. | Method, circuit and system for determining burn-in reliability from wafer level burn-in |
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- 2001-02-08 CN CN201010003815.7A patent/CN101916591B/en not_active Expired - Lifetime
- 2001-02-08 EP EP01904349A patent/EP1262996B1/en not_active Expired - Lifetime
- 2001-02-08 WO PCT/JP2001/000887 patent/WO2001059789A1/en active Application Filing
- 2001-02-08 DE DE60143643T patent/DE60143643D1/en not_active Expired - Lifetime
- 2001-02-08 AU AU2001232248A patent/AU2001232248A1/en not_active Abandoned
- 2001-02-08 KR KR1020027006867A patent/KR100816924B1/en active IP Right Grant
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JP4191355B2 (en) | 2008-12-03 |
CN101916591B (en) | 2014-05-07 |
EP1262996A4 (en) | 2007-06-27 |
US20050152186A1 (en) | 2005-07-14 |
US6611458B2 (en) | 2003-08-26 |
KR20070108570A (en) | 2007-11-12 |
KR100816924B1 (en) | 2008-03-26 |
US7149113B2 (en) | 2006-12-12 |
TW506135B (en) | 2002-10-11 |
US20040004879A1 (en) | 2004-01-08 |
KR100817343B1 (en) | 2008-03-27 |
EP1262996A1 (en) | 2002-12-04 |
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