Mangawati et al., 2019 - Google Patents
Clock Gating Integration Using 18T-TSPC Clocked Flip FlopMangawati et al., 2019
- Document ID
- 281110685797949543
- Author
- Mangawati A
- Palecha N
- Publication year
- Publication venue
- 2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT)
External Links
Snippet
Flip-flops are a standout among the most significant and fundamental block of any advanced circuits. The power being on the main consideration in planning of the advanced circuits must be enhanced to improve the exhibition of the circuit. There are many low power …
- 238000000034 method 0 abstract description 57
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Lin et al. | Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes | |
Teh et al. | Conditional data mapping flip-flops for low-power and high-performance systems | |
Lin | Low-power pulse-triggered flip-flop design based on a signal feed-through | |
US8207758B2 (en) | Ultra-low power multi-threshold asynchronous circuit design | |
Hirata et al. | The cross charge-control flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs | |
Consoli et al. | Novel class of energy-efficient very high-speed conditional push–pull pulsed latches | |
Pan et al. | A highly efficient conditional feedthrough pulsed flip-flop for high-speed applications | |
Dobriyal et al. | A high performance D-flip flop design with low power clocking system using MTCMOS technique | |
Wang et al. | A low-power double edge-triggered flip-flop with transmission gates and clock gating | |
Mahmoodi-Meimand et al. | Self-precharging flip-flop (SPFF): A new level converting flip-flop | |
Tsai et al. | An ultra-low-power true single-phase clocking flip-flop with improved hold time variation using logic structure reduction scheme | |
Mahmoodi-Meimand et al. | Dual-edge triggered level converting flip-flops | |
Mangawati et al. | Clock Gating Integration Using 18T-TSPC Clocked Flip Flop | |
Kuamar et al. | Low Power High Speed 15-Transistor Static True Single Phase Flip Flop | |
Fu et al. | Comparative analysis of ultra-low voltage flip-flops for energy efficiency | |
Li et al. | A transmission gate flip-flop based on dual-threshold CMOS techniques | |
Chiou et al. | An energy-efficient dual-edge triggered level-converting flip-flop | |
Bhuvana et al. | A Survey on sequential elements for low power clocking system | |
Cai et al. | Evaluation and analysis of single-phase clock flip-flops for NTV applications | |
Morell et al. | Evaluation of four power gating schemes applied to ecrl adiabatic logic | |
Park et al. | Conditional-Boosting flip-flop for near-threshold voltage application | |
Krishna et al. | Design and Analysis of 18T Master-Slave Flip-Flop Circuit | |
Chen et al. | Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme | |
Maheshwari | A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops | |
Kumar et al. | Static low-power 17t true single phase clocking flip-flop based on logic structure optimization |