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Jenila et al., 2023 - Google Patents

Implementation of Routing-denser PnR Flow for an Efficient IC Block Level Design

Jenila et al., 2023

Document ID
2573098768050573941
Author
Jenila C
Kumar K
Sreekanth T
Rao T
et al.
Publication year
Publication venue
2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON)

External Links

Snippet

This paper presents Place and Route (PnR) flow for a block level design by setting a target for routing density. The PnR flow includes the placement of standard cells and routing of interconnects between them. Routing density is a key factor in determining the performance …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
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    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
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