[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Alghareb et al., 2017 - Google Patents

Designing and evaluating redundancy-based soft-error masking on a continuum of energy versus robustness

Alghareb et al., 2017

View PDF
Document ID
8736205303071658409
Author
Alghareb F
Ashraf R
DeMara R
Publication year
Publication venue
IEEE Transactions on Sustainable Computing

External Links

Snippet

Near-threshold computing is an effective strategy to reduce the power dissipation of deeply- scaled CMOS logic circuits. However, near-threshold strategies exacerbate the impact of delay variations on device performance and increase the susceptibility to soft errors due to …
Continue reading at www.osti.gov (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Kwon et al. Razor-lite: A light-weight register for error detection by observing virtual supply rails
Yan et al. Double-node-upset-resilient latch design for nanoscale CMOS technology
Zhang et al. irazor: Current-based error detection and correction scheme for pvt variation in 40-nm arm cortex-r4 processor
Alghareb et al. Designing and evaluating redundancy-based soft-error masking on a continuum of energy versus robustness
Omana et al. Latch susceptibility to transient faults and new hardening approach
Guo et al. Design and evaluation of low-complexity radiation hardened CMOS latch for double-node upset tolerance
Mitra et al. The resilience wall: Cross-layer solution strategies
Eftaxiopoulos et al. DIRT latch: A novel low cost double node upset tolerant latch
Keller et al. DD1: a QDI, radiation-hard-by-design, near-threshold 18uW/MIPS microcontroller in 40nm bulk CMOS
Jahinuzzaman et al. TSPC-DICE: A single phase clock high performance SEU hardened flip-flop
Jin et al. In situ error detection techniques in ultralow voltage pipelines: Analysis and optimizations
Alghareb et al. Energy and delay tradeoffs of soft-error masking for 16-nm FinFET logic paths: Survey and impact of process variation in the near-threshold region
Lin et al. A low-cost radiation hardened flip-flop
Das et al. Frequency-independent warning detection sequential for dynamic voltage and frequency scaling in ASICs
Vangal et al. Wide-range many-core SoC design in scaled CMOS: Challenges and opportunities
Bal et al. Revamping timing error resilience to tackle choke points at NTC systems
Hua et al. Low area, low power, robust, highly sensitive error detecting latch for resilient architectures
Yang et al. Reliable state retention-based embedded processors through monitoring and recovery
Niaraki Asli et al. High efficiency time redundant hardened latch for reliable circuit design
Kim et al. Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline
Alghareb Soft-error resilience framework for reliable and energy-efficient CMOS logic and spintronic memory architectures
Shin et al. One-cycle correction of timing errors in pipelines with standard clocked elements
Krstic et al. Cross-Layer Digital Design Flow for Space Applications
Gherman et al. Error prediction based on concurrent self-test and reduced slack time
Tajima et al. A low power soft error hardened latch with schmitt-trigger-based C-Element