Liu et al., 2002 - Google Patents
Epitaxial La-doped SrTiO 3 on silicon: A conductive template for epitaxial ferroelectrics on siliconLiu et al., 2002
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- 8614809047344936176
- Author
- Liu B
- Maki K
- So Y
- Nagarajan V
- Ramesh R
- Lettieri J
- Haeni J
- Schlom D
- Tian W
- Pan X
- Walker F
- McKee R
- Publication year
- Publication venue
- Applied physics letters
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Snippet
Use of an epitaxial conducting template has enabled the integration of epitaxial ferroelectric perovskites on silicon. The conducting template layer, La x Sr 1− x TiO 3 (LSTO), deposited onto (001) silicon wafers by molecular-beam epitaxy is then used to seed {001}-oriented …
- 229910052710 silicon 0 title abstract description 21
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
- H01L27/112—Read-only memory structures [ROM] and multistep manufacturing processes therefor
- H01L27/115—Electrically programmable read-only memories; Multistep manufacturing processes therefor
- H01L27/11502—Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors
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- H01L39/2419—Processes or apparatus peculiar to the manufacture or treatment of devices provided for in H01L39/00 or of parts thereof the superconducting material comprising copper oxide
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
- H01L29/40—Electrodes; Multistep manufacturing processes therefor
- H01L29/43—Electrodes; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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