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Insights: openhwgroup/cva6
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1 Release published by 1 person
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cv32a60x-v6.0.0 CV32A60X 6.0.0
published
Apr 23, 2025
17 Pull requests merged by 11 people
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Add Agilex HPS in Altera FPGA design
#2956 merged
May 15, 2025 -
Zero pad
wdatatracer port based onXLEN#2957 merged
May 14, 2025 -
Bugfix/conflicting declaration read elf
#2958 merged
May 14, 2025 -
Add missing value to return
#2959 merged
May 12, 2025 -
Adding support for Scalar Cryptography Extensions (Zkn -- Zbkx, Zkne, Zknd, Zknh)
#2804 merged
May 11, 2025 -
Proposed CI fix: remove edatools repository from prerequisites
#2953 merged
May 5, 2025 -
Fix cvxif_off_instr_n in issue_read_operands
#2944 merged
Apr 29, 2025 -
Instruction Trace Interface
#2927 merged
Apr 25, 2025 -
WAW hazards elimination
#2881 merged
Apr 23, 2025 -
Fix 2943
#2945 merged
Apr 23, 2025 -
Fix URLs to point to CV32A60X-specific files on RTDs.
#2938 merged
Apr 16, 2025 -
Add back ICACHE/DCACHE CSRs, update Yaml+adocs. Fix design doc Makefile.
#2937 merged
Apr 16, 2025 -
docs: add missing link to RST 60x design doc
#2932 merged
Apr 15, 2025 -
docs: link to CV32A60X design documentation
#2931 merged
Apr 15, 2025 -
docs: generate HTML for 60x design doc
#2930 merged
Apr 15, 2025 -
Generate cv32a60x design document
#2924 merged
Apr 15, 2025 -
CV32A60X ISA
#2922 merged
Apr 15, 2025
9 Pull requests opened by 7 people
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MMU: H-Mode PTW permission and TLB fix
#2933 opened
Apr 15, 2025 -
Indicate dirty in mstatus.FS correctly
#2936 opened
Apr 16, 2025 -
[DO NOT MERGE] docs: Review of the current cv32a60x documentation
#2939 opened
Apr 16, 2025 -
hpdcache: update the submodule
#2940 opened
Apr 18, 2025 -
build(deps): bump verif/core-v-verif from `60e5724` to `21da3b0`
#2941 opened
Apr 21, 2025 -
Document how to load and run zephyr RTOS
#2949 opened
Apr 30, 2025 -
Add ALU to ALU bypass in superscalar mode
#2951 opened
May 3, 2025 -
split readme
#2954 opened
May 5, 2025 -
FPGA: add ZCU104 and PYNQ_Z2 compatibility through block design support
#2965 opened
May 14, 2025
13 Issues closed by 7 people
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FPGA synthesis: Long data path inside the FPU module
#2895 closed
May 11, 2025 -
[BUG] <title>PMP does not check misaligned accesses properly
#2955 closed
May 9, 2025 -
Unable to run any simulations, SPIKE install fails
#2836 closed
May 8, 2025 -
PMP may allow all acces in Machine Mode even if configuration is locked
#2947 closed
May 5, 2025 -
[BUG] Incorrect assignment of original instruction in issue_read_operands?
#2935 closed
Apr 29, 2025 -
[TASK] CV32A60X ifdef, ifndef, define status
#2948 closed
Apr 28, 2025 -
[TASK] CV32A60X functional coverage status
#2908 closed
Apr 28, 2025 -
[TASK] Build ReadTheDocs documentation from `cv32a60x` branch
#2861 closed
Apr 28, 2025 -
[BUG] shared TLB seems to be doing false hit
#2943 closed
Apr 23, 2025 -
Issue while running riscv_config_gen.py for configuration cv64a60ax
#2827 closed
Apr 19, 2025 -
[TASK] CV32A60X code coverage status
#2870 closed
Apr 18, 2025 -
toolchain build error
#2757 closed
Apr 15, 2025
9 Issues opened by 7 people
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agilex sdcard status
#2964 opened
May 14, 2025 -
Minor issue in declaring the type of the rvfi_probe_o within the file ariane_xilinx.sv
#2963 opened
May 13, 2025 -
[BUG] Unexpected trap into debug mode during float regs' initialization
#2962 opened
May 9, 2025 -
[Question] Poor performance in ariane_tb caused by memory preload, should we fix?
#2961 opened
May 8, 2025 -
[UVM] Mixing of task and functions
#2960 opened
May 7, 2025 -
[BUG] "More then one hit in TLB assertion" failing
#2952 opened
May 5, 2025 -
README is too long
#2950 opened
May 2, 2025 -
[BUG] spurious memory access by mmu
#2946 opened
Apr 23, 2025 -
[BUG] mstatus.FS does not indicate dirty correctly
#2934 opened
Apr 16, 2025
10 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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Simulate veri-testharness with RISC-V proxy kernel. Initial commit
#2900 commented on
May 15, 2025 • 1 new comment -
[BUG] No reference for Synthesis
#2860 commented on
Apr 15, 2025 • 0 new comments -
in mmu lsu unit response valid (lsu_valid_o) remains high for 2 clock cycles
#2903 commented on
Apr 16, 2025 • 0 new comments -
[BUG] type "hpdcache_data_word_t" is used before its declaration.
#2919 commented on
Apr 18, 2025 • 0 new comments -
[BUG] Wrong permission check walking HGATP
#2910 commented on
Apr 23, 2025 • 0 new comments -
scoreboard.sv [BUG] : RTL assertion failed
#2376 commented on
Apr 28, 2025 • 0 new comments -
[BUG] uvme_exception_covg and uvme_illegal_instr_covg not compliant LRM
#2026 commented on
May 7, 2025 • 0 new comments -
[BUG] Can't find export or definition for 'read_section_sv' and other used functions causing Fatal Errors when not found in any .so included with Questasim
#2744 commented on
May 8, 2025 • 0 new comments -
How to port this ariena CPU to other system
#2876 commented on
May 9, 2025 • 0 new comments -
Fix access to tp register for LLVM in syscalls.c
#2791 commented on
May 11, 2025 • 0 new comments