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Insights: openhwgroup/cva6
Overview
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- 4 Merged pull requests
- 0 Open pull requests
- 4 Closed issues
- 5 New issues
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4 Pull requests merged by 3 people
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Zero pad
wdatatracer port based onXLEN#2957 merged
May 14, 2025 -
Bugfix/conflicting declaration read elf
#2958 merged
May 14, 2025 -
Add missing value to return
#2959 merged
May 12, 2025 -
Adding support for Scalar Cryptography Extensions (Zkn -- Zbkx, Zkne, Zknd, Zknh)
#2804 merged
May 11, 2025
4 Issues closed by 3 people
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FPGA synthesis: Long data path inside the FPU module
#2895 closed
May 11, 2025 -
[BUG] <title>PMP does not check misaligned accesses properly
#2955 closed
May 9, 2025 -
Unable to run any simulations, SPIKE install fails
#2836 closed
May 8, 2025
5 Issues opened by 4 people
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agilex sdcard status
#2964 opened
May 14, 2025 -
Minor issue in declaring the type of the rvfi_probe_o within the file ariane_xilinx.sv
#2963 opened
May 13, 2025 -
[BUG] Unexpected trap into debug mode during float regs' initialization
#2962 opened
May 9, 2025 -
[Question] Poor performance in ariane_tb caused by memory preload, should we fix?
#2961 opened
May 8, 2025 -
[UVM] Mixing of task and functions
#2960 opened
May 7, 2025
9 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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[BUG] uvme_exception_covg and uvme_illegal_instr_covg not compliant LRM
#2026 commented on
May 7, 2025 • 0 new comments -
[BUG] Can't find export or definition for 'read_section_sv' and other used functions causing Fatal Errors when not found in any .so included with Questasim
#2744 commented on
May 8, 2025 • 0 new comments -
How to port this ariena CPU to other system
#2876 commented on
May 9, 2025 • 0 new comments -
Fix access to tp register for LLVM in syscalls.c
#2791 commented on
May 11, 2025 • 0 new comments -
Simulate veri-testharness with RISC-V proxy kernel. Initial commit
#2900 commented on
May 13, 2025 • 0 new comments -
MMU: H-Mode PTW permission and TLB fix
#2933 commented on
May 14, 2025 • 0 new comments -
build(deps): bump verif/core-v-verif from `60e5724` to `21da3b0`
#2941 commented on
May 12, 2025 • 0 new comments -
Add ALU to ALU bypass in superscalar mode
#2951 commented on
May 14, 2025 • 0 new comments -
Add Agilex HPS in Altera FPGA design
#2956 commented on
May 14, 2025 • 0 new comments