SIGPLAN: Vol 26, No 4

Volume 26, Issue 4Apr. 1991Special issue of a journal and a proceedings

Volume 26, Issue 4

Apr. 1991

Editor:

David A. Patterson
Univ. of California, Berkeley

Publisher:

Association for Computing Machinery
New York
NY
United States

ISSN:0362-1340

EISSN:1558-1160

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A variable instruction stream extension to the VLIW architecture

Pages 2–14https://doi.org/10.1145/106973.106976

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Reducing the branch penalty by rearranging instructions in a double-width memory

Pages 15–27https://doi.org/10.1145/106973.106977

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The floating point performance of a superscalar SPARC processor

Pages 28–37https://doi.org/10.1145/106973.106978

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Software prefetching

Pages 40–52https://doi.org/10.1145/106973.106979

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High-bandwidth data memory systems for superscalar processors

Pages 53–62https://doi.org/10.1145/106973.106980

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The cache performance and optimizations of blocked algorithms

Pages 63–74https://doi.org/10.1145/106973.106981

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The effect of context switches on cache performance

Pages 75–84https://doi.org/10.1145/106973.106982

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A portable interface for on-the-fly instruction space modification

David Keppel

Pages 86–95https://doi.org/10.1145/106973.106983

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Virtual memory primitives for user programs

Pages 96–107https://doi.org/10.1145/106973.106984

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The interaction of architecture and operating system design

Pages 108–120https://doi.org/10.1145/106973.106985

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Integrating register allocation and instruction scheduling for RISCs

Pages 122–131https://doi.org/10.1145/106973.106986

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Code generation for streaming: an access/execute mechanism

Pages 132–141https://doi.org/10.1145/106973.106987

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Efficient Implementation of high-level parallel programs

Pages 142–151https://doi.org/10.1145/106973.376053

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Vector register design for polycyclic vector scheduling

Pages 154–163https://doi.org/10.1145/106973.328664

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Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Pages 164–175https://doi.org/10.1145/106973.106990

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Limits of instruction-level parallelism

David W. Wall

Pages 176–188https://doi.org/10.1145/106973.106991

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Performance consequences of parity placement in disk arrays

Pages 190–199https://doi.org/10.1145/106973.106992

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Combining the concepts of compression and caching for a two-level filesystem

Pages 200–211https://doi.org/10.1145/106973.106993

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NUMA policies and their relation to memory architecture

Pages 212–221https://doi.org/10.1145/106973.106994

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LimitLESS directories: A scalable cache coherence scheme

Pages 224–234https://doi.org/10.1145/106973.106995

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An efficient cache-based access anomaly detection scheme

Pages 235–244https://doi.org/10.1145/106973.106996

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Performance evaluation of memory consistency models for shared-memory multiprocessors

Pages 245–257https://doi.org/10.1145/106973.106997

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Process coordination with fetch-and-increment

Pages 260–268https://doi.org/10.1145/106973.106998

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Synchronization without contention

Pages 269–278https://doi.org/10.1145/106973.106999

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The case for a read barrier

Douglas Johnson

Pages 279–287https://doi.org/10.1145/106973.107000

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An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks

Pages 290–302https://doi.org/10.1145/106973.107001

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Performance characteristics of architectural features of the IBM RISC System/6000

Pages 303–309https://doi.org/10.1145/106973.107002

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Performance from architecture: comparing a RISC and a CISC with similar hardware organization

Pages 310–319https://doi.org/10.1145/106973.107003

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