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Code generation for streaming: an access/execute mechanism

Authors:

Manuel E. Benitez,

Jack W. DavidsonAuthors Info & Claims

ACM SIGPLAN Notices, Volume 26, Issue 4

Pages 132 - 141

https://doi.org/10.1145/106973.106987

Published: 01 April 1991 Publication History

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Cited By

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Davidson JFraser C(2004)Automatic generation of peephole optimizationsACM SIGPLAN Notices10.1145/989393.98940739:4(104-111)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1145/989393.989407
Ottoni GRangan RStoler AAugust D(2005)Automatic Thread Extraction with Decoupled Software PipeliningProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.13(105-118)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.13
McKee SWulf WLandon T(2005)Bounds on memory bandwidth in streamed computationsEURO-PAR '95 Parallel Processing10.1007/BFb0020457(83-99)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0020457
Show More Cited By

Index Terms

Code generation for streaming: an access/execute mechanism
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Run-time code generation (RTCG) would be used routinely if application programmers had a facility with which they could easily create their own run-time code generators, because it would offer benefits both in terms of the efficiency of the code that ...
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Run-time code generation (RTCG) would be used routinely if application programmers had a facility with which they could easily create their own run-time code generators, because it would offer benefits both in terms of the efficiency of the code that ...
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Information & Contributors

Information

Published In

ACM SIGPLAN Notices Volume 26, Issue 4

Special issue of a journal and a proceedings

Apr. 1991

305 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/106973

Editor:
David A. Patterson
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
April 1991
320 pages
ISBN:0897913809
DOI:10.1145/106972
Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1991

Published in SIGPLAN Volume 26, Issue 4

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Cited By

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Davidson JFraser C(2004)Automatic generation of peephole optimizationsACM SIGPLAN Notices10.1145/989393.98940739:4(104-111)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1145/989393.989407
Ottoni GRangan RStoler AAugust D(2005)Automatic Thread Extraction with Decoupled Software PipeliningProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.13(105-118)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.13
McKee SWulf WLandon T(2005)Bounds on memory bandwidth in streamed computationsEURO-PAR '95 Parallel Processing10.1007/BFb0020457(83-99)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0020457
Pineo PSoffa M(2005)A practical approach to the symbolic debugging of parallelized codeCompiler Construction10.1007/3-540-57877-3_23(339-356)Online publication date: 30-May-2005
https://doi.org/10.1007/3-540-57877-3_23
Benitez MDavidson J(2005)The advantages of machine-dependent global optimizationProgramming Languages and System Architectures10.1007/3-540-57840-4_27(105-124)Online publication date: 31-May-2005
https://doi.org/10.1007/3-540-57840-4_27
Karl W(2005)Some design aspects for VLIW architectures exploiting fine-grained parallelismPARLE '93 Parallel Architectures and Languages Europe10.1007/3-540-56891-3_47(582-599)Online publication date: 27-May-2005
https://doi.org/10.1007/3-540-56891-3_47
Duesterwald EGupta RSoffa M(2005)Register pipelining: An integrated approach to register allocation for scalar and subscripted variablesCompiler Construction10.1007/3-540-55984-1_18(192-206)Online publication date: 1-Jun-2005
https://doi.org/10.1007/3-540-55984-1_18
Mallik AWildrick MMemik GJoshi RChoi KTiwari VRoy K(2004)Design and implementation of correlating cachesProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013255(58-61)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013255
Mohan TSupinski BMcKee SMueller FYoo ASchulz MMcGraw J(2003)Identifying and Exploiting Spatial Regularity in Data Memory ReferencesProceedings of the 2003 ACM/IEEE conference on Supercomputing10.1145/1048935.1050199Online publication date: 15-Nov-2003
https://dl.acm.org/doi/10.1145/1048935.1050199
Memik GMangione-Smith WBhattacharyya SMudge TWolf WJerraya A(2002)Increasing power efficiency of multi-core network processors through data filteringProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581647(108-116)Online publication date: 8-Oct-2002
https://dl.acm.org/doi/10.1145/581630.581647
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