Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation

Capacitive coupling between interconnects can lead to pattern-dependent delay variation. Statistical process variation results in variation in gate and interconnects delays, and interconnect coupling. These effects become increasingly important in deep submicron circuits. In this work, we describe a statistical timing analyzer for combinational circuits that considers these effects. The tool searches for the input vectors that sensitize the longest paths, and searches for the signal couplings that maximize the delay on these paths, and the sensitizations for these couplings. Under those sensitizations the spatially correlated variation in interconnects, parasitics is analyzed to determine the best and worst-case timing behaviors, assuming gate delay variations are random. We demonstrate timing analysis results on a subset of the ISCAS85 benchmark circuits for which we have synthesized layouts.