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Article

A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains

Published: 30 April 2000 Publication History

Abstract

This paper presents a rapid and scalable built-in self-test (BIST) diagnosis scheme for handling BIST environments with a large number of scan chains. The problem of identifying which scan cells captured errors during the BIST session is formulated here as a search problem. A scheme for adding a small amount of additional hardware that provides the capability of performing very efficient search techniques to locate the error capturing scan cells is proposed.The scheme can accurately diagnose any number of error capturing scan cells. The error-capturing scan cells can be located in time complexity that is logarithmic in the total number of scan cells in the design using the proposed approach. The technique scales well for very large designs. The hardware overhead is logarithmic in the number of scan cells and linear in the number of scan chains.

Cited By

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  • (2010)BISDProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871225(1243-1248)Online publication date: 8-Mar-2010
  • (2007)Column Parity Row Selection (CPRS) BIST Diagnosis TechniqueIEEE Transactions on Computers10.1109/TC.2007.4256:3(402-414)Online publication date: 1-Mar-2007
  • (2004)Combinatorial group testing methods for the BIST diagnosis problemProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015118(113-116)Online publication date: 27-Jan-2004
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  1. A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains

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    Published In

    cover image Guide Proceedings
    VTS '00: Proceedings of the 18th IEEE VLSI Test Symposium
    April 2000
    ISBN:0769506135

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 30 April 2000

    Author Tags

    1. Design-for-Debug
    2. Design-for-Diagnosis
    3. Design-for-Testability
    4. Digital Testing
    5. Integrated Circuits
    6. LFSR
    7. Multi-Input Signature Register
    8. built-in self-test Scan Chains

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    Cited By

    View all
    • (2010)BISDProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871225(1243-1248)Online publication date: 8-Mar-2010
    • (2007)Column Parity Row Selection (CPRS) BIST Diagnosis TechniqueIEEE Transactions on Computers10.1109/TC.2007.4256:3(402-414)Online publication date: 1-Mar-2007
    • (2004)Combinatorial group testing methods for the BIST diagnosis problemProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015118(113-116)Online publication date: 27-Jan-2004
    • (2003)A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault DiagnosisProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022731Online publication date: 3-Mar-2003
    • (2002)Effective diagnostics through interval unloads in a BIST environmentProceedings of the 39th annual Design Automation Conference10.1145/513918.513984(249-254)Online publication date: 10-Jun-2002

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