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GLARE: global and local wiring aware routability evaluation

Authors:

Natarajan Viswanathan,

Charles J. Alpert,

Andrew D. Huber,

Gustavo E. Tellez,

Douglas Keller,

Sachin S. SapatnekarAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 768 - 773

https://doi.org/10.1145/2228360.2228499

Published: 03 June 2012 Publication History

Abstract

Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router and serves the dual purpose of (i) seeding the following phases of a router and (ii) evaluating whether the current design point is routable. Lately, it has become common to use a "light mode" version of the global router, similar to today's academic routers, to quickly evaluate the routability of a given placement. This use model suffers from two primary weaknesses: (i) it does not adequately model the local routing resources, while the model is important to remove opens and shorts and eliminate DRC violations, (ii) the metrics used to represent congestion are non-intuitive and often fail to pinpoint the key issues that need to be addressed. This paper presents solutions to both issues, and empirically demonstrates that incorporating the proposed solutions within a global routing based congestion analyzer yields a more accurate view of design routability.

References

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Cited By

Chai ZZhao YLiu WLin YWang RHuang R(2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning StrategiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328797042:12(5034-5047)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3287970
Kazda MMonkowski MAntony G(2023)APEX: Recommending Design Flow Parameters Using a Variational Autoencoder2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299872(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299872
Zheng SZou LXu PLiu SYu BWong M(2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323800
Show More Cited By

Index Terms

GLARE: global and local wiring aware routability evaluation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Citations

Cited By

Chai ZZhao YLiu WLin YWang RHuang R(2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning StrategiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328797042:12(5034-5047)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3287970
Kazda MMonkowski MAntony G(2023)APEX: Recommending Design Flow Parameters Using a Variational Autoencoder2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299872(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299872
Zheng SZou LXu PLiu SYu BWong M(2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323800
Zheng SZou LLiu SLin YYu BWong M(2023)Mitigating Distribution Shift for Congestion Optimization in Global Placement2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247660(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247660
Melnyk VMelnyk A(2023)Analysis of Methods, Approaches and Tools for Organizing Self-Improvement of Computer Systems2023 13th International Conference on Advanced Computer Information Technologies (ACIT)10.1109/ACIT58437.2023.10275490(506-511)Online publication date: 21-Sep-2023
https://doi.org/10.1109/ACIT58437.2023.10275490
Brenner USilvanus A(2023) BonnLogicIntegration, the VLSI Journal10.1016/j.vlsi.2022.11.01489:C(123-133)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1016/j.vlsi.2022.11.014
Chhabria VSapatnekar S(2022)OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313255441:10(3515-3528)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3132554
He JAgarwal UYang YManohar RPingali K(2022)SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712557(586-591)Online publication date: 17-Jan-2022
https://doi.org/10.1109/ASP-DAC52403.2022.9712557
Brenner USilvanus AWang T(2022)Delay Optimization of Combinational Logic by AND-OR Path RestructuringProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712548(403-409)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712548
Chhabria VSapatnekar S(2022)Deep Learning for Analyzing Power Delivery Networks and Thermal NetworksMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_5(115-150)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_5
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