Article

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

Authors:

Seiji Miura,

Kazushige Ayukawa,

Takao WatanabeAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 358 - 363

https://doi.org/10.1145/383082.383183

Published: 06 August 2001 Publication History

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References

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H.Tanaka, et al., "Sub-1-m A Dynamic Reference Voltage Generator for Battery-Operated DRAMs," 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 87-88.

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K.Itoh, et al., "Trends in Low-Power RAM Circuit Technologies," Proceedings of The IEEE vol. 83, No. 4, April 1995.

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T.Inaba, et al., "250mV Bit-Line Swing Scheme for a 1V 4Gb DRAM," 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 99-100.

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T.Yamagata, et al., "Circuit Design Techniques for Low-Voltage Operation and/or Giga-Scale DRAMs," 1995 ISSCC Digest of Technical Papers, pp. 248-249.

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T.Watanabe, et al., "Access Optimizer to Overcome the Future Walls of Embedded DRAMs in the Era of Systems on Silicon," 1999 ISSCC Digest of Technical Papers, pp. 370- 371.

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Y.Kanno, et al., "A DRAM System for Consistently Reducing CPU Wait Cycles," 1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 131-132.

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Y.Kim, et al., "A Memory Access System for Merged Memory with Logic LSIs," 1999 AP-ASIC, pp. 384-387.

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Cited By

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MAYURI CSANJAY AVIJAY C(2017)AN EXPOSITION ON RESCALING OF CACHEi-manager's Journal on Computer Science10.26634/jcom.5.1.137945:1(22)Online publication date: 2017
https://doi.org/10.26634/jcom.5.1.13794
Suri TAggarwal A(2017)Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUsArchitecture of Computing Systems - ARCS 201710.1007/978-3-319-54999-6_8(99-110)Online publication date: 4-Mar-2017
https://doi.org/10.1007/978-3-319-54999-6_8
Ghasempour MJaleel AGarside JLuján MJacob B(2016)HAPPYProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989101(311-321)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.1145/2989081.2989101
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Index Terms

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
      2. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Semiconductor memory
      1. Dynamic memory

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Information

Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01

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SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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MAYURI CSANJAY AVIJAY C(2017)AN EXPOSITION ON RESCALING OF CACHEi-manager's Journal on Computer Science10.26634/jcom.5.1.137945:1(22)Online publication date: 2017
https://doi.org/10.26634/jcom.5.1.13794
Suri TAggarwal A(2017)Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUsArchitecture of Computing Systems - ARCS 201710.1007/978-3-319-54999-6_8(99-110)Online publication date: 4-Mar-2017
https://doi.org/10.1007/978-3-319-54999-6_8
Ghasempour MJaleel AGarside JLuján MJacob B(2016)HAPPYProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989101(311-321)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.1145/2989081.2989101
Awasthi MNellans DBalasubramonian RDavis A(2011)Prediction Based DRAM Row-Buffer Management in the Many-Core EraProceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2011.31(183-184)Online publication date: 10-Oct-2011
https://dl.acm.org/doi/10.1109/PACT.2011.31
Huan DLi ZHu WLiu Z(2006)Processor directed dynamic page policyProceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11859802_10(109-122)Online publication date: 6-Sep-2006
https://dl.acm.org/doi/10.1007/11859802_10
Ker NChen CYasuura H(2003)An effective SDRAM power mode management scheme for performance and energy sensitive embedded systemsProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119879(515-518)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119879
Park SYi YPark I(2003)High performance memory mode control for HDTV decodersIEEE Transactions on Consumer Electronics10.1109/TCE.2003.126123949:4(1348-1353)Online publication date: 1-Nov-2003
https://dl.acm.org/doi/10.1109/TCE.2003.1261239
Kobayashi SFukuda A(2003)Design of a library for DRAM power reduction in an embedded multi-task kernel2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) (Cat. No.03CH37490)10.1109/PACRIM.2003.1235705(5-8)Online publication date: 2003
https://doi.org/10.1109/PACRIM.2003.1235705
Seong-Il Park In-Cheol Park (2003)History-based memory mode prediction for improving memory performanceProceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.10.1109/ISCAS.2003.1206226(V-185-V-188)Online publication date: 2003
https://doi.org/10.1109/ISCAS.2003.1206226
Ning-Yaun Ker Chung-Ho Chen (2003)An effective SDRAM power mode management scheme for performance and energy sensitive embedded systemsProceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.10.1109/ASPDAC.2003.1195071(515-518)Online publication date: 2003
https://doi.org/10.1109/ASPDAC.2003.1195071
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