Article

Analysis and implementation of charge recycling for deep sub-micron buses

Authors:

Paul Sotiriadis,

Theodoros Konstantakopoulos,

Anantha ChandrakasanAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 364 - 369

https://doi.org/10.1145/383082.383184

Published: 06 August 2001 Publication History

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Cited By

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Yoshikawa TIwata TShibazaki JMuroga SIkeda H(2020)A Charge Recycling Stacked I/O in Standard CMOS Technology for Wide TSV Data BusIEICE Electronics Express10.1587/elex.17.20200112Online publication date: 2020
https://doi.org/10.1587/elex.17.20200112
Weerasekera RPamunuwa DZheng LTenhunen H(2019)Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755516:5(589-593)Online publication date: 14-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2008.917555
Patel KLee WPedram MNarayanan VYan ZMacii EBhanja S(2008)In-order pulsed charge recycling in off-chip data busesProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366198(371-374)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366198
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Index Terms

Analysis and implementation of charge recycling for deep sub-micron buses
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

Acceptance Rates

ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Yoshikawa TIwata TShibazaki JMuroga SIkeda H(2020)A Charge Recycling Stacked I/O in Standard CMOS Technology for Wide TSV Data BusIEICE Electronics Express10.1587/elex.17.20200112Online publication date: 2020
https://doi.org/10.1587/elex.17.20200112
Weerasekera RPamunuwa DZheng LTenhunen H(2019)Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755516:5(589-593)Online publication date: 14-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2008.917555
Patel KLee WPedram MNarayanan VYan ZMacii EBhanja S(2008)In-order pulsed charge recycling in off-chip data busesProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366198(371-374)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366198
Weerasekera RPamunuwa DZheng LTenhunen HHutton MDambre J(2006)Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regimeProceedings of the 2006 international workshop on System-level interconnect prediction10.1145/1117278.1117301(113-120)Online publication date: 4-Mar-2006
https://dl.acm.org/doi/10.1145/1117278.1117301
Kaul HSylvester DBlaauw DMudge TAustin T(2005)DVS for On-Chip Bus Designs Based on Timing Error CorrectionProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.125(80-85)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.125
Kaul HSylvester DAnders MKrishnamurthy RJoshi RChoi KTiwari VRoy K(2004)Spatial encoding circuit techniques for peak power reduction of on-chip high-performance busesProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013286(194-199)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013286
Caputa PFredriksson HHansson MAndersson SAlvandpour ASvensson C(2004)An Extended Transition Energy Cost Model for Buses in Deep Submicron TechnologiesIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-30205-6_87(849-858)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30205-6_87

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