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HAPPY: Hybrid Address-based Page Policy in DRAMs

Authors:

Mohsen Ghasempour,

Jim D. Garside,

Mikel LujánAuthors Info & Claims

MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

Pages 311 - 321

https://doi.org/10.1145/2989081.2989101

Published: 03 October 2016 Publication History

Abstract

Memory controllers have used static page closure policies to decide whether a row should be left open, open-page policy, or closed immediately, close-page policy, after the row has been accessed. The appropriate choice for a particular access can reduce the average memory latency. However, since application access patterns change at run time, static page policies cannot guarantee to deliver optimum execution time. Hybrid page policies have been investigated as a means of covering these dynamic scenarios and are now implemented in state-of-the-art processors. Hybrid page policies switch between open-page and close-page policies while the application is running, by monitoring the access pattern of row hits/conflicts and predicting future behavior. Unfortunately, as the size of DRAM memory increases, fine-grain tracking and analysis of memory access patterns does not remain practical.

We propose a compact memory address-based encoding technique which can improve or maintain the performance of DRAMs page closure predictors while reducing the hardware overhead in comparison with state-of-the-art techniques. As a case study, we integrate our technique, HAPPY, with a state-of-the-art Intel-adaptive monitor (e.g. part of the Intel Xeon X5650) and a traditional Hybrid page policy. We evaluate them across 70 memory intensive workload mixes consisting of single-thread and multi-thread applications. The experimental results show that using the HAPPY encoding applied to the Intel-adaptive page closure policy can reduce the hardware overhead by 5x for the evaluated 64 GB memory (up to 40× for a 512 GB memory) while maintaining the prediction accuracy.

References

[1]

John Ousterhout. Ramcloud.

[2]

K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. Biobench: A benchmark suite of bioinformatics applications. In Performance Analysis of Systems and Software, 2005. ISPASS 2005. IEEE International Symposium on, pages 2--9. IEEE, 2005.

Digital Library

[3]

M. Awasthi, D. W. Nellans, R. Balasubramonian, and A. Davis. Prediction based dram row-buffer management in the many-core era. In Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on, pages 183--184. IEEE, 2011.

Digital Library

[4]

C. Bienia, S. Kumar, J. P. Singh, and K. Li. The parsec benchmark suite: characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pages 72--81. ACM, 2008.

Digital Library

[5]

M. Blackmore. A quantitative analysis of memory controller page policies. Notes, 2013:01--01, 2013.

[6]

G. Brown. Ensemble learning. Encyclopedia of Machine Learning, 2010.

[7]

N. Chatterjee, R. Balasubramonian, M. Shevgoor, S. Pugsley, A. Udipi, A. Shafiee, K. Sudan, M. Awasthi, and Z. Chishti. Usimm: the utah simulated memory module. University of Utah, Tech. Rep, 2012.

[8]

K. M. Dixit. The spec benchmarks. Parallel computing, 17(10):1195--1209, 1991.

Digital Library

[9]

J. Dodd. Adaptive page management, July 11 2006. US Patent 7,076,617.

[10]

D. Huan, Z. Li, W. Hu, and Z. Liu. Processor directed dynamic page policy. In Advances in Computer Systems Architecture, pages 109--122. Springer, 2006.

Digital Library

[11]

Intel. Intel xeon processor x5650.

[12]

K. Itoh. VLSI memory chip design, volume 5. Springer New York, 2001.

[13]

B. Jacob, S. Ng, and D. Wang. Memory systems: cache, DRAM, disk. Morgan Kaufmann, 2010.

Digital Library

[14]

D. Kaseridis, J. Stuecheli, and L. K. John. Minimalist open-page: A dram page-mode scheduling policy for the many-core era. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, pages 24--35. ACM, 2011.

Digital Library

[15]

B. Keeth. DRAM circuit design: fundamental and high-speed topics, volume 13. Wiley. com, 2008.

Digital Library

[16]

C. Ma and S. Chen. A dram precharge policy based on address analysis. In Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on, pages 244--248. IEEE, 2007.

Digital Library

[17]

S. Miura, K. Ayukawa, and T. Watanabe. A dynamic-sdram-mode-control scheme for low-power systems with a 32-bit risc cpu. In Proceedings of the 2001 international symposium on Low power electronics and design, pages 358--363. ACM, 2001.

Digital Library

[18]

D. Ongaro, S. M. Rumble, R. Stutsman, J. Ousterhout, and M. Rosenblum. Fast crash recovery in ramcloud. In Proceedings of the Twenty-Third ACM Symposium on Operating Systems Principles, pages 29--41. ACM, 2011.

Digital Library

[19]

J. Ousterhout, P. Agrawal, D. Erickson, C. Kozyrakis, J. Leverich, D. Mazières, S. Mitra, A. Narayanan, G. Parulkar, M. Rosenblum, et al. The case for ramclouds: scalable high-performance storage entirely in dram. ACM SIGOPS Operating Systems Review, 43(4):92--105, 2010.

Digital Library

[20]

S.-I. Park and I.-C. Park. History-based memory mode prediction for improving memory performance. In Circuits and Systems, 2003. ISCAS'03. Proceedings of the 2003 International Symposium on, volume 5, pages V--185. IEEE, 2003.

[21]

Rajinder Gill. Everything you always wanted to know about sdram memory but were afraid to ask.

[22]

R. C. Schumann. Design of the 21174 memory controller for digital personal workstations. Digital Technical Journal, 9:57--70, 1997.

Digital Library

[23]

V. Stanković and N. Milenković. Access latency reduction in contemporary dram memories. Facta universitatis-series: Electronics and Energetics, 17(1):81--97, 2004.

[24]

V. Stankovic and N. Milenkovic. Dram controller with a complete predictor: Preliminary results. In Telecommunications in Modern Satellite, Cable and Broadcasting Services, 2005. 7th International Conference on, volume 2, pages 593--596. IEEE, 2005.

[25]

V. V. Stankovic and N. Z. Milenkovic. Dram controller with a close-page predictor. In Computer as a Tool, 2005. EUROCON 2005. The International Conference on, volume 1, pages 693--696. IEEE, 2005.

[26]

Y. Xu, A. S. Agarwal, and B. T. Davis. Prediction in dynamic sdram controller policies. In Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 128--138. Springer, 2009.

Digital Library

[27]

Z. Zhang, Z. Zhu, and X. Zhang. A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. In Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, pages 32--41. ACM, 2000.

Digital Library

Cited By

Alawneh TSharadqh AAl Sharah AAwada EAlkasassbeh JAl-Rawashdeh AAl-Qaisi A(2024)A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM SystemsIEEE Access10.1109/ACCESS.2024.351217612(182998-183023)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3512176
Rafique MZhu Z(2022)Dynamic Page Policy Using Perceptron LearningProceedings of the 2022 International Symposium on Memory Systems10.1145/3565053.3565055(1-11)Online publication date: 3-Oct-2022
https://dl.acm.org/doi/10.1145/3565053.3565055
DeLayo DZhang KAgrawal KBender MBerry JDas RMoseley BPhillips CAgrawal KLee I(2022)Automatic HBM ManagementProceedings of the 34th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3490148.3538570(147-159)Online publication date: 11-Jul-2022
https://dl.acm.org/doi/10.1145/3490148.3538570
Show More Cited By

HAPPY: Hybrid Address-based Page Policy in DRAMs
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

October 2016

463 pages

ISBN:9781450343053

DOI:10.1145/2989081

General Chair:
Bruce Jacob
University of Maryland

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 October 2016

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MEMSYS '16

MEMSYS '16: The Second International Symposium on Memory Systems

October 3 - 6, 2016

VA, Alexandria, USA

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Cited By

Alawneh TSharadqh AAl Sharah AAwada EAlkasassbeh JAl-Rawashdeh AAl-Qaisi A(2024)A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM SystemsIEEE Access10.1109/ACCESS.2024.351217612(182998-183023)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3512176
Rafique MZhu Z(2022)Dynamic Page Policy Using Perceptron LearningProceedings of the 2022 International Symposium on Memory Systems10.1145/3565053.3565055(1-11)Online publication date: 3-Oct-2022
https://dl.acm.org/doi/10.1145/3565053.3565055
DeLayo DZhang KAgrawal KBender MBerry JDas RMoseley BPhillips CAgrawal KLee I(2022)Automatic HBM ManagementProceedings of the 34th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3490148.3538570(147-159)Online publication date: 11-Jul-2022
https://dl.acm.org/doi/10.1145/3490148.3538570
Mahdavi NRazaghian FFarbeh H(2022)Data block manipulation for error rate reduction in STT-MRAM based main memoryThe Journal of Supercomputing10.1007/s11227-022-04394-778:11(13342-13372)Online publication date: 17-Mar-2022
https://doi.org/10.1007/s11227-022-04394-7
Rafique MZhu Z(2021)Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2020.304485632:11(2734-2747)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TPDS.2020.3044856
Rafique MZhu Z(2019)FAPS-3DProceedings of the International Symposium on Memory Systems10.1145/3357526.3357540(373-382)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357540
Alawneh T(2019)A Dynamic Row-Buffer Management Policy for Multimedia Applications2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/EMPDP.2019.8671566(148-157)Online publication date: Feb-2019
https://doi.org/10.1109/EMPDP.2019.8671566
Wang HJog A(2019)Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN.2019.00046(362-374)Online publication date: Jun-2019
https://doi.org/10.1109/DSN.2019.00046
Srikanth SSubramanian LSubramoney SConte TWang HJacob B(2018)Tackling memory access latency through DRAM row managementProceedings of the International Symposium on Memory Systems10.1145/3240302.3240314(137-147)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240314
Aboutalebi ADuan L(2017)Enabling reliable main memory using STT-MRAM via restore-aware memory managementProceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion10.1145/3125501.3125517(1-2)Online publication date: 15-Oct-2017
https://dl.acm.org/doi/10.1145/3125501.3125517
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