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ATPG tools for delay faults at the functional level

Authors:

S. TragoudasAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 7, Issue 1

Pages 33 - 57

https://doi.org/10.1145/504914.504916

Published: 01 January 2002 Publication History

Abstract

We present an ATPG tool for functional delay faults which applies to the single-input transition (SIT) and the multi-input transition (MIT) fault models, and is based on Reduced Ordered Binary Decision Diagrams (ROBDDs). We are able, for the first time, to identify all faults that do not have any SIT tests, and generate all SIT tests for nonredundant faults in combinational circuits. We also provide methodologies for efficient generation of MIT tests. Our experimental results on the ISCAS'85 benchmarks is by far superior to existing methods as well as a Satisfiability-based tool that we have developed for comparative purposes. The presented tool, coupled with advancements in path delay fault coverage, shows that both the SIT and MIT functional models are very useful in ATPG for robust path delay faults for synthesized circuits.

References

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Cited By

Raulamo-Jurvanen P(2017)Decision Support for Selecting Tools for Software Test AutomationACM SIGSOFT Software Engineering Notes10.1145/3011286.301130441:6(1-5)Online publication date: 5-Jan-2017
https://dl.acm.org/doi/10.1145/3011286.3011304
Bolchini CMichael MMiele ANeophytou S(2017)Dependability ThreatsDependable Multicore Architectures at Nanoscale10.1007/978-3-319-54422-9_2(37-92)Online publication date: 30-Aug-2017
https://doi.org/10.1007/978-3-319-54422-9_2
Neophytou SMichael M(2010)Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computers10.1109/TC.2009.17859:3(301-316)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.178
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 7, Issue 1

January 2002

230 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/504914

Issue’s Table of Contents

Copyright © 2002 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 January 2002

Published in TODAES Volume 7, Issue 1

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Cited By

Raulamo-Jurvanen P(2017)Decision Support for Selecting Tools for Software Test AutomationACM SIGSOFT Software Engineering Notes10.1145/3011286.301130441:6(1-5)Online publication date: 5-Jan-2017
https://dl.acm.org/doi/10.1145/3011286.3011304
Bolchini CMichael MMiele ANeophytou S(2017)Dependability ThreatsDependable Multicore Architectures at Nanoscale10.1007/978-3-319-54422-9_2(37-92)Online publication date: 30-Aug-2017
https://doi.org/10.1007/978-3-319-54422-9_2
Neophytou SMichael M(2010)Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computers10.1109/TC.2009.17859:3(301-316)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.178
Bareisa EJusas VMotiejunas KSeinauskas R(2009)Functional delay test generation based on software prototypeMicroelectronics Reliability10.1016/j.microrel.2009.06.05049:12(1578-1585)Online publication date: Dec-2009
https://doi.org/10.1016/j.microrel.2009.06.050
Bareia EJusas VMotiejunas Keinauskas R(2008)Development of Functional Delay TestsProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.11(626-632)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.11
Bareisa EJusas VMotiejunas KSeinauskas R(2008)Test generation at the algorithm-level for gate-level fault coverageMicroelectronics Reliability10.1016/j.microrel.2008.03.01748:7(1093-1101)Online publication date: Jul-2008
https://doi.org/10.1016/j.microrel.2008.03.017
Bareiša EJusas VMotiejūnas KŠeinauskas R(2007)Functional Test Generation Based on Combined Random and Deterministic Search MethodsInformatica10.5555/1413889.141389018:1(3-26)Online publication date: 1-Jan-2007
https://dl.acm.org/doi/10.5555/1413889.1413890
Bareisa EJusas VMotiejunas KSeinauskas R(2007)The Criteria of Functional Delay Test Quality Assessment10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341470(207-214)Online publication date: Aug-2007
https://doi.org/10.1109/DSD.2007.4341470
Bareisa EJusas VMotiejunas KSeinauskas R(2007)Transition Faults Testing Based on Functional Delay Tests2007 IEEE Design and Diagnostics of Electronic Circuits and Systems10.1109/DDECS.2007.4295315(1-5)Online publication date: Apr-2007
https://doi.org/10.1109/DDECS.2007.4295315
Padmanaban STragoudas S(2006)Implicit grading of multiple path delay faultsACM Transactions on Design Automation of Electronic Systems10.1145/1142155.114216011:2(346-361)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.1145/1142155.1142160
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