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Path delay fault testing using test points

Authors:

S. Tragoudas,

N. DennyAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8, Issue 1

Pages 1 - 10

https://doi.org/10.1145/606603.606604

Published: 01 January 2003 Publication History

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Abstract

Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more accuracy in testing, it is proposed that test points should be inserted with the additional constraint that every path has a bounded number of test points. A polynomial time solvable integer linear programming (ILP) formulation serves as the basis for the presented test placement methodology. Due to the ILP's global optimization property we achieve results that are comparable to those by an existing greedy technique for the less constrained test point placement problem.

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Cited By

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Siebert MGramatová E(2013)Delay Fault Coverage Increasing in Digital CircuitsProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.127(475-478)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.127
Jing-bo SGuang-sheng MXiao-xiao L(2006)State-of-art of delay testing2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design10.1109/CAIDCD.2006.329360(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/CAIDCD.2006.329360

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Path delay fault testing using test points

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Reviews

Reviewer: Festus Gail Gray

An interesting theoretical problem is addressed in this paper: when inserting exactly one test point in each physical path in a circuit (thereby dividing each physical path into two segments, and partitioning the circuit into two disjoint pieces), where should the test points be located so as to minimize the total number of paths in the modified circuit__?__ The authors present a polynomial time integer linear programming solution to the problem. They also assume that each test point is both controllable and observable, and that the test points are connected into a scan chain, for use in applying test vectors and observing test results. When compared to the algorithm in Pomeranz and Reddy [1], the new algorithm inserts fewer test points per path (which places fewer demands on the operational test clock, and tends to reduce the complexity of the testing procedure), but generates many more paths most of the time (which increases test time, and tends to increase the complexity of the testing procedure). In some instances, the number of paths increased by more than a factor of ten. Since the complexity of the test application algorithm increases in complexity exponentially with the number of paths, it is not clear exactly when it would be a good engineering decision to use the new algorithm. In addition, the full Pomeranz and Reddy algorithm was not implemented for testing, so the comparison may not be valid. Online Computing Reviews Service

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 8, Issue 1

January 2003

139 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/606603

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Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 January 2003

Published in TODAES Volume 8, Issue 1

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Cited By

View all

Siebert MGramatová E(2013)Delay Fault Coverage Increasing in Digital CircuitsProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.127(475-478)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.127
Jing-bo SGuang-sheng MXiao-xiao L(2006)State-of-art of delay testing2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design10.1109/CAIDCD.2006.329360(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/CAIDCD.2006.329360

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Cited By

Index Terms

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ATPG tools for delay faults at the functional level

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Path Delay Testing: Variable-Clock Versus Rated-Clock

Reviews

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