Article

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

Authors:

Rongtian Zhang,

Kaushik Roy,

David JanesAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 213 - 218

https://doi.org/10.1145/383082.383136

Published: 06 August 2001 Publication History

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Bindal AHamedi-Hagh SBindal AHamedi-Hagh S(2016)Dual Work Function Silicon Nanowire MOS TransistorsSilicon Nanowire Transistors10.1007/978-3-319-27177-4_1(1-26)Online publication date: 24-Feb-2016
https://doi.org/10.1007/978-3-319-27177-4_1
Veera Boopathy E Raghul G. Karthick K. (2015)Low power and high performance MOSFET2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)10.1109/VLSI-SATA.2015.7050455(1-5)Online publication date: Jan-2015
https://doi.org/10.1109/VLSI-SATA.2015.7050455
Manorama Shrivastava PAkashe S(2013)Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology2013 7th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2013.6481167(301-306)Online publication date: Jan-2013
https://doi.org/10.1109/ISCO.2013.6481167
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Index Terms

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
    2. Semiconductor memory

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Information

Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Bindal AHamedi-Hagh SBindal AHamedi-Hagh S(2016)Dual Work Function Silicon Nanowire MOS TransistorsSilicon Nanowire Transistors10.1007/978-3-319-27177-4_1(1-26)Online publication date: 24-Feb-2016
https://doi.org/10.1007/978-3-319-27177-4_1
Veera Boopathy E Raghul G. Karthick K. (2015)Low power and high performance MOSFET2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)10.1109/VLSI-SATA.2015.7050455(1-5)Online publication date: Jan-2015
https://doi.org/10.1109/VLSI-SATA.2015.7050455
Manorama Shrivastava PAkashe S(2013)Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology2013 7th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2013.6481167(301-306)Online publication date: Jan-2013
https://doi.org/10.1109/ISCO.2013.6481167
Bindal AHamedi-Hagh S(2007)The design of a new spiking neuron using dual work function silicon nanowire transistorsNanotechnology10.1088/0957-4484/18/9/09520118:9(095201)Online publication date: 24-Jan-2007
https://doi.org/10.1088/0957-4484/18/9/095201
Bindal AHamedi-Hagh S(2006)The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuitsNanotechnology10.1088/0957-4484/17/17/01017:17(4340-4351)Online publication date: 11-Aug-2006
https://doi.org/10.1088/0957-4484/17/17/010
Kim KDas KJoshi RChuang C(2005)Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and CircuitsIEEE Transactions on Electron Devices10.1109/TED.2005.84631752:5(980-986)Online publication date: May-2005
https://doi.org/10.1109/TED.2005.846317
Kim KDas KJoshi RChuang CJoshi RChoi KTiwari VRoy K(2004)Nanoscale CMOS circuit leakage power reduction by double-gate deviceProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013267(102-107)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013267
Fried DDuster JKornegay K(2004)High-Performance P-Type Independent-Gate FinFETsIEEE Electron Device Letters10.1109/LED.2004.82516025:4(199-201)Online publication date: Apr-2004
https://doi.org/10.1109/LED.2004.825160
Pacha CSchmal ASchulz TGöttsche RSteinhögl W(2003)Evaluation of circuit performance of ultra-thin-body SOI CMOSSolid-State Electronics10.1016/S0038-1101(03)00040-647:7(1205-1211)Online publication date: Jul-2003
https://doi.org/10.1016/S0038-1101(03)00040-6
Fossum JLixin Ge Meng-Hsueh Chiang (2002)Speed superiority of scaled double-gate CMOSIEEE Transactions on Electron Devices10.1109/16.99858849:5(808-811)Online publication date: May-2002
https://doi.org/10.1109/16.998588
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Double-gate SOI devices for low-power and high-performance applications

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime