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A self-optimizing embedded microprocessor using a loop table for low power

Published: 06 August 2001 Publication History
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References

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Bellas, N.; Hajj, I.; Polychronopoulos, C.; Stamoulis, G. Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. International Conference on Computer Design, pp. 378-383, 1999.
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Fisher, J.A. Customized Instruction-Sets for Embedded Processors. Design Automation Conference, pp. 253-257, 1999.
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Friendly, D., S. Patel, Y. Patt. Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. ACM/IEEE International Symposium on Microarchitecture, 1998.
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Gonzalez, R.E. Xtensa: A Configurable and Extensible Processor. IEEE Micro, pp. 60-70, 2000. Also see Tensillica Corp., http://www.tensillica.com.
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Ishihara, T., H. Yasuura. A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. Design Automation and Test in Europe, March 2000.
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Kiefendorff, K. Transistor Budgets Go Ballistic. Microprocessor Report, Volume 12, Number 10, August 1998, pp. 34-43.
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Kin, J., M. Gupta, W. Mangione-Smith. The Filter Cache: An Energy Efficient Memory Structure. International Symposium on Microarchitecture, pp. 184-193, December 1997.
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Klaiber, A. The Technology Behind Crusoe Processors. Transmeta Corporation White Paper, January 2000.
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Kucukcakar, K. An ASIP Design Methodology for Embedded Systems. Int. Workshop on Hardware/Software Codesign, pp. 17-21, 1999.
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Lee, L. H., B. Moyer, J. Arends. Instruction Fetch Energy Reduction Using Loop Caches For Embedded Applications with Small Tight Loops. International Symposium On Low Power Electronics and Design, 1999.
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Malik, A., B. Moyer, D. Cermak. A Low Power Unified Cache Architecture Providing Power and Performance Flexibility. Int. Symposium on Low Power Electronics and Design, pp. 241-243, 2000.
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Stitt, G., F. Vahid, T. Givargis and R. Lysecky. A First Step Towards an Architecture Tuning Methodology for Llow Power. International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2000.
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Vahid, F. and T. Givargis. Platform Tuning for Embedded Systems Design. IEEE Computer, Vol. 34, No. 3, pp. 112-114, March 2001. Also see The UCR Dalton Project, http://www.cs.ucr.edu/~dalton.

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          cover image ACM Conferences
          ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design
          August 2001
          393 pages
          ISBN:1581133715
          DOI:10.1145/383082
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          New York, NY, United States

          Publication History

          Published: 06 August 2001

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          Author Tags

          1. cores
          2. embedded systems
          3. low-power
          4. parameterized architectures
          5. platforms
          6. self-optimizing architecture
          7. system-on-a-chip
          8. tuning

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          ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;
          Overall Acceptance Rate 398 of 1,159 submissions, 34%

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          • (2008)Power optimization of embedded real-time systems and their adaptabilityAutomatic Control and Computer Sciences10.3103/S014641160803007342:3(153-162)Online publication date: 27-Jul-2008
          • (2005)Profiling soft-core processor applications for hardware/software partitioningJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2004.11.00251:5(315-329)Online publication date: 1-May-2005
          • (2005)A systematic approach to profiling for hardware/software partitioningComputers and Electrical Engineering10.1016/j.compeleceng.2004.07.00331:2(93-111)Online publication date: 1-Mar-2005
          • (2005)Designing low-power embedded software for mass-produced microprocessor by using a loop table in on-chip memoryProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_7(59-68)Online publication date: 21-Sep-2005
          • (2002)Parametric architecture for implementing multimedia algorithms2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628)10.1109/ICDSP.2002.1028322(1261-1264)Online publication date: 2002

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