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PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method

Authors:

Yuan XieAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1191 - 1196

https://doi.org/10.1145/2228360.2228580

Published: 03 June 2012 Publication History

Abstract

Process variations and thermal fluctuations significantly affect the write reliability of spin-transfer torque random access memory (STT-RAM). Traditionally, modeling the impacts of these variations on STT-RAM designs requires expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps. In this paper, we propose a fast and scalable semi-analytical simulation method--PS3-RAM, for STT-RAM write reliability analysis. Simulation results show that PS3-RAM offers excellent agreement with the conventional simulation method without running the costly macro-magnetic and SPICE simulations. Our method can accurately estimate the STT-RAM write error rate at both MTJ switching directions under different temperatures while receiving a speedup of multiple orders of magnitude (five order or more). PS3-RAM shows great potentials in the STT-RAM reliability analysis at the early design stage of memory or micro-architecture.

References

[1]

BSIM. http://www-device.eecs.berkeley.edu/bsim3/. UC Berkeley.

[2]

X. Cong, N. Dimin, Z. Xiaochun, K. H. Seung, N. Matt, and Y. Xie. "Device Architecture Co-Optimization of STT-RAM Based Memory for Low Power Embedded Systems". In ICCAD, pages 463--470, Nov 2011.

Digital Library

[3]

P. Doubilet, C. Begg, M. Weinstein, P. Braun, and B. McNeil. "Probabilistic Sensitivity Analysis Using Monte Carlo Simulation. A Practical Approach". 1985.

[4]

F. Harris. "On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform". Proceedings of the IEEE, 66(1):51--83, Jan. 1978.

[5]

J. Li, H. Liu, S. Salahuddin, and K. Roy. "Variation-Tolerant Spin-Torque Transfer (STT) MRAM Array for Yield Enhancement". In CICC, pages 193--196, Sep. 2008.

[6]

P. T. M. (PTM). http://www.eas.asu.edu/ptm/. ASU.

[7]

B. Sheu, D. Scharfetter, P.-K. Ko, and M.-C. Jeng. "BSIM: Berkeley short-channel IGFET model for MOS transistors". JSSC, 22(4):558--566, Aug 1987.

[8]

R. Singha, A. Balijepalli, A. Subramaniam, F. Liu, and S. Nassif. "Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation". In 44th DAC, pages 823--828, June 2007.

Digital Library

[9]

C. W. Smullen, A. Nigam, S. Gurumurthi, and M. R. Stan. "The STeTSiMS STT-RAM Simulation and Modeling System". In ICCAD, pages 318--325, Nov 2011.

Digital Library

[10]

G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs". In 15th HPCA, pages 239--249. IEEE, 2009.

[11]

X. Wang, Y. Zheng, H. Xi, and D. Dimitrov. "Thermal Fluctuation Effects on Spin Torque Induced Switching: Mean and Variations". JAP, 103(3):034507-034507-4, Feb. 2008.

[12]

W. Xu, Y. Chen, X. Wang, and T. Zhang. "Improving STT MRAM storage density through smaller-than-worst-case transistor sizing". In 46th DAC, pages 87--90, July 2009.

Digital Library

[13]

W. Xu, H. Sun, Y. Chen, and T. Zhang. "Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT-RAM)". In IEEE Trans. on VLSI System, pages 483--493. IEEE, 2011.

Digital Library

[14]

Y. Ye, F. Liu, S. Nassif, and Y. Cao. "Statistical Modeling and Simulation of Threshold Variation under Dopant Fluctuations and Line-Edge Roughness". In 45th DAC, pages 900--905, June 2008.

Digital Library

[15]

Y. Zhang, X. Wang, and Y. Chen. "STT-RAM Cell Design Optimization for Persistent and Non-Persistent Error rate Reduction: A statistcal Design View". In ICCAD, pages 471--477, Nov. 2011.

Digital Library

[16]

P. Zhou, B. Zhao, J. Yang, and Y. Zhang. "Energy Reduction for STT-RAM Using Early Write Termination". In ICCAD, pages 264--268. ACM, 2009.

Digital Library

Cited By

Kline DLongofono SOllivier SHiggins EMelhem RJones A(2019)PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2019.00049(396-409)Online publication date: Oct-2019
https://doi.org/10.1109/MASCOTS.2019.00049
Ghaemi SAhmadpour IArdebili MFarbeh H(2019)Sleepy-LRUThe Journal of Supercomputing10.1007/s11227-019-02758-075:7(3945-3974)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s11227-019-02758-0
Li BPei YWen W(2018)Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAMACM Journal on Emerging Technologies in Computing Systems10.1145/315483614:1(1-20)Online publication date: 8-Mar-2018
https://dl.acm.org/doi/10.1145/3154836
Show More Cited By

Index Terms

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
1. Hardware
  1. Hardware validation

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Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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National Science Foundation

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DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Kline DLongofono SOllivier SHiggins EMelhem RJones A(2019)PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2019.00049(396-409)Online publication date: Oct-2019
https://doi.org/10.1109/MASCOTS.2019.00049
Ghaemi SAhmadpour IArdebili MFarbeh H(2019)Sleepy-LRUThe Journal of Supercomputing10.1007/s11227-019-02758-075:7(3945-3974)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s11227-019-02758-0
Li BPei YWen W(2018)Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAMACM Journal on Emerging Technologies in Computing Systems10.1145/315483614:1(1-20)Online publication date: 8-Mar-2018
https://dl.acm.org/doi/10.1145/3154836
Liu ZMao MLiu TWang XWen WChen YLi HWang DPei YGe N(2018)TriZoneIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.278386037:10(1985-1998)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2783860
Zhang YYan BWang XChen Y(2017)Persistent and Nonpersistent Error Optimization for STT-RAM Cell DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261948436:7(1181-1192)Online publication date: Jul-2017
https://doi.org/10.1109/TCAD.2016.2619484
(2017) Process variation aware STT-RAM simulation tool: NVSim-VX s 2017 IEEE International Conference on IC Design and Technology (ICICDT)10.1109/ICICDT.2017.7993508(1-4)Online publication date: May-2017
https://doi.org/10.1109/ICICDT.2017.7993508
Wen WMao MLi HChen YPei YGe NFanucci LTeich J(2016)A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972108(1285-1290)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972108
Wang XMao MEken EWen WLi HChen YFanucci LTeich J(2016)Sliding basketProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971983(762-767)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971983
Eken ESong LBayram IXu CWen WXie YChen Y(2016)NVSim-VXsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898053(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898053
Long LLiu DLiang LZhu XZhong KShao ZSha E(2016)Morphable Resistive Memory Optimization for Mobile VirtualizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.249526435:6(891-904)Online publication date: Jun-2016
https://doi.org/10.1109/TCAD.2015.2495264
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